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  1. Index: a23_decode.v
  2. ===================================================================
  3. --- a23_decode.v (revision 103)
  4. +++ a23_decode.v (working copy)
  5. @@ -61,64 +61,64 @@
  6. // --------------------------------------------------
  7. // Control signals to execute stage
  8. // --------------------------------------------------
  9. -output reg [31:0] o_read_data = 1'd0,
  10. -output reg [4:0] o_read_data_alignment = 1'd0, // 2 LSBs of read address used for calculating shift in LDRB ops
  11. +output reg [31:0] o_read_data,
  12. +output reg [4:0] o_read_data_alignment, // 2 LSBs of read address used for calculating shift in LDRB ops
  13.  
  14. -output reg [31:0] o_imm32 = 'd0,
  15. -output reg [4:0] o_imm_shift_amount = 'd0,
  16. -output reg o_shift_imm_zero = 'd0,
  17. -output reg [3:0] o_condition = 4'he, // 4'he = al
  18. -output reg o_exclusive_exec = 'd0, // exclusive access request ( swap instruction )
  19. -output reg o_data_access_exec = 'd0, // high means the memory access is a read
  20. +output reg [31:0] o_imm32,
  21. +output reg [4:0] o_imm_shift_amount,
  22. +output reg o_shift_imm_zero,
  23. +output reg [3:0] o_condition, // 4'he = al
  24. +output reg o_exclusive_exec, // exclusive access request ( swap instruction )
  25. +output reg o_data_access_exec, // high means the memory access is a read
  26. // read or write, low for instruction
  27. -output reg [1:0] o_status_bits_mode = 2'b11, // SVC
  28. -output reg o_status_bits_irq_mask = 1'd1,
  29. -output reg o_status_bits_firq_mask = 1'd1,
  30. +output reg [1:0] o_status_bits_mode, // SVC
  31. +output reg o_status_bits_irq_mask,
  32. +output reg o_status_bits_firq_mask,
  33.  
  34. -output reg [3:0] o_rm_sel = 'd0,
  35. -output reg [3:0] o_rds_sel = 'd0,
  36. -output reg [3:0] o_rn_sel = 'd0,
  37. +output reg [3:0] o_rm_sel,
  38. +output reg [3:0] o_rds_sel,
  39. +output reg [3:0] o_rn_sel,
  40. output [3:0] o_rm_sel_nxt,
  41. output [3:0] o_rds_sel_nxt,
  42. output [3:0] o_rn_sel_nxt,
  43. -output reg [1:0] o_barrel_shift_amount_sel = 'd0,
  44. -output reg [1:0] o_barrel_shift_data_sel = 'd0,
  45. -output reg [1:0] o_barrel_shift_function = 'd0,
  46. -output reg [8:0] o_alu_function = 'd0,
  47. -output reg [1:0] o_multiply_function = 'd0,
  48. -output reg [2:0] o_interrupt_vector_sel = 'd0,
  49. -output reg [3:0] o_address_sel = 4'd2,
  50. -output reg [1:0] o_pc_sel = 2'd2,
  51. -output reg [1:0] o_byte_enable_sel = 'd0, // byte, halfword or word write
  52. -output reg [2:0] o_status_bits_sel = 'd0,
  53. +output reg [1:0] o_barrel_shift_amount_sel,
  54. +output reg [1:0] o_barrel_shift_data_sel,
  55. +output reg [1:0] o_barrel_shift_function,
  56. +output reg [8:0] o_alu_function,
  57. +output reg [1:0] o_multiply_function,
  58. +output reg [2:0] o_interrupt_vector_sel,
  59. +output reg [3:0] o_address_sel,
  60. +output reg [1:0] o_pc_sel,
  61. +output reg [1:0] o_byte_enable_sel, // byte, halfword or word write
  62. +output reg [2:0] o_status_bits_sel,
  63. output reg [2:0] o_reg_write_sel,
  64. output reg o_user_mode_regs_load,
  65. output reg o_user_mode_regs_store_nxt,
  66. output reg o_firq_not_user_mode,
  67.  
  68. -output reg o_write_data_wen = 'd0,
  69. -output reg o_base_address_wen = 'd0, // save LDM base address register
  70. +output reg o_write_data_wen,
  71. +output reg o_base_address_wen, // save LDM base address register
  72. // in case of data abort
  73. -output reg o_pc_wen = 1'd1,
  74. -output reg [14:0] o_reg_bank_wen = 'd0,
  75. -output reg [3:0] o_reg_bank_wsel = 'd0,
  76. -output reg o_status_bits_flags_wen = 'd0,
  77. -output reg o_status_bits_mode_wen = 'd0,
  78. -output reg o_status_bits_irq_mask_wen = 'd0,
  79. -output reg o_status_bits_firq_mask_wen = 'd0,
  80. +output reg o_pc_wen,
  81. +output reg [14:0] o_reg_bank_wen,
  82. +output reg [3:0] o_reg_bank_wsel,
  83. +output reg o_status_bits_flags_wen,
  84. +output reg o_status_bits_mode_wen,
  85. +output reg o_status_bits_irq_mask_wen,
  86. +output reg o_status_bits_firq_mask_wen,
  87.  
  88. // --------------------------------------------------
  89. // Co-Processor interface
  90. // --------------------------------------------------
  91. -output reg [2:0] o_copro_opcode1 = 'd0,
  92. -output reg [2:0] o_copro_opcode2 = 'd0,
  93. -output reg [3:0] o_copro_crn = 'd0,
  94. -output reg [3:0] o_copro_crm = 'd0,
  95. -output reg [3:0] o_copro_num = 'd0,
  96. -output reg [1:0] o_copro_operation = 'd0, // 0 = no operation,
  97. +output reg [2:0] o_copro_opcode1,
  98. +output reg [2:0] o_copro_opcode2,
  99. +output reg [3:0] o_copro_crn,
  100. +output reg [3:0] o_copro_crm,
  101. +output reg [3:0] o_copro_num,
  102. +output reg [1:0] o_copro_operation, // 0 = no operation,
  103. // 1 = Move to Amber Core Register from Coprocessor
  104. // 2 = Move to Coprocessor from Amber Core Register
  105. -output reg o_copro_write_data_wen = 'd0,
  106. +output reg o_copro_write_data_wen,
  107. output o_iabt_trigger,
  108. output [31:0] o_iabt_address,
  109. output [7:0] o_iabt_status,
  110. @@ -1693,6 +1693,51 @@
  111. end
  112. //synopsys translate_on
  113.  
  114. +initial begin
  115. +
  116. + o_read_data = 1'd0;
  117. + o_read_data_alignment = 1'd0; // 2 LSBs of read address used for calculating shift in LDRB ops
  118. + o_imm32 = 32'd0;
  119. + o_imm_shift_amount = 5'd0;
  120. + o_shift_imm_zero = 1'd0;
  121. + o_condition = 4'he; // 4'he = al
  122. + o_exclusive_exec = 1'd0; // exclusive access request ( swap instruction )
  123. + o_data_access_exec = 1'd0; // high means the memory access is a read
  124. + o_status_bits_mode = 2'b11; // SVC
  125. + o_status_bits_irq_mask = 1'd1;
  126. + o_status_bits_firq_mask = 1'd1;
  127. + o_rm_sel = 4'd0;
  128. + o_rds_sel = 4'd0;
  129. + o_rn_sel = 4'd0;
  130. + o_barrel_shift_amount_sel = 2'd0;
  131. + o_barrel_shift_data_sel = 2'd0;
  132. + o_barrel_shift_function = 2'd0;
  133. + o_alu_function = 9'd0;
  134. + o_multiply_function = 2'd0;
  135. + o_interrupt_vector_sel = 3'd0;
  136. + o_address_sel = 4'd2;
  137. + o_pc_sel = 2'd2;
  138. + o_byte_enable_sel = 2'd0; // byte; halfword or word write
  139. + o_status_bits_sel = 3'd0;
  140. + o_write_data_wen = 1'd0;
  141. + o_base_address_wen = 1'd0; // save LDM base address register
  142. + o_pc_wen = 1'd1;
  143. + o_reg_bank_wen = 15'd0;
  144. + o_reg_bank_wsel = 4'd0;
  145. + o_status_bits_flags_wen = 1'd0;
  146. + o_status_bits_mode_wen = 1'd0;
  147. + o_status_bits_irq_mask_wen = 1'd0;
  148. + o_status_bits_firq_mask_wen = 1'd0;
  149. + o_copro_opcode1 = 3'd0;
  150. + o_copro_opcode2 = 3'd0;
  151. + o_copro_crn = 4'd0;
  152. + o_copro_crm = 4'd0;
  153. + o_copro_num = 4'd0;
  154. + o_copro_operation = 2'd0; // 0 = no operation;
  155. + o_copro_write_data_wen = 1'd0;
  156. +
  157. +
  158. +end
  159. endmodule
  160.  
  161.  
  162. Index: a23_multiply.v
  163. ===================================================================
  164. --- a23_multiply.v (revision 103)
  165. +++ a23_multiply.v (working copy)
  166. @@ -64,7 +64,7 @@
  167.  
  168. output [31:0] o_out,
  169. output [1:0] o_flags, // [1] = N, [0] = Z
  170. -output reg o_done = 'd0 // goes high 2 cycles before completion
  171. +output reg o_done
  172. );
  173.  
  174.  
  175. @@ -195,6 +195,12 @@
  176. assign o_out = product[32:1];
  177. assign o_flags = flags_nxt;
  178.  
  179. +initial begin
  180. +
  181. + o_done = 1'd0; // goes high 2 cycles before completion
  182. +
  183. +end
  184. +
  185. endmodule
  186.  
  187.  
  188. Index: a23_execute.v
  189. ===================================================================
  190. --- a23_execute.v (revision 103)
  191. +++ a23_execute.v (working copy)
  192. @@ -55,19 +55,19 @@
  193. // high means the memory access is a read
  194. // read or write, low for instruction
  195.  
  196. -output reg [31:0] o_copro_write_data = 'd0,
  197. -output reg [31:0] o_write_data = 'd0,
  198. -output reg [31:0] o_address = 32'hdead_dead,
  199. -output reg o_adex = 'd0, // Address Exception
  200. -output reg o_address_valid = 'd0, // Prevents the reset address value being a
  201. +output reg [31:0] o_copro_write_data,
  202. +output reg [31:0] o_write_data,
  203. +output reg [31:0] o_address,
  204. +output reg o_adex, // Address Exception
  205. +output reg o_address_valid, // Prevents the reset address value being a
  206. // wishbone access
  207. output [31:0] o_address_nxt, // un-registered version of address to the
  208. // cache rams address ports
  209. -output reg o_priviledged = 'd0, // Priviledged access
  210. -output reg o_exclusive = 'd0, // swap access
  211. -output reg o_write_enable = 'd0,
  212. -output reg [3:0] o_byte_enable = 'd0,
  213. -output reg o_data_access = 'd0, // To Fetch stage. high = data fetch,
  214. +output reg o_priviledged, // Priviledged access
  215. +output reg o_exclusive, // swap access
  216. +output reg o_write_enable,
  217. +output reg [3:0] o_byte_enable,
  218. +output reg o_data_access, // To Fetch stage. high = data fetch,
  219. // low = instruction fetch
  220. output [31:0] o_status_bits, // Full PC will all status bits, but PC part zero'ed out
  221. output o_multiply_done,
  222. @@ -610,6 +610,21 @@
  223.  
  224. //synopsys translate_on
  225.  
  226. +initial begin
  227. +
  228. + o_copro_write_data = 32'd0;
  229. + o_write_data = 32'd0;
  230. + o_address = 32'hdead_dead;
  231. + o_adex = 1'd0; // Address Exception
  232. + o_address_valid = 1'd0; // Prevents the reset address value being a
  233. + o_priviledged = 1'd0; // Priviledged access
  234. + o_exclusive = 1'd0; // swap access
  235. + o_write_enable = 1'd0;
  236. + o_byte_enable = 4'd0;
  237. + o_data_access = 1'd0; // To Fetch stage. high = data fetch;
  238. +
  239. +
  240. +end
  241. endmodule
  242.  
  243.  
  244. Index: a23_wishbone.v
  245. ===================================================================
  246. --- a23_wishbone.v (revision 103)
  247. +++ a23_wishbone.v (working copy)
  248. @@ -73,13 +73,13 @@
  249. input i_cache_req,
  250.  
  251. // Wishbone Bus
  252. -output reg [31:0] o_wb_adr = 'd0,
  253. -output reg [3:0] o_wb_sel = 'd0,
  254. -output reg o_wb_we = 'd0,
  255. +output reg [31:0] o_wb_adr,
  256. +output reg [3:0] o_wb_sel,
  257. +output reg o_wb_we ,
  258. input [31:0] i_wb_dat,
  259. -output reg [31:0] o_wb_dat = 'd0,
  260. -output reg o_wb_cyc = 'd0,
  261. -output reg o_wb_stb = 'd0,
  262. +output reg [31:0] o_wb_dat,
  263. +output reg o_wb_cyc,
  264. +output reg o_wb_stb,
  265. input i_wb_ack,
  266. input i_wb_err
  267.  
  268. @@ -300,5 +300,16 @@
  269.  
  270. //synopsys translate_on
  271.  
  272. +initial begin
  273. +
  274. + o_wb_adr = 32'd0;
  275. + o_wb_sel = 4'd0;
  276. + o_wb_we = 1'd0;
  277. + o_wb_dat = 32'd0;
  278. + o_wb_cyc = 1'd0;
  279. + o_wb_stb = 1'd0;
  280. +
  281. +
  282. +end
  283. endmodule
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