2014-10-31 07:57:25 < clever_> i also did some strange stuff one day in my verilog
2014-10-31 07:57:44 < clever_> i wrote some dma like code, which will read ~6 bytes of ram at once, in a single clock cycle
2014-10-31 07:58:06 < clever_> turns out, 6 port ram isnt possible, so instead the SDK creates 6 seperate ram blocks
2014-10-31 07:58:17 < clever_> all share the write port
2014-10-31 07:58:29 < clever_> resource explosion!