Flashy flashy

// Module to receive USART letters from the PC and toggle
// 4 leds.
// Rafael Arce Nazario 2017

module top
(
    input wire          clk,
    input wire          ftdi_rx,
     output reg [3:0]   led = 4'b0001
);

wire uart_valid;

wire [7:0] uart_data_rx;

wire letter_a, letter_s, letter_d, letter_f;



// Combinational logic
assign letter_a = uart_valid && (uart_data_rx == 8'h61);
assign letter_s = uart_valid && (uart_data_rx == 8'h73);
assign letter_d = uart_valid && (uart_data_rx == 8'h64);
assign letter_f = uart_valid && (uart_data_rx == 8'h66);

// Module instantiation
uart_rx rx0 (
    .clk(clk),
    .rst(1'b0),
    .din(ftdi_rx),
    .data_out(uart_data_rx),
    .valid(uart_valid)
);

reg  [24:0]count = 0;
reg  speed = 32000000;



//flash rot(.f(letter_s) , .s(letter_a) , .clk(clk) , .count(count), .speed(speed) );


// Whenever the signals letter_a, etc pulse then
// toggle the corresponding output.

//always @(posedge clk)
//  begin

/*
    if (letter_a)
            led[0] <= ~led[0];

    if (letter_s)
            led[1] <= ~led[1];

    if (letter_d)
            led[2] <= ~led[2];

    if (letter_f)
            led[3] <= ~led[3];
*/
//  end

    always @(posedge clk)
        begin

        if(letter_s)
            speed <= speed << 1;

        if(letter_a)
            speed <= speed >> 1;


        count <= count + 1;
        if (count == speed)
            begin
                led <= {led[2:0], led[3]};
                count <= 0;
            end
        end

        /*
        led[0] <= out[0];

        led[1] <= out[1];

        led[2] <= out[2];

        led[3] <= out[3];


        end
        */



endmodule