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  1. // Sim6800.cpp : Defines the entry point for the console application.
  2. //
  3.  
  4. #include "stdafx.h"
  5. #include <winsock2.h>
  6.  
  7. #pragma comment(lib, "wsock32.lib")
  8.  
  9.  
  10. #define STUDENT_NUMBER "14013795"
  11.  
  12. #define IP_ADDRESS_SERVER "127.0.0.1"
  13.  
  14. #define PORT_SERVER 0x1984 // We define a port that we are going to use.
  15. #define PORT_CLIENT 0x1985 // We define a port that we are going to use.
  16.  
  17.  
  18. #define WORD unsigned short
  19. #define DWORD unsigned long
  20. #define BYTE unsigned char
  21.  
  22. #define MAX_FILENAME_SIZE 500
  23.  
  24. #define MAX_BUFFER_SIZE 500
  25.  
  26.  
  27.  
  28. SOCKADDR_IN server_addr;
  29. SOCKADDR_IN client_addr;
  30.  
  31. SOCKET sock; // This is our socket, it is the handle to the IO address to read/write packets
  32.  
  33. WSADATA data;
  34.  
  35.  
  36.  
  37.  
  38. char InputBuffer [MAX_BUFFER_SIZE];
  39.  
  40. char hex_file [MAX_BUFFER_SIZE];
  41. char trc_file [MAX_BUFFER_SIZE];
  42.  
  43.  
  44.  
  45.  
  46. //////////////////////////
  47. // Intel 6800 Registers //
  48. //////////////////////////
  49.  
  50. #define REGISTER_A 0
  51. #define REGISTER_B 1
  52.  
  53. #define FLAG_N 0x08
  54. #define FLAG_Z 0x04
  55. #define FLAG_H 0x20
  56. #define FLAG_I 0x10
  57. #define FLAG_V 0x02
  58. #define FLAG_C 0x01
  59.  
  60. BYTE Registers[2];
  61. BYTE Flags;
  62. WORD IndexRegister;
  63. WORD ProgramCounter;
  64. WORD StackPointer;
  65.  
  66. ////////////
  67. // Memory //
  68. ////////////
  69.  
  70. #define K_1 1024
  71. #define MEMORY_SIZE K_1
  72.  
  73. BYTE Memory[MEMORY_SIZE];
  74.  
  75. #define TEST_ADDRESS_1 0x00FD
  76. #define TEST_ADDRESS_2 0x00FE
  77. #define TEST_ADDRESS_3 0x00FF
  78. #define TEST_ADDRESS_4 0x0100
  79. #define TEST_ADDRESS_5 0x0101
  80.  
  81. ///////////////////////
  82. // Control variables //
  83. ///////////////////////
  84.  
  85. bool memory_in_range = true;
  86. bool halt = false;
  87.  
  88. ///////////////////////
  89. // Disassembly table //
  90. ///////////////////////
  91.  
  92. char opcode_mneumonics[][12] =
  93. {
  94. "Illegal ",
  95. "NOP ",
  96. "Illegal ",
  97. "Illegal ",
  98. "Illegal ",
  99. "Illegal ",
  100. "TAP ",
  101. "TPA ",
  102. "INX ",
  103. "DEX ",
  104. "CLV ",
  105. "SEV ",
  106. "CLC ",
  107. "SEC ",
  108. "CLI ",
  109. "SEI ",
  110.  
  111. "SBA ",
  112. "CBA ",
  113. "Illegal ",
  114. "Illegal ",
  115. "Illegal ",
  116. "Illegal ",
  117. "TAB ",
  118. "TBA ",
  119. "Illegal ",
  120. "DAA ",
  121. "Illegal ",
  122. "ABA ",
  123. "Illegal ",
  124. "Illegal ",
  125. "Illegal ",
  126. "Illegal ",
  127.  
  128. "BRA ",
  129. "Illegal ",
  130. "BHI ",
  131. "BLS ",
  132. "BCC ",
  133. "BCS ",
  134. "BNE ",
  135. "BEQ ",
  136. "BVC ",
  137. "BVS ",
  138. "BPL ",
  139. "BMI ",
  140. "BGE ",
  141. "BLT ",
  142. "BGT ",
  143. "BLE ",
  144.  
  145. "TSX ",
  146. "INS ",
  147. "PULA ",
  148. "PULB ",
  149. "DES ",
  150. "TXS ",
  151. "PSHA ",
  152. "PSHB ",
  153. "Illegal ",
  154. "RTS ",
  155. "Illegal ",
  156. "RTI ",
  157. "Illegal ",
  158. "Illegal ",
  159. "WAI ",
  160. "SWI ",
  161.  
  162. "NEGA ",
  163. "Illegal ",
  164. "Illegal ",
  165. "COMA ",
  166. "LSRA ",
  167. "Illegal ",
  168. "RORA ",
  169. "ASRA ",
  170. "ASLA ",
  171. "ROLA ",
  172. "DECA ",
  173. "Illegal ",
  174. "INCA ",
  175. "TSTA ",
  176. "Illegal ",
  177. "CLRA ",
  178.  
  179. "NEGB ",
  180. "Illegal ",
  181. "Illegal ",
  182. "COMB ",
  183. "LSRB ",
  184. "Illegal ",
  185. "RORB ",
  186. "ASRB ",
  187. "ASLB ",
  188. "ROLB ",
  189. "DECB ",
  190. "Illegal ",
  191. "INCB ",
  192. "TSTB ",
  193. "Illegal ",
  194. "CLRB ",
  195.  
  196. "NEG d,X ",
  197. "Illegal ",
  198. "Illegal ",
  199. "COM d,X ",
  200. "LSR d,X ",
  201. "Illegal ",
  202. "ROR d,X ",
  203. "ASR d,X ",
  204. "ASL d,X ",
  205. "ROL d,X ",
  206. "DEC d,X ",
  207. "Illegal ",
  208. "INC d,X ",
  209. "TST d,X ",
  210. "JMP d,X ",
  211. "CLR d,X ",
  212.  
  213. "NEG w ",
  214. "Illegal ",
  215. "Illegal ",
  216. "COM w ",
  217. "LSR w ",
  218. "Illegal ",
  219. "ROR w ",
  220. "ASR w ",
  221. "ASL w ",
  222. "ROL w ",
  223. "DEC w ",
  224. "Illegal ",
  225. "INC w ",
  226. "TST w ",
  227. "JMP w ",
  228. "CLR w ",
  229.  
  230. "SUBA #d ",
  231. "CMPA #d ",
  232. "SBCA #d ",
  233. "Illegal ",
  234. "ANDA #d ",
  235. "BITA #d ",
  236. "LDAA #d ",
  237. "Illegal ",
  238. "EORA #d ",
  239. "ADCA #d ",
  240. "ORAA #d ",
  241. "ADDA #d ",
  242. "CPX #w ",
  243. "BSR d ",
  244. "LDS #w ",
  245. "Illegal ",
  246.  
  247. "SUBA d ",
  248. "CMPA d ",
  249. "SBCA d ",
  250. "Illegal ",
  251. "ANDA d ",
  252. "BITA d ",
  253. "LDAA d ",
  254. "STAA d ",
  255. "EORA d ",
  256. "ADCA d ",
  257. "ORAA d ",
  258. "ADDA d ",
  259. "CPX d ",
  260. "Illegal ",
  261. "LDS d ",
  262. "STS d ",
  263.  
  264. "SUBA d,X ",
  265. "CMPA d,X ",
  266. "SBCA d,X ",
  267. "Illegal ",
  268. "ANDA d,X ",
  269. "BITA d,X ",
  270. "LDAA d,X ",
  271. "STAA d,X ",
  272. "EORA d,X ",
  273. "ADCA d,X ",
  274. "ORAA d,X ",
  275. "ADDA d,X ",
  276. "CPX d,X ",
  277. "JSR d,X ",
  278. "LDS d,X ",
  279. "STS d,X ",
  280.  
  281. "SUBA w ",
  282. "CMPA w ",
  283. "SBCA w ",
  284. "Illegal ",
  285. "ANDA w ",
  286. "BITA w ",
  287. "LDAA w ",
  288. "STAA w ",
  289. "EORA w ",
  290. "ADCA w ",
  291. "ORAA w ",
  292. "ADDA w ",
  293. "CPX w ",
  294. "JSR w ",
  295. "LDS w ",
  296. "STS w ",
  297.  
  298. "SUBB #d ",
  299. "CMPB #d ",
  300. "SBCB #d ",
  301. "Illegal ",
  302. "ANDB #d ",
  303. "BITB #d ",
  304. "LDAB #d ",
  305. "Illegal ",
  306. "EORB #d ",
  307. "ADCB #d ",
  308. "ORAB #d ",
  309. "ADDB #d ",
  310. "Illegal ",
  311. "Illegal ",
  312. "LDX #w ",
  313. "Illegal ",
  314.  
  315. "SUBB d ",
  316. "CMPB d ",
  317. "SBCB d ",
  318. "Illegal ",
  319. "ANDB d ",
  320. "BITB d ",
  321. "LDAB d ",
  322. "STAB d ",
  323. "EORB d ",
  324. "ADCB d ",
  325. "ORAB d ",
  326. "ADDB d ",
  327. "Illegal ",
  328. "Illegal ",
  329. "LDX d ",
  330. "STX d ",
  331.  
  332. "SUBB d,X ",
  333. "CMPB d,X ",
  334. "SBCB d,X ",
  335. "Illegal ",
  336. "ANDB d,X ",
  337. "BITB d,X ",
  338. "LDAB d,X ",
  339. "STAB d,X ",
  340. "EORB d,X ",
  341. "ADCB d,X ",
  342. "ORAB d,X ",
  343. "ADDB d,X ",
  344. "Illegal ",
  345. "Illegal ",
  346. "LDX d,X ",
  347. "STX d,X ",
  348.  
  349. "SUBB w ",
  350. "CMPB w ",
  351. "SBCB w ",
  352. "Illegal ",
  353. "ANDB w ",
  354. "BITB w ",
  355. "LDAB w ",
  356. "STAB w ",
  357. "EORB w ",
  358. "ADCB w ",
  359. "ORAB w ",
  360. "ADDB w ",
  361. "Illegal ",
  362. "Illegal ",
  363. "LDX w ",
  364. "STX w "
  365. };
  366.  
  367.  
  368.  
  369.  
  370.  
  371.  
  372.  
  373. ////////////////////////////////////////////////////////////////////////////////
  374. // Intel 6800 Simulator/Emulator (Start) //
  375. ////////////////////////////////////////////////////////////////////////////////
  376.  
  377.  
  378. BYTE fetch()
  379. {
  380. BYTE byte = 0;
  381.  
  382. if ((ProgramCounter >= 0) && (ProgramCounter <= MEMORY_SIZE))
  383. {
  384. memory_in_range = true;
  385. byte = Memory[ProgramCounter];
  386. ProgramCounter++;
  387. }
  388. else
  389. {
  390. memory_in_range = false;
  391. }
  392. return byte;
  393. }
  394.  
  395.  
  396. // Add any instruction implementing routines here...
  397.  
  398.  
  399.  
  400. void set_flag_z(BYTE inReg)
  401. {
  402. BYTE reg;
  403.  
  404. reg = inReg;
  405.  
  406. if (reg == 0) // set to zero
  407. {
  408. Flags = Flags | FLAG_Z;
  409. }
  410. else
  411. {
  412. Flags = Flags & (0xFF - FLAG_Z);
  413. }
  414. }
  415.  
  416. void set_flag_zword(WORD inReg) //zero flag word
  417. {
  418. WORD reg;
  419. reg = inReg;
  420. if (reg == 0) // set to zero
  421. {
  422. Flags = Flags | FLAG_Z;
  423. }
  424. else
  425. {
  426. Flags = Flags & (0xFF - FLAG_Z);
  427. }
  428. }
  429.  
  430.  
  431. void set_carry_flag(BYTE inReg)
  432. {
  433. WORD temp_word;
  434.  
  435. temp_word = inReg;
  436.  
  437. if(temp_word >= 0x100)
  438. {
  439. //Set Carry Flag
  440. Flags = Flags | FLAG_C;
  441. }
  442. else
  443. {
  444. //Clear Carry Flag
  445. Flags = Flags & (0xFF - FLAG_C);
  446. }
  447. }
  448.  
  449. void set_flag_n(BYTE inReg)
  450. {
  451. BYTE reg;
  452.  
  453. reg = inReg;
  454.  
  455. if ((reg & 0x80) !=0) //msbit set
  456. {
  457. Flags = Flags | FLAG_N;
  458. }
  459. else
  460. {
  461. Flags = Flags & (0xFF - FLAG_N);
  462. }
  463. }
  464.  
  465. void set_flag_nword(BYTE inReg)
  466. {
  467. WORD reg;
  468.  
  469. reg = inReg;
  470.  
  471. if ((reg & 0x8000) !=0)
  472. {
  473. Flags = Flags | FLAG_N;
  474. }
  475. else
  476. {
  477. Flags = Flags & (0xFF - FLAG_N);
  478. }
  479. }
  480.  
  481. void set_flag_v(BYTE in1, BYTE in2, BYTE out1)
  482. {
  483. BYTE reg1in;
  484. BYTE reg2in;
  485. BYTE regOut;
  486.  
  487. reg1in = in1;
  488. reg2in = in2;
  489. regOut = out1;
  490.  
  491. //code for overflow flag given in PAL session
  492.  
  493. if ((((reg1in & 0x80) == 0x80) && ((reg2in & 0x80) == 0x80) && ((regOut & 0x80) != 0x80)) //overflow
  494. || (((reg1in & 0x80) != 0x80) && ((reg2in & 0x80) != 0x80) && ((regOut & 0x80) == 0x80)))
  495. {
  496. Flags = Flags | FLAG_V;
  497. }
  498. else
  499. {
  500. Flags = Flags & (0xFF - FLAG_V);
  501. }
  502.  
  503. }
  504.  
  505.  
  506. void Group_1_Dual_Operand_Instructions(BYTE opcode)
  507. {
  508. BYTE regA;
  509. BYTE regB;
  510. BYTE lb;
  511. BYTE hb;
  512. BYTE byte_address;
  513. WORD wresult;
  514. WORD wdata;
  515. WORD hi_address, lo_address;
  516. WORD address;
  517. WORD temp_word;
  518. WORD offset;
  519.  
  520.  
  521.  
  522. switch (opcode)
  523. {
  524. case 0x86: // LDAA immediate
  525. Registers[REGISTER_A]=fetch();
  526. //flags
  527. Flags = Flags & (0xFF - FLAG_V);
  528. set_flag_n(Registers[REGISTER_A]);
  529. set_flag_z(Registers[REGISTER_A]);
  530. break;
  531.  
  532. case 0xA6: //LDAA indexed
  533. address=IndexRegister+(WORD)fetch();
  534. if((address >=0)&&(address<MEMORY_SIZE))
  535. {
  536. Registers[REGISTER_A]=Memory[address];
  537. }
  538. else
  539. {
  540. Registers[REGISTER_A]=0;
  541. }
  542. //flags
  543. Flags = Flags & (0xFF - FLAG_V);
  544. set_flag_n(Registers[REGISTER_A]);
  545. set_flag_z(Registers[REGISTER_A]);
  546. break;
  547.  
  548. case 0xB6: // LDAA extended
  549. hb=(WORD)fetch();
  550. lb=(WORD)fetch();
  551. address=(hb<<8)+lb;
  552. if((address >=0)&&(address<MEMORY_SIZE))
  553. {
  554. Registers[REGISTER_A]=Memory[address];
  555. }
  556. else
  557. {
  558. Registers[REGISTER_A]=0;
  559. }
  560. //flags
  561. Flags = Flags & (0xFF - FLAG_V);
  562. set_flag_n(Registers[REGISTER_A]);
  563. set_flag_z(Registers[REGISTER_A]);
  564. break;
  565.  
  566. case 0x96: // LDAA direct
  567. address = (WORD)fetch();
  568. if ((address >= 0)&&(address<MEMORY_SIZE))
  569. {
  570. Registers[REGISTER_A]=Memory[address];
  571. }
  572. else
  573. {
  574. Registers[REGISTER_A]=0;
  575. }
  576. //flags
  577. Flags = Flags & (0xFF - FLAG_V);
  578. set_flag_n(Registers[REGISTER_A]);
  579. set_flag_z(Registers[REGISTER_A]);
  580. break;
  581.  
  582.  
  583.  
  584. case 0x97: // STAA direct
  585. address = (WORD)fetch();
  586. if ((address >= 0)&&(address<MEMORY_SIZE))
  587. {
  588. Memory[address]=Registers[REGISTER_A];
  589. }
  590. else{}
  591. //flags
  592. Flags = Flags & (0xFF - FLAG_V);
  593. set_flag_n(Registers[REGISTER_A]);
  594. set_flag_z(Registers[REGISTER_A]);
  595. break;
  596.  
  597. case 0xA7: //STAA indexed
  598. address=IndexRegister+(WORD)fetch();
  599. if((address >=0)&&(address<MEMORY_SIZE))
  600. {
  601. Memory[address]=Registers[REGISTER_A];
  602. }
  603. else {}
  604. //flags
  605. Flags = Flags & (0xFF - FLAG_V);
  606. set_flag_n(Registers[REGISTER_A]);
  607. set_flag_z(Registers[REGISTER_A]);
  608. break;
  609.  
  610. case 0xB7: //StAA extended
  611. hb=(WORD)fetch();
  612. lb=(WORD)fetch();
  613. address=(hb<<8)+lb;
  614. if((address >=0)&&(address<MEMORY_SIZE))
  615. {
  616. Memory[address]=Registers[REGISTER_A];
  617. }
  618. else{}
  619. //flags
  620. Flags = Flags & (0xFF - FLAG_V);
  621. set_flag_n(Registers[REGISTER_A]);
  622. set_flag_z(Registers[REGISTER_A]);
  623. break;
  624.  
  625. case 0xC6: // LDAB immediate
  626. Registers[REGISTER_B]=fetch();
  627. //flags
  628. //flags
  629. Flags = Flags & (0xFF - FLAG_V);
  630. set_flag_n(Registers[REGISTER_B]);
  631. set_flag_z(Registers[REGISTER_B]);
  632. break;
  633.  
  634. case 0xD6: // LDAB direct
  635. address = (WORD)fetch();
  636. if ((address >= 0)&&(address<MEMORY_SIZE))
  637. {
  638. Registers[REGISTER_B]=Memory[address];
  639. }
  640. else
  641. {
  642. Registers[REGISTER_B]=0;
  643. }
  644. //flags
  645. Flags = Flags & (0xFF - FLAG_V);
  646. set_flag_n(Registers[REGISTER_B]);
  647. set_flag_z(Registers[REGISTER_B]);
  648. break;
  649.  
  650. case 0xE6: // LDAB indexed
  651. address=IndexRegister+(WORD)fetch();
  652. if((address >=0)&&(address<MEMORY_SIZE))
  653. {
  654. Registers[REGISTER_B]=Memory[address];
  655. }
  656. else
  657. {
  658. Registers[REGISTER_B]=0;
  659. }
  660. //flags
  661. Flags = Flags & (0xFF - FLAG_V);
  662. set_flag_n(Registers[REGISTER_B]);
  663. set_flag_z(Registers[REGISTER_B]);
  664. break;
  665.  
  666. case 0xF6: //LDAB extended
  667. hb=(WORD)fetch();
  668. lb=(WORD)fetch();
  669. address=(hb<<8)+lb;
  670. if((address >=0)&&(address<MEMORY_SIZE))
  671. {
  672. Registers[REGISTER_B]=Memory[address];
  673. }
  674. else
  675. {
  676. Registers[REGISTER_B]=0;
  677. }
  678. //flags
  679. Flags = Flags & (0xFF - FLAG_V);
  680. set_flag_n(Registers[REGISTER_B]);
  681. set_flag_z(Registers[REGISTER_B]);
  682. break;
  683.  
  684. case 0xD7: // STAB direct
  685. address = (WORD)fetch();
  686. if ((address >= 0)&&(address<MEMORY_SIZE))
  687. {
  688. Memory[address]=Registers[REGISTER_B];
  689. }
  690. else{}
  691. //flags
  692. Flags = Flags & (0xFF - FLAG_V);
  693. set_flag_n(Registers[REGISTER_B]);
  694. set_flag_z(Registers[REGISTER_B]);
  695. break;
  696.  
  697. case 0xE7: //STAB indexed
  698. address=IndexRegister+(WORD)fetch();
  699. if((address >=0)&&(address<MEMORY_SIZE))
  700. {
  701. Memory[address]=Registers[REGISTER_B];
  702. }
  703. else {}
  704. //flags
  705. Flags = Flags & (0xFF - FLAG_V);
  706. set_flag_n(Registers[REGISTER_B]);
  707. set_flag_z(Registers[REGISTER_B]);
  708. break;
  709.  
  710. case 0xF7: // STAB extended
  711. hb=(WORD)fetch();
  712. lb=(WORD)fetch();
  713. address=(hb<<8)+lb;
  714. if((address >=0)&&(address<MEMORY_SIZE))
  715. {
  716. Memory[address]=Registers[REGISTER_B];
  717. }
  718. else{}
  719. //flags
  720. Flags = Flags & (0xFF - FLAG_V);
  721. set_flag_n(Registers[REGISTER_B]);
  722. set_flag_z(Registers[REGISTER_B]);
  723. break;
  724.  
  725. case 0xCE: // LDX immediate
  726. IndexRegister=(((WORD)fetch())<<8)+fetch();
  727. temp_word = (WORD)IndexRegister;
  728. //flags
  729. if (IndexRegister < 0x00)
  730. {
  731. Flags = Flags | FLAG_N;
  732. }
  733. else
  734. {
  735. Flags = Flags & (0xFF - FLAG_N);
  736. }
  737. Flags = Flags & (0xFF - FLAG_V);
  738. set_flag_z((BYTE)temp_word);
  739. break;
  740.  
  741. case 0xDE: // LDX direct
  742. address=(WORD)fetch();
  743. temp_word = (WORD)IndexRegister;
  744. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  745. {
  746. IndexRegister=(((WORD)Memory[address])<<8)+(WORD)Memory[address+1];
  747. }
  748. else
  749. {
  750. IndexRegister=0;
  751. }
  752. //flags
  753. if (IndexRegister < 0x00)
  754. {
  755. Flags = Flags | FLAG_N;
  756. }
  757. else
  758. {
  759. Flags = Flags & (0xFF - FLAG_N);
  760. }
  761. Flags = Flags & (0xFF - FLAG_V);
  762. set_flag_z((BYTE)temp_word);
  763. break;
  764.  
  765. case 0xEE: //LDX indexed
  766. address=IndexRegister+(WORD)fetch();
  767. temp_word = (WORD)IndexRegister;
  768. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  769. {
  770. IndexRegister=(((WORD)Memory[address])<<8)+(WORD)Memory[address+1];
  771. }
  772. else
  773. {
  774. IndexRegister=0;
  775. }
  776. //flags
  777. if (IndexRegister < 0x00)
  778. {
  779. Flags = Flags | FLAG_N;
  780. }
  781. else
  782. {
  783. Flags = Flags & (0xFF - FLAG_N);
  784. }
  785. Flags = Flags & (0xFF - FLAG_V);
  786. set_flag_z((BYTE)temp_word);
  787. break;
  788.  
  789. case 0xFE: // LDX extended
  790. hb=(WORD)fetch();
  791. lb=(WORD)fetch();
  792. address=(hb<<8)+lb;
  793. temp_word = (WORD)IndexRegister;
  794. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  795. {
  796. IndexRegister=(((WORD)Memory[address])<<8)+(WORD)Memory[address+1];
  797. }
  798. else
  799. {
  800. IndexRegister=0;
  801. }
  802. //flags
  803. if (IndexRegister < 0x00)
  804. {
  805. Flags = Flags | FLAG_N;
  806. }
  807. else
  808. {
  809. Flags = Flags & (0xFF - FLAG_N);
  810. }
  811. Flags = Flags & (0xFF - FLAG_V);
  812. set_flag_z((BYTE)temp_word);
  813. break;
  814.  
  815. case 0xDF: // STX direct
  816. address=(WORD)fetch();
  817. temp_word = (WORD)IndexRegister;
  818. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  819. {
  820. Memory[address]=(BYTE)((IndexRegister>>8)&0xFF);
  821. Memory[address+1]=(BYTE)((IndexRegister>>8)&0xFF);
  822. }
  823. //flags
  824. if (IndexRegister < 0x00)
  825. {
  826. Flags = Flags | FLAG_N;
  827. }
  828. else
  829. {
  830. Flags = Flags & (0xFF - FLAG_N);
  831. }
  832. Flags = Flags & (0xFF - FLAG_V);
  833. set_flag_z((BYTE)temp_word);
  834. break;
  835.  
  836. case 0xEF: // STX Indexed
  837. address=IndexRegister+(WORD)fetch();
  838. temp_word = (WORD)IndexRegister;
  839. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  840. {
  841. Memory[address]=(BYTE)((IndexRegister>>8)&0xFF);
  842. Memory[address+1]=(BYTE)((IndexRegister>>8)&0xFF);
  843. }
  844. //flags
  845. if (IndexRegister < 0x00)
  846. {
  847. Flags = Flags | FLAG_N;
  848. }
  849. else
  850. {
  851. Flags = Flags & (0xFF - FLAG_N);
  852. }
  853. Flags = Flags & (0xFF - FLAG_V);
  854. set_flag_z((BYTE)temp_word);
  855. break;
  856.  
  857. case 0xFF: // STX extended
  858. hb=(WORD)fetch();
  859. lb=(WORD)fetch();
  860. address=(hb<<8)+lb;
  861. temp_word = (WORD)IndexRegister;
  862. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  863. {
  864. Memory[address]=(BYTE)((IndexRegister>>8)&0xFF);
  865. Memory[address+1]=(BYTE)((IndexRegister>>8)&0xFF);
  866. }
  867. //flags
  868. if (IndexRegister < 0x00)
  869. {
  870. Flags = Flags | FLAG_N;
  871. }
  872. else
  873. {
  874. Flags = Flags & (0xFF - FLAG_N);
  875. }
  876. Flags = Flags & (0xFF - FLAG_V);
  877. set_flag_z((BYTE)temp_word);
  878. break;
  879.  
  880. case 0x8E: //LDS immediate
  881. StackPointer=(((WORD)fetch())<<8)+fetch();
  882. temp_word = (WORD)StackPointer;
  883. //flags
  884. if (StackPointer < 0x00)
  885. {
  886. Flags = Flags | FLAG_N;
  887. }
  888. else
  889. {
  890. Flags = Flags & (0xFF - FLAG_N);
  891. }
  892. Flags = Flags & (0xFF - FLAG_V);
  893. set_flag_z((BYTE)temp_word);
  894. break;
  895.  
  896. case 0x9E: //LDS Direct
  897. address=(WORD)fetch();
  898. temp_word = (WORD)StackPointer;
  899. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  900. {
  901. StackPointer=(((WORD)Memory[address])<<8)+(WORD)Memory[address+1];
  902. }
  903. else
  904. {
  905. StackPointer=0;
  906. }
  907. //flags
  908. if (StackPointer < 0x00)
  909. {
  910. Flags = Flags | FLAG_N;
  911. }
  912. else
  913. {
  914. Flags = Flags & (0xFF - FLAG_N);
  915. }
  916. Flags = Flags & (0xFF - FLAG_V);
  917. set_flag_z((BYTE)temp_word);
  918. break;
  919.  
  920. case 0xAE: //LDS indexed
  921. address=IndexRegister+(WORD)fetch();
  922. temp_word = (WORD)StackPointer;
  923. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  924. {
  925. StackPointer=(((WORD)Memory[address])<<8)+(WORD)Memory[address+1];
  926. }
  927. else
  928. {
  929. StackPointer=0;
  930. }
  931. //flags
  932. if (StackPointer < 0x00)
  933. {
  934. Flags = Flags | FLAG_N;
  935. }
  936. else
  937. {
  938. Flags = Flags & (0xFF - FLAG_N);
  939. }
  940. Flags = Flags & (0xFF - FLAG_V);
  941. set_flag_z((BYTE)temp_word);
  942. break;
  943.  
  944. case 0xBE: //LDS extended
  945. hb=(WORD)fetch();
  946. lb=(WORD)fetch();
  947. address=(hb<<8)+lb;
  948. temp_word = (WORD)StackPointer;
  949. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  950. {
  951. StackPointer=(((WORD)Memory[address])<<8)+(WORD)Memory[address+1];
  952. }
  953. else
  954. {
  955. StackPointer=0;
  956. }
  957. //flags
  958. if (StackPointer < 0x00)
  959. {
  960. Flags = Flags | FLAG_N;
  961. }
  962. else
  963. {
  964. Flags = Flags & (0xFF - FLAG_N);
  965. }
  966. Flags = Flags & (0xFF - FLAG_V);
  967. set_flag_z((BYTE)temp_word);
  968. break;
  969.  
  970. case 0x9F: // STS direct
  971. address=(WORD)fetch();
  972. temp_word = (WORD)StackPointer;
  973. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  974. {
  975. Memory[address]=(BYTE)((StackPointer>>8)&0xFF);
  976. Memory[address+1]=(BYTE)((StackPointer>>8)&0xFF);
  977. }
  978. //flags
  979. if (StackPointer < 0x00)
  980. {
  981. Flags = Flags | FLAG_N;
  982. }
  983. else
  984. {
  985. Flags = Flags & (0xFF - FLAG_N);
  986. }
  987. Flags = Flags & (0xFF - FLAG_V);
  988. set_flag_z((BYTE)temp_word);
  989. break;
  990.  
  991. case 0xAf: //STS indexed
  992. address=IndexRegister+(WORD)fetch();
  993. temp_word = (WORD)StackPointer;
  994. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  995. {
  996. Memory[address]=(BYTE)((StackPointer>>8)&0xFF);
  997. Memory[address+1]=(BYTE)((StackPointer>>8)&0xFF);
  998. }
  999. //flags
  1000. if (StackPointer < 0x00)
  1001. {
  1002. Flags = Flags | FLAG_N;
  1003. }
  1004. else
  1005. {
  1006. Flags = Flags & (0xFF - FLAG_N);
  1007. }
  1008. Flags = Flags & (0xFF - FLAG_V);
  1009. set_flag_z((BYTE)temp_word);
  1010. break;
  1011.  
  1012. case 0xBF: //STS extended
  1013. hb=(WORD)fetch();
  1014. lb=(WORD)fetch();
  1015. address=(hb<<8)+lb;
  1016. temp_word = (WORD)StackPointer;
  1017. if((address >=0)&&(address<(MEMORY_SIZE-1)))
  1018. {
  1019. Memory[address]=(BYTE)((StackPointer>>8)&0xFF);
  1020. Memory[address+1]=(BYTE)((StackPointer>>8)&0xFF);
  1021. }
  1022. //flags
  1023. if (StackPointer < 0x00)
  1024. {
  1025. Flags = Flags | FLAG_N;
  1026. }
  1027. else
  1028. {
  1029. Flags = Flags & (0xFF - FLAG_N);
  1030. }
  1031. Flags = Flags & (0xFF - FLAG_V);
  1032. set_flag_z((BYTE)temp_word);
  1033. break;
  1034.  
  1035. case 0x8B: // ADDA immediate
  1036. regA=Registers[REGISTER_A];
  1037. lb=fetch();
  1038. temp_word=(WORD)Registers[REGISTER_A]+(WORD)lb;
  1039. set_carry_flag(temp_word);
  1040. set_flag_n((BYTE)temp_word);
  1041. set_flag_z((BYTE)temp_word);
  1042. set_flag_v(regA,lb,(BYTE)temp_word);
  1043. Registers[REGISTER_A]=(BYTE)temp_word;
  1044.  
  1045. break;
  1046.  
  1047. case 0x9B: //ADDA direct
  1048. regA=Registers[REGISTER_A];
  1049. address=(WORD)fetch();
  1050. if ((address >= 0) && (address < MEMORY_SIZE))
  1051. {
  1052. lb = Memory[address];
  1053. }
  1054. else
  1055. {
  1056. lb = 0;
  1057. }
  1058. temp_word=(WORD)Registers[REGISTER_A]+(WORD)lb;
  1059. set_carry_flag(temp_word);
  1060. set_flag_n((BYTE)temp_word);
  1061. set_flag_z((BYTE)temp_word);
  1062. set_flag_v(regA,lb,(BYTE)temp_word);
  1063. Registers[REGISTER_A]=(BYTE)temp_word;
  1064. break;
  1065.  
  1066. case 0xAB: //ADDA Index
  1067. regA = Registers[REGISTER_A];
  1068. address = IndexRegister + (WORD)fetch();
  1069. if ((address >= 0) && (address < MEMORY_SIZE))
  1070. {
  1071. lb = Memory[address];
  1072. }
  1073. else
  1074. {
  1075. lb = 0;
  1076. }
  1077. temp_word = (WORD) Registers[REGISTER_A] + (WORD)lb;
  1078. set_carry_flag(temp_word);
  1079. set_flag_n((BYTE)temp_word);
  1080. set_flag_z((BYTE)temp_word);
  1081. set_flag_v(regA, lb, (BYTE)temp_word);
  1082. Registers[REGISTER_A] = (BYTE)temp_word;
  1083. break;
  1084.  
  1085. case 0xBB: //ADDA Extended
  1086. hb=(WORD)fetch();
  1087. lb=(WORD)fetch();
  1088. address=(hb<<8)+lb;
  1089. regA=Registers[REGISTER_A];
  1090. address=(WORD)fetch();
  1091. if ((address >= 0) && (address < MEMORY_SIZE))
  1092. {
  1093. lb = Memory[address];
  1094. }
  1095. else
  1096. {
  1097. lb = 0;
  1098. }
  1099. temp_word = (WORD) Registers[REGISTER_A] + (WORD)lb;
  1100. set_carry_flag(temp_word);
  1101. set_flag_n((BYTE)temp_word);
  1102. set_flag_z((BYTE)temp_word);
  1103. set_flag_v(regA,lb,(BYTE)temp_word);
  1104. Registers[REGISTER_A]=(BYTE)temp_word;
  1105. break;
  1106.  
  1107. case 0xCB: //ADDB Immediate
  1108. regB=Registers[REGISTER_B];
  1109. lb=fetch();
  1110. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1111. set_carry_flag(temp_word);
  1112. set_flag_n((BYTE)temp_word);
  1113. set_flag_z((BYTE)temp_word);
  1114. set_flag_v(regB,lb,(BYTE)temp_word);
  1115. Registers[REGISTER_B]=(BYTE)temp_word;
  1116. break;
  1117.  
  1118. case 0xDB: //ADDB Direct
  1119. regB=Registers[REGISTER_B];
  1120. address=(WORD)fetch();
  1121. if ((address >= 0) && (address < MEMORY_SIZE))
  1122. {
  1123. lb = Memory[address];
  1124. }
  1125. else
  1126. {
  1127. lb = 0;
  1128. }
  1129. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1130. set_carry_flag(temp_word);
  1131. set_flag_n((BYTE)temp_word);
  1132. set_flag_z((BYTE)temp_word);
  1133. set_flag_v(regB,lb,(BYTE)temp_word);
  1134. Registers[REGISTER_B]=(BYTE)temp_word;
  1135. break;
  1136.  
  1137. case 0xEB: //ADDB Index
  1138. regB = Registers[REGISTER_B];
  1139. address = IndexRegister + (WORD)fetch();
  1140. if ((address >= 0) && (address < MEMORY_SIZE))
  1141. {
  1142. lb = Memory[address];
  1143. }
  1144. else
  1145. {
  1146. lb = 0;
  1147. }
  1148. temp_word = (WORD) Registers[REGISTER_B] + (WORD)lb;
  1149. set_carry_flag(temp_word);
  1150. set_flag_n((BYTE)temp_word);
  1151. set_flag_z((BYTE)temp_word);
  1152. set_flag_v(regB, lb, (BYTE)temp_word);
  1153. Registers[REGISTER_B] = (BYTE)temp_word;
  1154. break;
  1155.  
  1156. case 0xFB: //ADDB Extended
  1157. hb=(WORD)fetch();
  1158. lb=(WORD)fetch();
  1159. address=(hb<<8)+lb;
  1160. regB=Registers[REGISTER_B];
  1161. address=(WORD)fetch();
  1162. if ((address >= 0) && (address < MEMORY_SIZE))
  1163. {
  1164. lb = Memory[address];
  1165. }
  1166. else
  1167. {
  1168. lb = 0;
  1169. }
  1170. temp_word = (WORD) Registers[REGISTER_B] + (WORD)lb;
  1171. set_carry_flag(temp_word);
  1172. set_flag_n((BYTE)temp_word);
  1173. set_flag_z((BYTE)temp_word);
  1174. set_flag_v(regB,lb,(BYTE)temp_word);
  1175. Registers[REGISTER_B]=(BYTE)temp_word;
  1176. break;
  1177.  
  1178.  
  1179.  
  1180. case 0x89: //ADCA immediate
  1181. regA=Registers[REGISTER_A];
  1182. lb=fetch();
  1183. temp_word=(WORD)Registers[REGISTER_A]+(WORD)lb;
  1184. if ((Flags & FLAG_C) !=0)
  1185. {
  1186. temp_word++;
  1187. }
  1188. set_carry_flag(temp_word);
  1189. set_flag_n((BYTE)temp_word);
  1190. set_flag_z((BYTE)temp_word);
  1191. set_flag_v(regA,lb,(BYTE)temp_word);
  1192. Registers[REGISTER_A]=(BYTE)temp_word;
  1193.  
  1194. break;
  1195.  
  1196. case 0x99: //ADCA Direct
  1197. regA=Registers[REGISTER_A];
  1198. address=(WORD)fetch();
  1199. lb=fetch();
  1200. temp_word=(WORD)Registers[REGISTER_A]+(WORD)lb;
  1201. if((Flags & FLAG_C) !=0)
  1202. {
  1203. temp_word++;
  1204. }
  1205. set_carry_flag(temp_word);
  1206. set_flag_n((BYTE)temp_word);
  1207. set_flag_z((BYTE)temp_word);
  1208. set_flag_v(regA,lb,(BYTE)temp_word);
  1209. Registers[REGISTER_A]=(BYTE)temp_word;
  1210. break;
  1211.  
  1212. case 0xA9: //ADCA Index
  1213. address=IndexRegister+(WORD)fetch();
  1214. regA=Registers[REGISTER_A];
  1215. address=(WORD)fetch();
  1216. lb=fetch();
  1217. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1218. if((Flags & FLAG_C) !=0)
  1219. {
  1220. temp_word++;
  1221. }
  1222. set_carry_flag(temp_word);
  1223. set_flag_n((BYTE)temp_word);
  1224. set_flag_z((BYTE)temp_word);
  1225. set_flag_v(regA,lb,(BYTE)temp_word);
  1226. Registers[REGISTER_A]=(BYTE)temp_word;
  1227. break;
  1228.  
  1229. case 0xB9: //ADCA Extended
  1230. hb=(WORD)fetch();
  1231. lb=(WORD)fetch();
  1232. address=(hb<<8)+lb;
  1233. regA=Registers[REGISTER_A];
  1234. address=(hb << 8) + lb;
  1235. if ((address >=0) && (address < MEMORY_SIZE))
  1236. {
  1237. lb = Memory[address];
  1238. }
  1239. else
  1240. {
  1241. lb = 0;
  1242. }
  1243. temp_word=(WORD)Registers[REGISTER_A]+(WORD)lb;
  1244. if((Flags & FLAG_C) !=0)
  1245. {
  1246. temp_word++;
  1247. }
  1248. set_carry_flag(temp_word);
  1249. set_flag_n((BYTE)temp_word);
  1250. set_flag_z((BYTE)temp_word);
  1251. set_flag_v(regA,lb,(BYTE)temp_word);
  1252. Registers[REGISTER_A]=(BYTE)temp_word;
  1253. break;
  1254.  
  1255. case 0xC9: //ADCB Immediate
  1256. regB=Registers[REGISTER_B];
  1257. lb=fetch();
  1258. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1259. if ((Flags & FLAG_C) !=0)
  1260. {
  1261. temp_word++;
  1262. }
  1263. set_carry_flag(temp_word);
  1264. set_flag_n((BYTE)temp_word);
  1265. set_flag_z((BYTE)temp_word);
  1266. set_flag_v(regB,lb,(BYTE)temp_word);
  1267. Registers[REGISTER_B]=(BYTE)temp_word;
  1268. break;
  1269.  
  1270. case 0xD9: //ADCB Direct
  1271. regB=Registers[REGISTER_B];
  1272. address=(WORD)fetch();
  1273. lb=fetch();
  1274. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1275. if((Flags & FLAG_C) !=0)
  1276. {
  1277. temp_word++;
  1278. }
  1279. set_carry_flag(temp_word);
  1280. set_flag_n((BYTE)temp_word);
  1281. set_flag_z((BYTE)temp_word);
  1282. set_flag_v(regB,lb,(BYTE)temp_word);
  1283. Registers[REGISTER_B]=(BYTE)temp_word;
  1284. break;
  1285.  
  1286. case 0xE9: //ADCB Index
  1287. address=IndexRegister+(WORD)fetch();
  1288. regB=Registers[REGISTER_B];
  1289. address=(WORD)fetch();
  1290. lb=fetch();
  1291. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1292. if((Flags & FLAG_C) !=0)
  1293. {
  1294. temp_word++;
  1295. }
  1296. set_carry_flag(temp_word);
  1297. set_flag_n((BYTE)temp_word);
  1298. set_flag_z((BYTE)temp_word);
  1299. set_flag_v(regB,lb,(BYTE)temp_word);
  1300. Registers[REGISTER_B]=(BYTE)temp_word;
  1301. break;
  1302.  
  1303. case 0xF9: //ADCB Extended
  1304. hb=(WORD)fetch();
  1305. lb=(WORD)fetch();
  1306. address=(hb<<8)+lb;
  1307. regB=Registers[REGISTER_B];
  1308. address=(hb << 8) + lb;
  1309. if ((address >=0) && (address < MEMORY_SIZE))
  1310. {
  1311. lb = Memory[address];
  1312. }
  1313. else
  1314. {
  1315. lb = 0;
  1316. }
  1317. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1318. if((Flags & FLAG_C) !=0)
  1319. {
  1320. temp_word++;
  1321. }
  1322. set_carry_flag(temp_word);
  1323. set_flag_n((BYTE)temp_word);
  1324. set_flag_z((BYTE)temp_word);
  1325. set_flag_v(regB,lb,(BYTE)temp_word);
  1326. Registers[REGISTER_B]=(BYTE)temp_word;
  1327. break;
  1328.  
  1329.  
  1330.  
  1331. case 0x81: //CMPA immediate
  1332. regA=Registers[REGISTER_A];
  1333. lb=fetch();
  1334. temp_word=(WORD)Registers[REGISTER_A]-(WORD)lb;
  1335. set_carry_flag(temp_word);
  1336. set_flag_n((BYTE)temp_word);
  1337. set_flag_z((BYTE)temp_word);
  1338. set_flag_v(regA,lb,(BYTE)temp_word);
  1339.  
  1340. break;
  1341.  
  1342. case 0x91: //CMPA Direct
  1343. regA=Registers[REGISTER_A];
  1344. address=(WORD)fetch();
  1345. lb=fetch();
  1346. temp_word=(WORD)Registers[REGISTER_A]+(WORD)lb;
  1347. set_carry_flag(temp_word);
  1348. set_flag_n((BYTE)temp_word);
  1349. set_flag_z((BYTE)temp_word);
  1350. set_flag_v(regA,lb,(BYTE)temp_word);
  1351. Registers[REGISTER_A]=(BYTE)temp_word;
  1352. break;
  1353.  
  1354. case 0xA1: //CMPA Index
  1355. address=IndexRegister+(WORD)fetch();
  1356. regA=Registers[REGISTER_A];
  1357. address=(WORD)fetch();
  1358. lb=fetch();
  1359. temp_word=(WORD)Registers[REGISTER_A]+(WORD)lb;
  1360. set_carry_flag(temp_word);
  1361. set_flag_n((BYTE)temp_word);
  1362. set_flag_z((BYTE)temp_word);
  1363. set_flag_v(regA,lb,(BYTE)temp_word);
  1364. Registers[REGISTER_A]=(BYTE)temp_word;
  1365. break;
  1366.  
  1367. case 0xB1: //CMPA Extended
  1368. hb=(WORD)fetch();
  1369. lb=(WORD)fetch();
  1370. address=(hb<<8)+lb;
  1371. regA=Registers[REGISTER_A];
  1372. if ((address >= 0) && (address < MEMORY_SIZE))
  1373. {
  1374. lb = Memory [(WORD)address];
  1375. }
  1376. else
  1377. {
  1378. lb=0;
  1379. }
  1380. temp_word=(WORD)Registers[REGISTER_A]+(WORD)lb;
  1381. set_carry_flag(temp_word);
  1382. set_flag_n((BYTE)temp_word);
  1383. set_flag_z((BYTE)temp_word);
  1384. set_flag_v(regA,lb,(BYTE)temp_word);
  1385. Registers[REGISTER_A]=(BYTE)temp_word;
  1386. break;
  1387.  
  1388. case 0xC1: //CMPB Immediate
  1389. regB=Registers[REGISTER_B];
  1390. lb=fetch();
  1391. temp_word=(WORD)Registers[REGISTER_B]-(WORD)lb;
  1392. set_carry_flag(temp_word);
  1393. set_flag_n((BYTE)temp_word);
  1394. set_flag_z((BYTE)temp_word);
  1395. set_flag_v(regB,lb,(BYTE)temp_word);
  1396.  
  1397. break;
  1398.  
  1399. case 0xD1: //CMPB Direct
  1400. regB=Registers[REGISTER_B];
  1401. address=(WORD)fetch();
  1402. lb=fetch();
  1403. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1404. set_carry_flag(temp_word);
  1405. set_flag_n((BYTE)temp_word);
  1406. set_flag_z((BYTE)temp_word);
  1407. set_flag_v(regB,lb,(BYTE)temp_word);
  1408. Registers[REGISTER_B]=(BYTE)temp_word;
  1409. break;
  1410.  
  1411. case 0xE1: //CMPB Index
  1412. address=IndexRegister+(WORD)fetch();
  1413. regB=Registers[REGISTER_B];
  1414. address=(WORD)fetch();
  1415. lb=fetch();
  1416. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1417. set_carry_flag(temp_word);
  1418. set_flag_n((BYTE)temp_word);
  1419. set_flag_z((BYTE)temp_word);
  1420. set_flag_v(regB,lb,(BYTE)temp_word);
  1421. Registers[REGISTER_B]=(BYTE)temp_word;
  1422. break;
  1423.  
  1424. case 0xF1: //CMPB Extended
  1425. hb=(WORD)fetch();
  1426. lb=(WORD)fetch();
  1427. address=(hb<<8)+lb;
  1428. regB=Registers[REGISTER_B];
  1429. if ((address >= 0) && (address < MEMORY_SIZE))
  1430. {
  1431. lb = Memory [(WORD)address];
  1432. }
  1433. else
  1434. {
  1435. lb=0;
  1436. }
  1437. temp_word=(WORD)Registers[REGISTER_B]+(WORD)lb;
  1438. set_carry_flag(temp_word);
  1439. set_flag_n((BYTE)temp_word);
  1440. set_flag_z((BYTE)temp_word);
  1441. set_flag_v(regB,lb,(BYTE)temp_word);
  1442. Registers[REGISTER_B]=(BYTE)temp_word;
  1443. break;
  1444.  
  1445. case 0xAD: //JSR indexed
  1446. address=IndexRegister+(WORD)fetch();
  1447. hb = Memory[address];
  1448. lb = Memory[address+1];
  1449. address = ((WORD)hb << 8) + (WORD)lb;
  1450. if((StackPointer >= 2) && (StackPointer < MEMORY_SIZE))
  1451. {
  1452. Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
  1453. StackPointer--;
  1454. Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
  1455. StackPointer--;
  1456. ProgramCounter = address;
  1457. }
  1458.  
  1459. break;
  1460.  
  1461. case 0xBD: //JSR extended
  1462. hb = fetch();
  1463. lb = fetch();
  1464. address = ((WORD)hb << 8) + (WORD)lb;
  1465. if((StackPointer >= 2) && (StackPointer < MEMORY_SIZE))
  1466. {
  1467. Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
  1468. StackPointer--;
  1469. Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
  1470. StackPointer--;
  1471. ProgramCounter = address;
  1472. }
  1473.  
  1474. break;
  1475.  
  1476. case 0x8D: //BSR
  1477. lb = fetch();
  1478. offset = (WORD) lb;
  1479. if((offset & 0x80) !=0) // need to sign extend
  1480. {
  1481. offset = offset + 0xFF00;
  1482. }
  1483. address = ProgramCounter + offset;
  1484. if((StackPointer >= 2) && (StackPointer < MEMORY_SIZE))
  1485. {
  1486. Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
  1487. StackPointer--;
  1488. Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
  1489. StackPointer--;
  1490. }
  1491. ProgramCounter = address;
  1492. break;
  1493.  
  1494. case 0x84: //ANDA Immediate
  1495. lb=fetch();
  1496. temp_word=(WORD)Registers[REGISTER_A]&(WORD)lb;
  1497. Flags = Flags & (0xFF - FLAG_V);
  1498. set_flag_n((BYTE)temp_word);
  1499. set_flag_z((BYTE)temp_word);
  1500. Registers[REGISTER_A]=(BYTE)temp_word;
  1501. break;
  1502.  
  1503. case 0x94: //ANDA Direct
  1504. address=(WORD)fetch();
  1505. if ((address >= 0) && (address < MEMORY_SIZE))
  1506. {
  1507. lb = Memory[address];
  1508. }
  1509. else
  1510. {
  1511. lb = 0;
  1512. }
  1513. temp_word=(WORD)Registers[REGISTER_A]&(WORD)lb;
  1514. set_flag_n((BYTE)temp_word);
  1515. set_flag_z((BYTE)temp_word);
  1516. Flags = Flags & (0xFF - FLAG_V);
  1517. Registers[REGISTER_A]=(BYTE)temp_word;
  1518. break;
  1519.  
  1520. case 0xA4: //ANDA Index
  1521. address = IndexRegister + (WORD)fetch();
  1522. if ((address >= 0) && (address < MEMORY_SIZE))
  1523. {
  1524. lb = Memory[address];
  1525. }
  1526. else
  1527. {
  1528. lb = 0;
  1529. }
  1530. temp_word = (WORD) Registers[REGISTER_A] & (WORD)lb;
  1531. set_flag_n((BYTE)temp_word);
  1532. set_flag_z((BYTE)temp_word);
  1533. Flags = Flags & (0xFF - FLAG_V);
  1534. Registers[REGISTER_A] = (BYTE)temp_word;
  1535. break;
  1536.  
  1537. case 0xB4: //ANDA Extended
  1538. hb=(WORD)fetch();
  1539. lb=(WORD)fetch();
  1540. address=(hb<<8)+lb;
  1541. address=(WORD)fetch();
  1542. if ((address >= 0) && (address < MEMORY_SIZE))
  1543. {
  1544. lb = Memory[address];
  1545. }
  1546. else
  1547. {
  1548. lb = 0;
  1549. }
  1550. temp_word = (WORD) Registers[REGISTER_A] & (WORD)lb;
  1551. set_flag_n((BYTE)temp_word);
  1552. set_flag_z((BYTE)temp_word);
  1553. Flags = Flags & (0xFF - FLAG_V);
  1554. Registers[REGISTER_A]=(BYTE)temp_word;
  1555. break;
  1556.  
  1557. case 0xC4: //ANDB Immediate
  1558. lb=fetch();
  1559. temp_word=(WORD)Registers[REGISTER_B]&(WORD)lb;
  1560. Flags = Flags & (0xFF - FLAG_V);
  1561. set_flag_n((BYTE)temp_word);
  1562. set_flag_z((BYTE)temp_word);
  1563. Registers[REGISTER_B]=(BYTE)temp_word;
  1564. break;
  1565.  
  1566. case 0xD4: //ANDB Direct
  1567. address=(WORD)fetch();
  1568. if ((address >= 0) && (address < MEMORY_SIZE))
  1569. {
  1570. lb = Memory[address];
  1571. }
  1572. else
  1573. {
  1574. lb = 0;
  1575. }
  1576. temp_word=(WORD)Registers[REGISTER_B]&(WORD)lb;
  1577. set_flag_n((BYTE)temp_word);
  1578. set_flag_z((BYTE)temp_word);
  1579. Flags = Flags & (0xFF - FLAG_V);
  1580. Registers[REGISTER_B]=(BYTE)temp_word;
  1581. break;
  1582.  
  1583. case 0xE4: //ANDB Indexed
  1584. address = IndexRegister + (WORD)fetch();
  1585. if ((address >= 0) && (address < MEMORY_SIZE))
  1586. {
  1587. lb = Memory[address];
  1588. }
  1589. else
  1590. {
  1591. lb = 0;
  1592. }
  1593. temp_word = (WORD) Registers[REGISTER_B] & (WORD)lb;
  1594. set_flag_n((BYTE)temp_word);
  1595. set_flag_z((BYTE)temp_word);
  1596. Flags = Flags & (0xFF - FLAG_V);
  1597. Registers[REGISTER_B] = (BYTE)temp_word;
  1598. break;
  1599.  
  1600. case 0xF4: //ANDB Extended
  1601. hb=(WORD)fetch();
  1602. lb=(WORD)fetch();
  1603. address=(hb<<8)+lb;
  1604. address=(WORD)fetch();
  1605. if ((address >= 0) && (address < MEMORY_SIZE))
  1606. {
  1607. lb = Memory[address];
  1608. }
  1609. else
  1610. {
  1611. lb = 0;
  1612. }
  1613. temp_word = (WORD) Registers[REGISTER_B] & (WORD)lb;
  1614. set_flag_n((BYTE)temp_word);
  1615. set_flag_z((BYTE)temp_word);
  1616. Flags = Flags & (0xFF - FLAG_V);
  1617. Registers[REGISTER_B]=(BYTE)temp_word;
  1618. break;
  1619.  
  1620. case 0x85: //BITA Immediate
  1621. regA = Registers[REGISTER_A];
  1622. lb = fetch();
  1623. temp_word = (WORD)Registers[REGISTER_A] & (WORD)lb;
  1624. Flags = Flags & (0xFF - FLAG_V);
  1625. set_flag_n((BYTE)temp_word);
  1626. set_flag_z((BYTE)temp_word);
  1627. Flags = Flags & (0xFF - FLAG_V);
  1628. break;
  1629.  
  1630. case 0x95: //BITA Direct
  1631. address= (WORD)fetch();
  1632. if ((address >= 0) && (address < MEMORY_SIZE))
  1633. {
  1634. lb = Memory[address];
  1635. }
  1636. else
  1637. {
  1638. lb = 0;
  1639. }
  1640. temp_word = (WORD)Registers[REGISTER_A] & (WORD)lb;
  1641. set_flag_n((BYTE)temp_word);
  1642. set_flag_z((BYTE)temp_word);
  1643. Flags = Flags & (0xFF - FLAG_V);
  1644. break;
  1645.  
  1646. case 0xA5: //BITA Index
  1647. address = IndexRegister & (WORD)fetch();
  1648. if ((address >= 0) && (address < MEMORY_SIZE))
  1649. {
  1650. lb = Memory[address];
  1651. }
  1652. else
  1653. {
  1654. lb = 0;
  1655. }
  1656. temp_word = (WORD) Registers[REGISTER_A] & (WORD)lb;
  1657. set_flag_n((BYTE)temp_word);
  1658. set_flag_z((BYTE)temp_word);
  1659. Flags = Flags & (0xFF - FLAG_V);
  1660. break;
  1661.  
  1662. case 0xB5: //BITA extended
  1663. hi_address = (WORD)fetch();
  1664. lo_address = (WORD)fetch();
  1665. address = (hi_address << 8) + lo_address;
  1666. if ((address >= 0) && (address < MEMORY_SIZE))
  1667. {
  1668. lb = Memory[address];
  1669. }
  1670. else
  1671. {
  1672. lb = 0;
  1673. }
  1674. temp_word = (WORD)Registers[REGISTER_A] & (WORD)lb;
  1675. set_flag_n((BYTE)temp_word);
  1676. set_flag_z((BYTE)temp_word);
  1677. Flags = Flags & (0xFF - FLAG_V);
  1678. break;
  1679.  
  1680. case 0xC5: //BITB Immediate
  1681. lb = fetch();
  1682. temp_word = (WORD)Registers[REGISTER_B] & (WORD)lb;
  1683. Flags = Flags & (0xFF - FLAG_V);
  1684. set_flag_n((BYTE)temp_word);
  1685. set_flag_z((BYTE)temp_word);
  1686. Flags = Flags & (0xFF - FLAG_V);
  1687. break;
  1688.  
  1689. case 0xD5: //BITB Direct
  1690. address= (WORD)fetch();
  1691. if ((address >= 0) && (address < MEMORY_SIZE))
  1692. {
  1693. lb = Memory[address];
  1694. }
  1695. else
  1696. {
  1697. lb = 0;
  1698. }
  1699. temp_word = (WORD)Registers[REGISTER_B] & (WORD)lb;
  1700. set_flag_n((BYTE)temp_word);
  1701. set_flag_z((BYTE)temp_word);
  1702. Flags = Flags & (0xFF - FLAG_V);
  1703. break;
  1704.  
  1705. case 0xE5: //BITB Index
  1706. address = IndexRegister & (WORD)fetch();
  1707. if ((address >= 0) && (address < MEMORY_SIZE))
  1708. {
  1709. lb = Memory[address];
  1710. }
  1711. else
  1712. {
  1713. lb = 0;
  1714. }
  1715. temp_word = (WORD) Registers[REGISTER_B] & (WORD)lb;
  1716. set_flag_n((BYTE)temp_word);
  1717. set_flag_z((BYTE)temp_word);
  1718. Flags = Flags & (0xFF - FLAG_V);
  1719. break;
  1720.  
  1721. case 0xF5: //BITB Extended
  1722. hi_address = (WORD)fetch();
  1723. lo_address = (WORD)fetch();
  1724. address = (hi_address << 8) + lo_address;
  1725. if ((address >= 0) && (address < MEMORY_SIZE))
  1726. {
  1727. lb = Memory[address];
  1728. }
  1729. else
  1730. {
  1731. lb = 0;
  1732. }
  1733. temp_word = (WORD)Registers[REGISTER_B] & (WORD)lb;
  1734. set_flag_n((BYTE)temp_word);
  1735. set_flag_z((BYTE)temp_word);
  1736. Flags = Flags & (0xFF - FLAG_V);
  1737. break;
  1738.  
  1739. case 0x80: //SUBA Immediate
  1740. regA = Registers[REGISTER_A];
  1741. lb = fetch();
  1742. temp_word = (WORD)Registers[REGISTER_A] - (WORD)lb;
  1743. set_carry_flag(temp_word);
  1744. set_flag_n((BYTE)temp_word);
  1745. set_flag_z((BYTE)temp_word);
  1746. set_flag_v(regA, lb, (BYTE)temp_word);
  1747. Registers[REGISTER_A] = (BYTE)temp_word;
  1748. break;
  1749.  
  1750.  
  1751. case 0x90: //SUBA Direct
  1752. regA=Registers[REGISTER_A];
  1753. address=(WORD)fetch();
  1754. if ((address >= 0) && (address < MEMORY_SIZE))
  1755. {
  1756. lb = Memory[address];
  1757. }
  1758. else
  1759. {
  1760. lb = 0;
  1761. }
  1762. temp_word=(WORD)Registers[REGISTER_A]-(WORD)lb;
  1763. set_carry_flag(temp_word);
  1764. set_flag_n((BYTE)temp_word);
  1765. set_flag_z((BYTE)temp_word);
  1766. set_flag_v(regA,lb,(BYTE)temp_word);
  1767. Registers[REGISTER_A]=(BYTE)temp_word;
  1768. break;
  1769.  
  1770. case 0xA0: //SUBA Index
  1771. regA = Registers[REGISTER_A];
  1772. address = IndexRegister - (WORD)fetch();
  1773. if ((address >= 0) && (address < MEMORY_SIZE))
  1774. {
  1775. lb = Memory[address];
  1776. }
  1777. else
  1778. {
  1779. lb = 0;
  1780. }
  1781. temp_word = (WORD) Registers[REGISTER_A] - (WORD)lb;
  1782. set_carry_flag(temp_word);
  1783. set_flag_n((BYTE)temp_word);
  1784. set_flag_z((BYTE)temp_word);
  1785. set_flag_v(regA, lb, (BYTE)temp_word);
  1786. Registers[REGISTER_A] = (BYTE)temp_word;
  1787. break;
  1788.  
  1789. case 0xB0: //SUBA Extended
  1790. hb=(WORD)fetch();
  1791. lb=(WORD)fetch();
  1792. address=(hb<<8)-lb;
  1793. regA=Registers[REGISTER_A];
  1794. address=(WORD)fetch();
  1795. if ((address >= 0) && (address < MEMORY_SIZE))
  1796. {
  1797. lb = Memory[address];
  1798. }
  1799. else
  1800. {
  1801. lb = 0;
  1802. }
  1803. temp_word = (WORD) Registers[REGISTER_A] - (WORD)lb;
  1804. set_carry_flag(temp_word);
  1805. set_flag_n((BYTE)temp_word);
  1806. set_flag_z((BYTE)temp_word);
  1807. set_flag_v(regA,lb,(BYTE)temp_word);
  1808. Registers[REGISTER_A]=(BYTE)temp_word;
  1809. break;
  1810.  
  1811. case 0xC0: //SUBB Immediate
  1812. regB = Registers[REGISTER_B];
  1813. lb = fetch();
  1814. temp_word = (WORD)Registers[REGISTER_B] - (WORD)lb;
  1815. set_carry_flag(temp_word);
  1816. set_flag_n((BYTE)temp_word);
  1817. set_flag_z((BYTE)temp_word);
  1818. set_flag_v(regB, lb, (BYTE)temp_word);
  1819. Registers[REGISTER_B] = (BYTE)temp_word;
  1820. break;
  1821.  
  1822. case 0xD0: //SUBB Direct
  1823. regB=Registers[REGISTER_B];
  1824. address=(WORD)fetch();
  1825. if ((address >= 0) && (address < MEMORY_SIZE))
  1826. {
  1827. lb = Memory[address];
  1828. }
  1829. else
  1830. {
  1831. lb = 0;
  1832. }
  1833. temp_word=(WORD)Registers[REGISTER_B]-(WORD)lb;
  1834. set_carry_flag(temp_word);
  1835. set_flag_n((BYTE)temp_word);
  1836. set_flag_z((BYTE)temp_word);
  1837. set_flag_v(regB,lb,(BYTE)temp_word);
  1838. Registers[REGISTER_B]=(BYTE)temp_word;
  1839. break;
  1840.  
  1841. case 0xE0: //SUBB Index
  1842. regB = Registers[REGISTER_B];
  1843. address = IndexRegister - (WORD)fetch();
  1844. if ((address >= 0) && (address < MEMORY_SIZE))
  1845. {
  1846. lb = Memory[address];
  1847. }
  1848. else
  1849. {
  1850. lb = 0;
  1851. }
  1852. temp_word = (WORD) Registers[REGISTER_B] - (WORD)lb;
  1853. set_carry_flag(temp_word);
  1854. set_flag_n((BYTE)temp_word);
  1855. set_flag_z((BYTE)temp_word);
  1856. set_flag_v(regB, lb, (BYTE)temp_word);
  1857. Registers[REGISTER_B] = (BYTE)temp_word;
  1858. break;
  1859.  
  1860. case 0xF0: //SUBB Extended
  1861. hb=(WORD)fetch();
  1862. lb=(WORD)fetch();
  1863. address=(hb<<8)-lb;
  1864. regA=Registers[REGISTER_B];
  1865. address=(WORD)fetch();
  1866. if ((address >= 0) && (address < MEMORY_SIZE))
  1867. {
  1868. lb = Memory[address];
  1869. }
  1870. else
  1871. {
  1872. lb = 0;
  1873. }
  1874. temp_word = (WORD) Registers[REGISTER_B] - (WORD)lb;
  1875. set_carry_flag(temp_word);
  1876. set_flag_n((BYTE)temp_word);
  1877. set_flag_z((BYTE)temp_word);
  1878. set_flag_v(regB,lb,(BYTE)temp_word);
  1879. Registers[REGISTER_B]=(BYTE)temp_word;
  1880. break;
  1881.  
  1882. case 0x82: //SBCA Immediate
  1883. regA=Registers[REGISTER_A];
  1884. lb=fetch();
  1885. temp_word=(WORD)Registers[REGISTER_A]-(WORD)lb;
  1886. if ((Flags & FLAG_C) !=0)
  1887. {
  1888. temp_word--;
  1889. }
  1890. set_carry_flag(temp_word);
  1891. set_flag_n((BYTE)temp_word);
  1892. set_flag_z((BYTE)temp_word);
  1893. set_flag_v(regA,lb,(BYTE)temp_word);
  1894. Registers[REGISTER_A]=(BYTE)temp_word;
  1895. break;
  1896.  
  1897. case 0x92: //SBCA Direct
  1898. regA=Registers[REGISTER_A];
  1899. address=(WORD)fetch();
  1900. temp_word=(WORD)Registers[REGISTER_A]-(WORD)lb;
  1901. if ((address >=0) && (address < MEMORY_SIZE))
  1902. {
  1903. lb = Memory[address];
  1904. }
  1905. else
  1906. {
  1907. lb = 0;
  1908. }
  1909. if((Flags & FLAG_C) !=0)
  1910. {
  1911. temp_word--;
  1912. }
  1913. set_carry_flag(temp_word);
  1914. set_flag_n((BYTE)temp_word);
  1915. set_flag_z((BYTE)temp_word);
  1916. set_flag_v(regA,lb,(BYTE)temp_word);
  1917. Registers[REGISTER_A]=(BYTE)temp_word;
  1918. break;
  1919.  
  1920.  
  1921. case 0xA2: //SBCA Index
  1922. regA = Registers[REGISTER_A];
  1923. address = IndexRegister + (WORD)fetch();
  1924. temp_word=(WORD)Registers[REGISTER_A]-(WORD)lb;
  1925. if ((address >=0) && (address < MEMORY_SIZE))
  1926. {
  1927. lb = Memory[address];
  1928. }
  1929. else
  1930. {
  1931. lb = 0;
  1932. }
  1933. if((Flags & FLAG_C) !=0)
  1934. {
  1935. temp_word--;
  1936. }
  1937. set_carry_flag(temp_word);
  1938. set_flag_n((BYTE)temp_word);
  1939. set_flag_z((BYTE)temp_word);
  1940. set_flag_v(regA,lb,(BYTE)temp_word);
  1941. Registers[REGISTER_A]=(BYTE)temp_word;
  1942. break;
  1943.  
  1944. case 0xB2: //SBCA Extended
  1945. hb=(WORD)fetch();
  1946. lb=(WORD)fetch();
  1947. address=(hb<<8)+lb;
  1948. regA=Registers[REGISTER_A];
  1949. temp_word=(WORD)Registers[REGISTER_A]-(WORD)lb;
  1950. if ((address >=0) && (address < MEMORY_SIZE))
  1951. {
  1952. lb = Memory[address];
  1953. }
  1954. else
  1955. {
  1956. lb = 0;
  1957. }
  1958. if((Flags & FLAG_C) !=0)
  1959. {
  1960. temp_word--;
  1961. }
  1962. set_carry_flag(temp_word);
  1963. set_flag_n((BYTE)temp_word);
  1964. set_flag_z((BYTE)temp_word);
  1965. set_flag_v(regA,lb,(BYTE)temp_word);
  1966. Registers[REGISTER_A]=(BYTE)temp_word;
  1967. break;
  1968.  
  1969. case 0xC2: //SBCB Immediate
  1970. regB=Registers[REGISTER_B];
  1971. lb=fetch();
  1972. temp_word=(WORD)Registers[REGISTER_B]-(WORD)lb;
  1973. if ((Flags & FLAG_C) !=0)
  1974. {
  1975. temp_word--;
  1976. }
  1977. //flags
  1978. set_carry_flag(temp_word);
  1979. set_flag_n((BYTE)temp_word);
  1980. set_flag_z((BYTE)temp_word);
  1981. set_flag_v(regB,lb,(BYTE)temp_word);
  1982. Registers[REGISTER_B]=(BYTE)temp_word;
  1983. break;
  1984.  
  1985. case 0xD2: //SBCB Direct
  1986. regB=Registers[REGISTER_B];
  1987. address=(WORD)fetch();
  1988. lb=fetch();
  1989. temp_word=(WORD)Registers[REGISTER_B]-(WORD)lb;
  1990. if ((address >=0) && (address < MEMORY_SIZE))
  1991. {
  1992. lb = Memory[address];
  1993. }
  1994. else
  1995. {
  1996. lb = 0;
  1997. }
  1998. if((Flags & FLAG_C) !=0)
  1999. {
  2000. temp_word--;
  2001. }
  2002. set_carry_flag(temp_word);
  2003. set_flag_n((BYTE)temp_word);
  2004. set_flag_z((BYTE)temp_word);
  2005. set_flag_v(regB,lb,(BYTE)temp_word);
  2006. Registers[REGISTER_B]=(BYTE)temp_word;
  2007. break;
  2008.  
  2009. case 0xE2: //SBCB Index
  2010. regB = Registers[REGISTER_B];
  2011. address = IndexRegister + (WORD)fetch();
  2012. lb=fetch();
  2013. temp_word=(WORD)Registers[REGISTER_B]-(WORD)lb;
  2014. if ((address >=0) && (address < MEMORY_SIZE))
  2015. {
  2016. lb = Memory[address];
  2017. }
  2018. else
  2019. {
  2020. lb = 0;
  2021. }
  2022. if((Flags & FLAG_C) !=0)
  2023. {
  2024. temp_word--;
  2025. }
  2026. set_carry_flag(temp_word);
  2027. set_flag_n((BYTE)temp_word);
  2028. set_flag_z((BYTE)temp_word);
  2029. set_flag_v(regB,lb,(BYTE)temp_word);
  2030. Registers[REGISTER_B]=(BYTE)temp_word;
  2031. break;
  2032.  
  2033. case 0xF2: //SBCB Extended
  2034. hb=(WORD)fetch();
  2035. lb=(WORD)fetch();
  2036. address=(hb<<8)+lb;
  2037. regB=Registers[REGISTER_B];
  2038. temp_word=(WORD)Registers[REGISTER_B]-(WORD)lb;
  2039. if ((address >=0) && (address < MEMORY_SIZE))
  2040. {
  2041. lb = Memory[address];
  2042. }
  2043. else
  2044. {
  2045. lb = 0;
  2046. }
  2047. if((Flags & FLAG_C) !=0)
  2048. {
  2049. temp_word--;
  2050. }
  2051. set_carry_flag(temp_word);
  2052. set_flag_n((BYTE)temp_word);
  2053. set_flag_z((BYTE)temp_word);
  2054. set_flag_v(regB,lb,(BYTE)temp_word);
  2055. Registers[REGISTER_B]=(BYTE)temp_word;
  2056. break;
  2057.  
  2058. case 0x8C: //CPX Immediate
  2059. wdata = (((WORD) fetch()) << 8) + fetch();
  2060. wresult = IndexRegister - wdata;
  2061. //flags
  2062. set_flag_z(wresult);
  2063. set_flag_n(wresult);
  2064. set_flag_v((BYTE)IndexRegister >> 8,(BYTE)wdata,(BYTE)wresult >> 8);
  2065. break;
  2066.  
  2067. case 0x9C: //CPX Direct
  2068. address = fetch();
  2069. hb = Memory[address];
  2070. lb = Memory[address+1];
  2071. wdata = (((WORD) hb) << 8) + lb;
  2072. wresult = IndexRegister - wdata;
  2073. //flags
  2074. set_flag_z(wresult);
  2075. set_flag_n(wresult);
  2076. set_flag_v((BYTE)IndexRegister >> 8,(BYTE)wdata,(BYTE)wresult >> 8);
  2077. break;
  2078.  
  2079. case 0xAC: //CPX Index
  2080. address = IndexRegister + (WORD) fetch;
  2081. hb = Memory[address];
  2082. lb = Memory[address+1];
  2083. wdata = (((WORD) hb) << 8) + lb;
  2084. wresult = IndexRegister - wdata;
  2085. //flags
  2086. set_flag_z(wresult);
  2087. set_flag_n(wresult);
  2088. set_flag_v((BYTE)IndexRegister >> 8,(BYTE)wdata,(BYTE)wresult >> 8);
  2089. break;
  2090.  
  2091. case 0xBC: //CPX Extended
  2092. hb=(WORD)fetch();
  2093. lb=(WORD)fetch();
  2094. address=(hb<<8)+lb;
  2095. hb = Memory[address];
  2096. lb = Memory[address+1];
  2097. wdata = (((WORD) hb) << 8) + lb;
  2098. wresult = IndexRegister - wdata;
  2099. //flags
  2100. set_flag_z(wresult);
  2101. set_flag_n(wresult);
  2102. set_flag_v((BYTE)IndexRegister >> 8,(BYTE)wdata,(BYTE)wresult >> 8);
  2103. break;
  2104.  
  2105. case 0x88: //EORA Immediate
  2106. lb=fetch();
  2107. temp_word=(WORD)Registers[REGISTER_A] ^ (WORD)lb;
  2108. //flags
  2109. Flags = Flags & (0xFF - FLAG_V);
  2110. set_flag_n((BYTE)temp_word);
  2111. set_flag_z((BYTE)temp_word);
  2112. Registers[REGISTER_A]=(BYTE)temp_word;
  2113. break;
  2114.  
  2115. case 0x98: //EORA Direct
  2116. address=(WORD)fetch();
  2117. if ((address >= 0) ^ (address < MEMORY_SIZE))
  2118. {
  2119. lb = Memory[address];
  2120. }
  2121. else
  2122. {
  2123. lb = 0;
  2124. }
  2125. temp_word=(WORD)Registers[REGISTER_A]^(WORD)lb;
  2126. //flags
  2127. set_flag_n((BYTE)temp_word);
  2128. set_flag_z((BYTE)temp_word);
  2129. Flags = Flags & (0xFF - FLAG_V);
  2130. Registers[REGISTER_A]=(BYTE)temp_word;
  2131. break;
  2132.  
  2133. case 0xA8: //EORA Index
  2134. address = IndexRegister + (WORD)fetch();
  2135. if ((address >= 0) ^ (address < MEMORY_SIZE))
  2136. {
  2137. lb = Memory[address];
  2138. }
  2139. else
  2140. {
  2141. lb = 0;
  2142. }
  2143. temp_word = (WORD) Registers[REGISTER_A] ^ (WORD)lb;
  2144. //flags
  2145. set_flag_n((BYTE)temp_word);
  2146. set_flag_z((BYTE)temp_word);
  2147. Flags = Flags & (0xFF - FLAG_V);
  2148. Registers[REGISTER_A] = (BYTE)temp_word;
  2149. break;
  2150.  
  2151. case 0xB8: //EORA Extended
  2152. hb=(WORD)fetch();
  2153. lb=(WORD)fetch();
  2154. address=(hb<<8)+lb;
  2155. address=(WORD)fetch();
  2156. if ((address >= 0) ^ (address < MEMORY_SIZE))
  2157. {
  2158. lb = Memory[address];
  2159. }
  2160. else
  2161. {
  2162. lb = 0;
  2163. }
  2164. temp_word = (WORD) Registers[REGISTER_A] ^ (WORD)lb;
  2165. //flags
  2166. set_flag_n((BYTE)temp_word);
  2167. set_flag_z((BYTE)temp_word);
  2168. Flags = Flags & (0xFF - FLAG_V);
  2169. Registers[REGISTER_A]=(BYTE)temp_word;
  2170. break;
  2171.  
  2172. case 0xC8: //EORB Immediate
  2173. lb=fetch();
  2174. temp_word=(WORD)Registers[REGISTER_B] ^ (WORD)lb;
  2175. //flags
  2176. Flags = Flags & (0xFF - FLAG_V);
  2177. set_flag_n((BYTE)temp_word);
  2178. set_flag_z((BYTE)temp_word);
  2179. Registers[REGISTER_B]=(BYTE)temp_word;
  2180. break;
  2181.  
  2182. case 0xD8: //EORB Direct
  2183. address=(WORD)fetch();
  2184. if ((address >= 0) ^ (address < MEMORY_SIZE))
  2185. {
  2186. lb = Memory[address];
  2187. }
  2188. else
  2189. {
  2190. lb = 0;
  2191. }
  2192. temp_word=(WORD)Registers[REGISTER_B]^(WORD)lb;
  2193. //flags
  2194. set_flag_n((BYTE)temp_word);
  2195. set_flag_z((BYTE)temp_word);
  2196. Flags = Flags & (0xFF - FLAG_V);
  2197. Registers[REGISTER_B]=(BYTE)temp_word;
  2198. break;
  2199.  
  2200. case 0xE8: //EORB Index
  2201. address = IndexRegister + (WORD)fetch();
  2202. if ((address >= 0) ^ (address < MEMORY_SIZE))
  2203. {
  2204. lb = Memory[address];
  2205. }
  2206. else
  2207. {
  2208. lb = 0;
  2209. }
  2210. temp_word = (WORD) Registers[REGISTER_B] ^ (WORD)lb;
  2211. //flags
  2212. set_flag_n((BYTE)temp_word);
  2213. set_flag_z((BYTE)temp_word);
  2214. Flags = Flags & (0xFF - FLAG_V);
  2215. Registers[REGISTER_B] = (BYTE)temp_word;
  2216. break;
  2217.  
  2218. case 0xF8: //EORB Extended
  2219. hb=(WORD)fetch();
  2220. lb=(WORD)fetch();
  2221. address=(hb<<8)+lb;
  2222. address=(WORD)fetch();
  2223. if ((address >= 0) ^ (address < MEMORY_SIZE))
  2224. {
  2225. lb = Memory[address];
  2226. }
  2227. else
  2228. {
  2229. lb = 0;
  2230. }
  2231. temp_word = (WORD) Registers[REGISTER_B] ^ (WORD)lb;
  2232. //flags
  2233. set_flag_n((BYTE)temp_word);
  2234. set_flag_z((BYTE)temp_word);
  2235. Flags = Flags & (0xFF - FLAG_V);
  2236. Registers[REGISTER_B]=(BYTE)temp_word;
  2237. break;
  2238.  
  2239. case 0x8A: //ORAA Immediate
  2240. lb=fetch();
  2241. temp_word=(WORD)Registers[REGISTER_A]|(WORD)lb;
  2242. //flags
  2243. Flags = Flags & (0xFF - FLAG_V);
  2244. set_flag_n((BYTE)temp_word);
  2245. set_flag_z((BYTE)temp_word);
  2246. Registers[REGISTER_A]=(BYTE)temp_word;
  2247. break;
  2248.  
  2249. case 0x9A: //ORAA Direct
  2250. address=(WORD)fetch();
  2251. if ((address >= 0) | (address < MEMORY_SIZE))
  2252. {
  2253. lb = Memory[address];
  2254. }
  2255. else
  2256. {
  2257. lb = 0;
  2258. }
  2259. temp_word=(WORD)Registers[REGISTER_A]|(WORD)lb;
  2260. //flags
  2261. set_flag_n((BYTE)temp_word);
  2262. set_flag_z((BYTE)temp_word);
  2263. Flags = Flags & (0xFF - FLAG_V);
  2264. Registers[REGISTER_A]=(BYTE)temp_word;
  2265. break;
  2266.  
  2267. case 0xAA: //ORAA Index
  2268. address = IndexRegister + (WORD)fetch();
  2269. if ((address >= 0) | (address < MEMORY_SIZE))
  2270. {
  2271. lb = Memory[address];
  2272. }
  2273. else
  2274. {
  2275. lb = 0;
  2276. }
  2277. temp_word = (WORD) Registers[REGISTER_A] | (WORD)lb;
  2278. //flags
  2279. set_flag_n((BYTE)temp_word);
  2280. set_flag_z((BYTE)temp_word);
  2281. Flags = Flags & (0xFF - FLAG_V);
  2282. Registers[REGISTER_A] = (BYTE)temp_word;
  2283. break;
  2284.  
  2285. case 0xBA: //ORAA Extended
  2286. hb=(WORD)fetch();
  2287. lb=(WORD)fetch();
  2288. address=(hb<<8)+lb;
  2289. address=(WORD)fetch();
  2290. if ((address >= 0) | (address < MEMORY_SIZE))
  2291. {
  2292. lb = Memory[address];
  2293. }
  2294. else
  2295. {
  2296. lb = 0;
  2297. }
  2298. temp_word = (WORD) Registers[REGISTER_A] | (WORD)lb;
  2299. //flags
  2300. set_flag_n((BYTE)temp_word);
  2301. set_flag_z((BYTE)temp_word);
  2302. Flags = Flags & (0xFF - FLAG_V);
  2303. Registers[REGISTER_A]=(BYTE)temp_word;
  2304. break;
  2305.  
  2306. case 0xCA: //ORAB Immediate
  2307. lb=fetch();
  2308. temp_word=(WORD)Registers[REGISTER_B] | (WORD)lb;
  2309. //flags
  2310. Flags = Flags & (0xFF - FLAG_V);
  2311. set_flag_n((BYTE)temp_word);
  2312. set_flag_z((BYTE)temp_word);
  2313. Registers[REGISTER_B]=(BYTE)temp_word;
  2314. break;
  2315.  
  2316. case 0xDA: //ORAB Direct
  2317. address=(WORD)fetch();
  2318. if ((address >= 0) | (address < MEMORY_SIZE))
  2319. {
  2320. lb = Memory[address];
  2321. }
  2322. else
  2323. {
  2324. lb = 0;
  2325. }
  2326. temp_word=(WORD)Registers[REGISTER_B]|(WORD)lb;
  2327. //flags
  2328. set_flag_n((BYTE)temp_word);
  2329. set_flag_z((BYTE)temp_word);
  2330. Flags = Flags & (0xFF - FLAG_V);
  2331. Registers[REGISTER_B]=(BYTE)temp_word;
  2332. break;
  2333.  
  2334. case 0xEA: //ORAB Index
  2335. address = IndexRegister + (WORD)fetch();
  2336. if ((address >= 0) | (address < MEMORY_SIZE))
  2337. {
  2338. lb = Memory[address];
  2339. }
  2340. else
  2341. {
  2342. lb = 0;
  2343. }
  2344. temp_word = (WORD) Registers[REGISTER_B] | (WORD)lb;
  2345. //flags
  2346. set_flag_n((BYTE)temp_word);
  2347. set_flag_z((BYTE)temp_word);
  2348. Flags = Flags & (0xFF - FLAG_V);
  2349. Registers[REGISTER_B] = (BYTE)temp_word;
  2350. break;
  2351.  
  2352. case 0xFA: //ORAB Extended
  2353. hb=(WORD)fetch();
  2354. lb=(WORD)fetch();
  2355. address=(hb<<8)+lb;
  2356. address=(WORD)fetch();
  2357. if ((address >= 0) | (address < MEMORY_SIZE))
  2358. {
  2359. lb = Memory[address];
  2360. }
  2361. else
  2362. {
  2363. lb = 0;
  2364. }
  2365. temp_word = (WORD) Registers[REGISTER_B] | (WORD)lb;
  2366. //flags
  2367. set_flag_n((BYTE)temp_word);
  2368. set_flag_z((BYTE)temp_word);
  2369. Flags = Flags & (0xFF - FLAG_V);
  2370. Registers[REGISTER_B]=(BYTE)temp_word;
  2371. break;
  2372.  
  2373. default:
  2374. break;
  2375. }
  2376. }
  2377.  
  2378.  
  2379. void Group_2_Single_Operand_Instructions(BYTE opcode)
  2380. {
  2381. BYTE regA;
  2382. BYTE regB;
  2383. BYTE lb;
  2384. BYTE hb;
  2385. BYTE byte_address;
  2386. BYTE saved_flags;
  2387. WORD wdata;
  2388. WORD hi_address, lo_address;
  2389. WORD address;
  2390. WORD temp_word;
  2391. WORD offset;
  2392.  
  2393. switch (opcode)
  2394. {
  2395. case 0x6E: //JMP indexed
  2396. address = IndexRegister + (WORD)fetch();
  2397. hb = Memory[address];
  2398. lb = Memory[address+1];
  2399. address = ((WORD)hb << 8) +(WORD)lb;
  2400. if (( address >=0) && (address < MEMORY_SIZE))
  2401. {
  2402. ProgramCounter = address;
  2403. }
  2404. break;
  2405.  
  2406. case 0x7E: //JMP Extended
  2407. hb = fetch();
  2408. lb = fetch();
  2409. address = ((WORD)hb << 8) + (WORD)lb;
  2410. if (( address >=0) && (address < MEMORY_SIZE))
  2411. {
  2412. ProgramCounter = address;
  2413. }
  2414. break;
  2415.  
  2416. case 0x4C: //INCA
  2417. Registers[REGISTER_A] = Registers[REGISTER_A] + 1;
  2418. set_flag_n(Registers[REGISTER_A]);
  2419. set_flag_z(Registers[REGISTER_A]);
  2420. if (Registers[REGISTER_A] == 0x80)
  2421. {
  2422. Flags = Flags | FLAG_V;
  2423. }
  2424. else
  2425. {
  2426. Flags = Flags & (0xFF - FLAG_V);
  2427. }
  2428. break;
  2429.  
  2430. case 0x5C: //INCB
  2431. Registers[REGISTER_B] = Registers[REGISTER_B] + 1;
  2432. set_flag_n(Registers[REGISTER_B]);
  2433. set_flag_z(Registers[REGISTER_B]);
  2434. Registers[REGISTER_B];
  2435. if (Registers[REGISTER_B] == 0x80)
  2436. {
  2437. Flags = Flags | FLAG_V;
  2438. }
  2439. else
  2440. {
  2441. Flags = Flags & (0xFF - FLAG_V);
  2442. }
  2443. break;
  2444.  
  2445. case 0x6C: //INC Indexed
  2446. address = IndexRegister + (WORD) fetch();
  2447. Memory[address]++;
  2448. if ((address >=0) && (address < MEMORY_SIZE))
  2449. {
  2450. lb = Memory[address];
  2451. }
  2452. else
  2453. {
  2454. lb = 0;
  2455. }
  2456. set_flag_n(Memory[address]);
  2457. set_flag_z(Memory[address]);
  2458. if (Memory[address] == 0x80)
  2459. {
  2460. Flags = Flags | FLAG_V;
  2461. }
  2462. else
  2463. {
  2464. Flags = Flags & (0xFF - FLAG_V);
  2465. }
  2466. break;
  2467.  
  2468. case 0x7C: //INC Extended
  2469. hb = fetch();
  2470. lb = fetch();
  2471. address = ((WORD)hb << 8) + (WORD)lb;
  2472. Memory[address]++;
  2473. if ((address >=0) && (address < MEMORY_SIZE))
  2474. {
  2475. lb = Memory[address];
  2476. }
  2477. else
  2478. {
  2479. lb = 0;
  2480. }
  2481. set_flag_n(Memory[address]);
  2482. set_flag_z(Memory[address]);
  2483. if (address == 0x80)
  2484. {
  2485. Flags = Flags | FLAG_V;
  2486. }
  2487. else
  2488. {
  2489. Flags = Flags & (0xFF - FLAG_V);
  2490. }
  2491. break;
  2492.  
  2493. case 0x6A: //DEC Indexed
  2494. address = IndexRegister + (WORD) fetch();
  2495. Memory[address]--;
  2496. set_flag_n((BYTE)address);
  2497. set_flag_z((BYTE)address);
  2498. if (address == 0x7F)
  2499. {
  2500. Flags = Flags | FLAG_V;
  2501. }
  2502. else
  2503. {
  2504. Flags = Flags & (0xFF - FLAG_V);
  2505. }
  2506. break;
  2507.  
  2508. case 0x7A: //DEC Extended
  2509. hb = fetch();
  2510. lb = fetch();
  2511. address = ((WORD)hb << 8) - (WORD)lb;
  2512. Memory[address]--;
  2513. set_flag_n((BYTE)address);
  2514. set_flag_z((BYTE)address);
  2515. if (address == 0x7F)
  2516. {
  2517. Flags = Flags | FLAG_V;
  2518. }
  2519. else
  2520. {
  2521. Flags = Flags & (0xFF - FLAG_V);
  2522. }
  2523. break;
  2524.  
  2525. case 0x4A: //DECA
  2526. Registers[REGISTER_A]--;
  2527. set_flag_n(Registers[REGISTER_A]);
  2528. set_flag_z(Registers[REGISTER_A]);
  2529. Registers[REGISTER_A];
  2530. if (Registers[REGISTER_A] == 0x7F)
  2531. {
  2532. Flags = Flags | FLAG_V;
  2533. }
  2534. else
  2535. {
  2536. Flags = Flags & (0xFF - FLAG_V);
  2537. }
  2538. break;
  2539.  
  2540. case 0x5A: //DECB
  2541. Registers[REGISTER_B]--;
  2542. set_flag_n(Registers[REGISTER_B]);
  2543. set_flag_z(Registers[REGISTER_B]);
  2544. Registers[REGISTER_B];
  2545. if (Registers[REGISTER_B] == 0x7F)
  2546. {
  2547. Flags = Flags | FLAG_V;
  2548. }
  2549. else
  2550. {
  2551. Flags = Flags & (0xFF - FLAG_V);
  2552. }
  2553. break;
  2554.  
  2555. case 0x4F: //CLRA Inherent
  2556. Registers[REGISTER_A] = 0;
  2557. Flags = Flags & (0xFF - FLAG_N);
  2558. Flags = Flags & (0xFF - FLAG_V);
  2559. Flags = Flags & (0xFF - FLAG_C);
  2560. set_flag_z((BYTE)Registers[REGISTER_A]);
  2561. break;
  2562.  
  2563. case 0x5F: //CLRB Inherent
  2564. Registers[REGISTER_B] = 0;
  2565. Flags = Flags & (0xFF - FLAG_N);
  2566. Flags = Flags & (0xFF - FLAG_V);
  2567. Flags = Flags & (0xFF - FLAG_C);
  2568. set_flag_z((BYTE)Registers[REGISTER_B]);
  2569. break;
  2570.  
  2571. case 0x6F: //CLR Index
  2572. address = IndexRegister + (WORD) fetch();
  2573. Memory[address] = 0;
  2574. //Flags
  2575. Flags = Flags & (0xFF - FLAG_N);
  2576. Flags = Flags & (0xFF - FLAG_V);
  2577. Flags = Flags & (0xFF - FLAG_C);
  2578. set_flag_z((BYTE)address);
  2579. break;
  2580.  
  2581. case 0x7F: //CLR Extended
  2582. hb = fetch();
  2583. lb = fetch();
  2584. address = ((WORD)hb << 8) + (WORD)lb;
  2585. Memory[address] = 0;
  2586. //Flags
  2587. Flags = Flags & (0xFF - FLAG_N);
  2588. Flags = Flags & (0xFF - FLAG_V);
  2589. Flags = Flags & (0xFF - FLAG_C);
  2590. set_flag_z((BYTE)address);
  2591. break;
  2592.  
  2593. case 0x43: //COMA
  2594. Registers[REGISTER_A] = Registers[REGISTER_A] ^ 0xFF;
  2595. set_flag_n(Registers[REGISTER_A]);
  2596. set_flag_z(Registers[REGISTER_A]);
  2597. Flags = Flags & (0xFF - FLAG_V);
  2598. Flags = Flags | FLAG_C;
  2599. break;
  2600.  
  2601. case 0x53: // COMB
  2602. Registers[REGISTER_B] = Registers[REGISTER_B] ^ 0xFF;
  2603. set_flag_n(Registers[REGISTER_B]);
  2604. set_flag_z(Registers[REGISTER_B]);
  2605. Flags = Flags & (0xFF - FLAG_V);
  2606. Flags = Flags | FLAG_C;
  2607. break;
  2608.  
  2609. case 0x63: // COM Index
  2610. address = IndexRegister + fetch();
  2611. if ((address >=0) && (address < MEMORY_SIZE))
  2612. {
  2613. temp_word = Memory[address];
  2614. }
  2615. else
  2616. {
  2617. temp_word = 0;
  2618. }
  2619. temp_word = temp_word ^ 0xFF;
  2620. Memory[address] = temp_word;
  2621. set_flag_n(temp_word);
  2622. set_flag_z(temp_word);
  2623. Flags = Flags & (0xFF - FLAG_V);
  2624. Flags = Flags | FLAG_C;
  2625. break;
  2626.  
  2627. case 0x73: //COM Extended
  2628. hb = fetch();
  2629. lb = fetch();
  2630. address = ((WORD) hb << 8 ) + lb;
  2631. if ((address >=0) && (address < MEMORY_SIZE))
  2632. {
  2633. temp_word = Memory[address];
  2634. }
  2635. else
  2636. {
  2637. temp_word = 0;
  2638. }
  2639. temp_word = Memory[address];
  2640. temp_word = temp_word ^ 0xFF;
  2641. Memory[address] = temp_word;
  2642. set_flag_n(temp_word);
  2643. set_flag_z(temp_word);
  2644. Flags = Flags & (0xFF - FLAG_V);
  2645. Flags = Flags | FLAG_C;
  2646. break;
  2647.  
  2648. case 0x60: //NEG Indexed
  2649. address = IndexRegister + fetch();
  2650. if ((address >=0) && (address < MEMORY_SIZE))
  2651. {
  2652. temp_word = Memory[address];
  2653. }
  2654. else
  2655. {
  2656. temp_word = 0;
  2657. }
  2658. temp_word = (temp_word ^ 0xFF) + 1;
  2659. Memory[address] = temp_word;
  2660. set_flag_n(temp_word);
  2661. set_flag_z(temp_word);
  2662. if (Flags == 0x00)
  2663. {
  2664. Flags | FLAG_C;
  2665. }
  2666. if ((Flags & 0x80) == 0x80)
  2667. {
  2668. Flags | FLAG_V;
  2669. }
  2670. break;
  2671.  
  2672. case 0x70: //NEG Extended
  2673. hb = fetch();
  2674. lb = fetch();
  2675. address = ((WORD) hb << 8 ) + lb;
  2676. if ((address >=0) && (address < MEMORY_SIZE))
  2677. {
  2678. temp_word = Memory[address];
  2679. }
  2680. else
  2681. {
  2682. temp_word = 0;
  2683. }
  2684. temp_word = Memory[address];
  2685. temp_word = (temp_word ^ 0xFF) + 1;
  2686. Memory[address] = temp_word;
  2687. set_flag_n(temp_word);
  2688. set_flag_z(temp_word);
  2689. if (Flags == 0x00)
  2690. {
  2691. Flags | FLAG_C;
  2692. }
  2693. if ((Flags & 0x80) == 0x80)
  2694. {
  2695. Flags | FLAG_V;
  2696. }
  2697. break;
  2698.  
  2699. case 0x40: //NEGA
  2700. Registers[REGISTER_A] = (Registers[REGISTER_A] ^ 0xFF) + 1;
  2701. set_flag_n(Registers[REGISTER_A]);
  2702. set_flag_z(Registers[REGISTER_A]);
  2703. if (Flags == 0x00)
  2704. {
  2705. Flags | FLAG_C;
  2706. }
  2707. if ((Flags & 0x80) == 0x80)
  2708. {
  2709. Flags | FLAG_V;
  2710. }
  2711. break;
  2712.  
  2713. case 0x50: // NEGB
  2714. Registers[REGISTER_B] = (Registers[REGISTER_B] ^ 0xFF) + 1;
  2715. set_flag_n(Registers[REGISTER_B]);
  2716. set_flag_z(Registers[REGISTER_B]);
  2717. if (Flags == 0x00)
  2718. {
  2719. Flags | FLAG_C;
  2720. }
  2721. if ((Flags & 0x80) == 0x80)
  2722. {
  2723. Flags | FLAG_V;
  2724. }
  2725. break;
  2726.  
  2727. case 0x44: //LSRA
  2728. saved_flags = Flags;
  2729. if((Registers[REGISTER_A]& 0x01)==0x01) //carry
  2730. {
  2731. Flags=Flags |FLAG_C; //setting the carry flag.
  2732. }
  2733. else
  2734. {
  2735. Flags= Flags&(0xFF -FLAG_C);
  2736. }
  2737. Registers[REGISTER_A]=(Registers[REGISTER_A]>>1)&0x7F;
  2738. set_flag_z(Registers[REGISTER_A]);
  2739. set_flag_n(Registers[REGISTER_A]);
  2740. if (Registers[REGISTER_A] == 0x80)
  2741. {
  2742. Flags = Flags | FLAG_V;
  2743. }
  2744. else
  2745. {
  2746. Flags = Flags & (0xFF - FLAG_V);
  2747. }
  2748. break;
  2749.  
  2750. case 0x54: //LSRB
  2751. saved_flags = Flags;
  2752. if((Registers[REGISTER_B]& 0x01)==0x01) //carry
  2753. {
  2754. Flags=Flags |FLAG_C; //setting the carry flag.
  2755. }
  2756. else
  2757. {
  2758. Flags= Flags&(0xFF -FLAG_C);
  2759. }
  2760. Registers[REGISTER_B]=(Registers[REGISTER_B]>>1)&0x7F;
  2761. set_flag_z(Registers[REGISTER_B]);
  2762. set_flag_n(Registers[REGISTER_B]);
  2763. if (Registers[REGISTER_B] == 0x80)
  2764. {
  2765. Flags = Flags | FLAG_V;
  2766. }
  2767. else
  2768. {
  2769. Flags = Flags & (0xFF - FLAG_V);
  2770. }
  2771. break;
  2772.  
  2773. case 0x64: //LSR Index
  2774. saved_flags = Flags;
  2775. address = IndexRegister + (WORD) fetch();
  2776. if((Memory[address]& 0x01)==0x01) //carry
  2777. {
  2778. Flags=Flags |FLAG_C; //setting the carry flag.
  2779. }
  2780. else
  2781. {
  2782. Flags= Flags&(0xFF -FLAG_C);
  2783. }
  2784. Memory[address]=(Memory[address]>>1)&0x7F;
  2785. set_flag_z(Memory[address]);
  2786. set_flag_n(Memory[address]);
  2787. if (Memory[address] == 0x80)
  2788. {
  2789. Flags = Flags | FLAG_V;
  2790. }
  2791. else
  2792. {
  2793. Flags = Flags & (0xFF - FLAG_V);
  2794. }
  2795. break;
  2796.  
  2797. case 0x74: //LSR Extended
  2798. saved_flags = Flags;
  2799. hb = fetch();
  2800. lb = fetch();
  2801. address = ((WORD) hb << 8 ) + lb;
  2802. if((Memory[address]& 0x01)==0x01) //carry
  2803. {
  2804. Flags=Flags |FLAG_C; //setting the carry flag.
  2805. }
  2806. else
  2807. {
  2808. Flags= Flags&(0xFF -FLAG_C);
  2809. }
  2810. Memory[address]=(Memory[address]>>1)&0x7F;
  2811. set_flag_z(Memory[address]);
  2812. set_flag_n(Memory[address]);
  2813. if (Memory[address] == 0x80)
  2814. {
  2815. Flags = Flags | FLAG_V;
  2816. }
  2817. else
  2818. {
  2819. Flags = Flags & (0xFF - FLAG_V);
  2820. }
  2821. break;
  2822.  
  2823. case 0x48: //ASLA
  2824. saved_flags =Flags;
  2825. if((Registers[REGISTER_A]&0x80)==0x80) //carry
  2826. {
  2827. Flags= Flags | FLAG_C;
  2828. }
  2829. else
  2830. {
  2831. Flags=Flags&(0xFF - FLAG_C);
  2832. }
  2833. Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
  2834. if(((Registers[REGISTER_A]&0x80)==0x80)^((Flags &FLAG_C)==FLAG_C))//overflow
  2835. {
  2836. Flags =Flags | FLAG_V;
  2837. }
  2838. else
  2839. {
  2840. Flags = Flags &(0xFF - FLAG_V);
  2841. }
  2842. if((saved_flags & FLAG_C)==FLAG_C)
  2843. {
  2844. Registers[REGISTER_A]=Registers[REGISTER_A]|0x01;
  2845. }
  2846. set_flag_z(Registers[REGISTER_A]);
  2847. set_flag_n(Registers[REGISTER_A]);
  2848. break;
  2849.  
  2850. case 0x58: //ASLB
  2851. saved_flags =Flags;
  2852. if((Registers[REGISTER_B]&0x80)==0x80) //carry
  2853. {
  2854. Flags= Flags | FLAG_C;
  2855. }
  2856. else
  2857. {
  2858. Flags=Flags&(0xFF - FLAG_C);
  2859. }
  2860. Registers[REGISTER_B] = (Registers[REGISTER_B] << 1) & 0xFE;
  2861. if(((Registers[REGISTER_B]&0x80)==0x80)^((Flags &FLAG_C)==FLAG_C))//overflow
  2862. {
  2863. Flags =Flags | FLAG_V;
  2864. }
  2865. else
  2866. {
  2867. Flags = Flags &(0xFF - FLAG_V);
  2868. }
  2869. if((saved_flags & FLAG_C)==FLAG_C)
  2870. {
  2871. Registers[REGISTER_B]=Registers[REGISTER_B]|0x01;
  2872. }
  2873. set_flag_z(Registers[REGISTER_B]);
  2874. set_flag_n(Registers[REGISTER_B]);
  2875. break;
  2876.  
  2877. case 0x68: //ASL Index
  2878. saved_flags = Flags;
  2879. address = IndexRegister + (WORD) fetch();
  2880. if((address &0x80)==0x80) //carry
  2881. {
  2882. Flags= Flags | FLAG_C;
  2883. }
  2884. else
  2885. {
  2886. Flags=Flags&(0xFF - FLAG_C);
  2887. }
  2888. Memory[address] = (Memory[address] << 1) & 0xFE;
  2889. if(((Memory[address] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  2890. {
  2891. Flags = Flags | FLAG_V;
  2892. }
  2893. else
  2894. {
  2895. Flags = Flags &(0xFF - FLAG_V);
  2896. }
  2897. if((saved_flags & FLAG_C) == FLAG_C)
  2898. {
  2899. Memory[address]=Memory[address]|0x01;
  2900. }
  2901. set_flag_z(Memory[address]);
  2902. set_flag_n(Memory[address]);
  2903. break;
  2904.  
  2905. case 0x78: //ASL Extended
  2906. saved_flags = Flags;
  2907. hb = fetch();
  2908. lb = fetch();
  2909. address = ((WORD) hb << 8 ) + lb;
  2910. if((address &0x80)==0x80) //carry
  2911. {
  2912. Flags= Flags | FLAG_C;
  2913. }
  2914. else
  2915. {
  2916. Flags=Flags&(0xFF - FLAG_C);
  2917. }
  2918. Memory[address] = (Memory[address] << 1) & 0xFE;
  2919. if(((Memory[address] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  2920. {
  2921. Flags = Flags | FLAG_V;
  2922. }
  2923. else
  2924. {
  2925. Flags = Flags &(0xFF - FLAG_V);
  2926. }
  2927. if((saved_flags & FLAG_C) == FLAG_C)
  2928. {
  2929. Memory[address]=Memory[address]|0x01;
  2930. }
  2931. set_flag_z(Memory[address]);
  2932. set_flag_n(Memory[address]);
  2933. break;
  2934.  
  2935. case 0x47: //ASRA //// needs to be changed
  2936. saved_flags =Flags;
  2937. if((Registers[REGISTER_A]&0x80)==0x80) //carry
  2938. {
  2939. Flags= Flags | FLAG_C;
  2940. }
  2941. else
  2942. {
  2943. Flags=Flags&(0xFF - FLAG_C);
  2944. }
  2945. Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0xFE;
  2946. if((saved_flags & FLAG_C)==FLAG_C)
  2947. {
  2948. Registers[REGISTER_A]=Registers[REGISTER_A]|0x01;
  2949. }
  2950. set_flag_z(Registers[REGISTER_A]);
  2951. set_flag_n(Registers[REGISTER_A]);
  2952. if(((Registers[REGISTER_A]&0x80)==0x80)^((Flags &FLAG_C)==FLAG_C))//overflow
  2953. {
  2954. Flags =Flags | FLAG_V;
  2955. }
  2956. else
  2957. {
  2958. Flags = Flags &(0xFF - FLAG_V);
  2959. }
  2960. break;
  2961.  
  2962. case 0x57: //ASRB
  2963. saved_flags =Flags;
  2964. if((Registers[REGISTER_B]&0x80)==0x80) //carry
  2965. {
  2966. Flags= Flags | FLAG_C;
  2967. }
  2968. else
  2969. {
  2970. Flags=Flags&(0xFF - FLAG_C);
  2971. }
  2972. Registers[REGISTER_B] = (Registers[REGISTER_B] >> 1) & 0xFE;
  2973. if((saved_flags & FLAG_C)==FLAG_C)
  2974. {
  2975. Registers[REGISTER_B]=Registers[REGISTER_B]|0x01;
  2976. }
  2977. set_flag_z(Registers[REGISTER_B]);
  2978. set_flag_n(Registers[REGISTER_B]);
  2979. if(((Registers[REGISTER_A]&0x80)==0x80)^((Flags &FLAG_C)==FLAG_C))//overflow
  2980. {
  2981. Flags =Flags | FLAG_V;
  2982. }
  2983. else
  2984. {
  2985. Flags = Flags &(0xFF - FLAG_V);
  2986. }
  2987. break;
  2988.  
  2989. case 0x67: //ASR index
  2990. saved_flags = Flags;
  2991. address = IndexRegister + (WORD) fetch();
  2992. if((address &0x80)==0x80) //carry
  2993. {
  2994. Flags= Flags | FLAG_C;
  2995. }
  2996. else
  2997. {
  2998. Flags=Flags&(0xFF - FLAG_C);
  2999. }
  3000. Memory[address] = (Memory[address] >> 1) & 0xFE;
  3001. if((saved_flags & FLAG_C) == FLAG_C)
  3002. {
  3003. Memory[address]=Memory[address]|0x01;
  3004. }
  3005. set_flag_z(Memory[address]);
  3006. set_flag_n(Memory[address]);
  3007. if(((Memory[address] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3008. {
  3009. Flags = Flags | FLAG_V;
  3010. }
  3011. else
  3012. {
  3013. Flags = Flags &(0xFF - FLAG_V);
  3014. }
  3015. break;
  3016.  
  3017. case 0x77: //ASR Extended
  3018. saved_flags = Flags;
  3019. hb = fetch();
  3020. lb = fetch();
  3021. address = ((WORD) hb << 8 ) + lb;
  3022. if((address &0x80)==0x80) //carry
  3023. {
  3024. Flags= Flags | FLAG_C;
  3025. }
  3026. else
  3027. {
  3028. Flags=Flags&(0xFF - FLAG_C);
  3029. }
  3030. Memory[address] = (Memory[address] >> 1) & 0xFE;
  3031. if((saved_flags & FLAG_C) == FLAG_C)
  3032. {
  3033. Memory[address]=Memory[address]|0x01;
  3034. }
  3035. set_flag_z(Memory[address]);
  3036. set_flag_n(Memory[address]);
  3037. if(((Memory[address] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3038. {
  3039. Flags = Flags | FLAG_V;
  3040. }
  3041. else
  3042. {
  3043. Flags = Flags &(0xFF - FLAG_V);
  3044. }
  3045. break;
  3046.  
  3047. case 0x49: //ROLA
  3048. saved_flags = Flags;
  3049. if((Registers[REGISTER_A]&0x80)==0x80) //carry
  3050. {
  3051. Flags= Flags | FLAG_C;
  3052. }
  3053. else
  3054. {
  3055. Flags=Flags&(0xFF - FLAG_C);
  3056. }
  3057. Registers[REGISTER_A]=(Registers[REGISTER_A]<<1) & 0xFE;
  3058. if(((Registers[REGISTER_A] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3059. {
  3060. Flags = Flags | FLAG_V;
  3061. }
  3062. else
  3063. {
  3064. Flags = Flags &(0xFF - FLAG_V);
  3065. }
  3066. if((saved_flags & FLAG_C) == FLAG_C)
  3067. {
  3068. Registers[REGISTER_A]=Registers[REGISTER_A]|0x01;
  3069. }
  3070. set_flag_z(Registers[REGISTER_A]);
  3071. set_flag_n(Registers[REGISTER_A]);
  3072. break;
  3073.  
  3074. case 0x59: //ROLB
  3075. saved_flags = Flags;
  3076. if((Registers[REGISTER_B]&0x80)==0x80) //carry
  3077. {
  3078. Flags= Flags | FLAG_C;
  3079. }
  3080. else
  3081. {
  3082. Flags=Flags&(0xFF - FLAG_C);
  3083. }
  3084. Registers[REGISTER_B]=(Registers[REGISTER_B]<<1) & 0xFE;
  3085. if(((Registers[REGISTER_B] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3086. {
  3087. Flags = Flags | FLAG_V;
  3088. }
  3089. else
  3090. {
  3091. Flags = Flags &(0xFF - FLAG_V);
  3092. }
  3093. if((saved_flags & FLAG_C) == FLAG_C)
  3094. {
  3095. Registers[REGISTER_B]=Registers[REGISTER_B]|0x01;
  3096. }
  3097. set_flag_z(Registers[REGISTER_B]);
  3098. set_flag_n(Registers[REGISTER_B]);
  3099. break;
  3100.  
  3101. case 0x69: //ROL Index
  3102. saved_flags = Flags;
  3103. address = IndexRegister + (WORD) fetch();
  3104. if((address &0x80)==0x80) //carry
  3105. {
  3106. Flags= Flags | FLAG_C;
  3107. }
  3108. else
  3109. {
  3110. Flags=Flags&(0xFF - FLAG_C);
  3111. }
  3112. Memory[address]=(Memory[address]<<1) & 0xFE;
  3113. if(((Memory[address] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3114. {
  3115. Flags = Flags | FLAG_V;
  3116. }
  3117. else
  3118. {
  3119. Flags = Flags &(0xFF - FLAG_V);
  3120. }
  3121. if((saved_flags & FLAG_C) == FLAG_C)
  3122. {
  3123. Memory[address]=Memory[address]|0x01;
  3124. }
  3125. set_flag_z(Memory[address]);
  3126. set_flag_n(Memory[address]);
  3127. break;
  3128.  
  3129. case 0x79: //ROL Extended
  3130. saved_flags = Flags;
  3131. hb = fetch();
  3132. lb = fetch();
  3133. address = ((WORD) hb << 8 ) + lb;
  3134. if((address &0x80)==0x80) //carry
  3135. {
  3136. Flags= Flags | FLAG_C;
  3137. }
  3138. else
  3139. {
  3140. Flags=Flags&(0xFF - FLAG_C);
  3141. }
  3142. Memory[address]=(Memory[address]<<1) & 0xFE;
  3143. if(((Memory[address] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3144. {
  3145. Flags = Flags | FLAG_V;
  3146. }
  3147. else
  3148. {
  3149. Flags = Flags &(0xFF - FLAG_V);
  3150. }
  3151. if((saved_flags & FLAG_C) == FLAG_C)
  3152. {
  3153. Memory[address]=Memory[address]|0x01;
  3154. }
  3155. set_flag_z(Memory[address]);
  3156. set_flag_n(Memory[address]);
  3157. break;
  3158.  
  3159. case 0x46: //RORA ///// RORS may need to be changed
  3160. saved_flags = Flags;
  3161. if((Registers[REGISTER_A]&0x80)==0x80) //carry
  3162. {
  3163. Flags= Flags | FLAG_C;
  3164. }
  3165. else
  3166. {
  3167. Flags=Flags&(0xFF - FLAG_C);
  3168. }
  3169. Registers[REGISTER_A]=(Registers[REGISTER_A]>>1) & 0xFE;
  3170. if(((Registers[REGISTER_A] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3171. {
  3172. Flags = Flags | FLAG_V;
  3173. }
  3174. else
  3175. {
  3176. Flags = Flags &(0xFF - FLAG_V);
  3177. }
  3178. if((saved_flags & FLAG_C) == FLAG_C)
  3179. {
  3180. Registers[REGISTER_A]=Registers[REGISTER_A]|0x01;
  3181. }
  3182. set_flag_z(Registers[REGISTER_A]);
  3183. set_flag_n(Registers[REGISTER_A]);
  3184. if(((Registers[REGISTER_A] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3185. {
  3186. Flags = Flags | FLAG_V;
  3187. }
  3188. else
  3189. {
  3190. Flags = Flags &(0xFF - FLAG_V);
  3191. }
  3192. break;
  3193.  
  3194. case 0x56: //RORB
  3195. saved_flags = Flags;
  3196. if((Registers[REGISTER_B]&0x80)==0x80) //carry
  3197. {
  3198. Flags= Flags | FLAG_C;
  3199. }
  3200. else
  3201. {
  3202. Flags=Flags&(0xFF - FLAG_C);
  3203. }
  3204. Registers[REGISTER_B]=(Registers[REGISTER_B]>>1) & 0xFE;
  3205.  
  3206. if((saved_flags & FLAG_C) == FLAG_C)
  3207. {
  3208. Registers[REGISTER_B]=Registers[REGISTER_B]|0x01;
  3209. }
  3210. set_flag_z(Registers[REGISTER_B]);
  3211. set_flag_n(Registers[REGISTER_B]);
  3212. if(((Registers[REGISTER_B] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3213. {
  3214. Flags = Flags | FLAG_V;
  3215. }
  3216. else
  3217. {
  3218. Flags = Flags &(0xFF - FLAG_V);
  3219. }
  3220. break;
  3221.  
  3222. case 0x66: //ROR Index
  3223. saved_flags = Flags;
  3224. address = IndexRegister + (WORD) fetch();
  3225. if((address &0x80)==0x80) //carry
  3226. {
  3227. Flags= Flags | FLAG_C;
  3228. }
  3229. else
  3230. {
  3231. Flags=Flags&(0xFF - FLAG_C);
  3232. }
  3233. Memory[address]=(Memory[address]>>1) & 0xFE;
  3234.  
  3235. if((saved_flags & FLAG_C) == FLAG_C)
  3236. {
  3237. Memory[address]=Memory[address]|0x01;
  3238. }
  3239. set_flag_z(Memory[address]);
  3240. set_flag_n(Memory[address]);
  3241. if(((Memory[address] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3242. {
  3243. Flags = Flags | FLAG_V;
  3244. }
  3245. else
  3246. {
  3247. Flags = Flags &(0xFF - FLAG_V);
  3248. }
  3249. break;
  3250.  
  3251. case 0x76: //ROR Extended
  3252. saved_flags = Flags;
  3253. hb = fetch();
  3254. lb = fetch();
  3255. address = ((WORD) hb << 8 ) + lb;
  3256. if((address &0x80)==0x80) //carry
  3257. {
  3258. Flags= Flags | FLAG_C;
  3259. }
  3260. else
  3261. {
  3262. Flags=Flags&(0xFF - FLAG_C);
  3263. }
  3264. Memory[address]=(Memory[address]>>1) & 0xFE;
  3265. if((saved_flags & FLAG_C) == FLAG_C)
  3266. {
  3267. Memory[address]=Memory[address]|0x01;
  3268. }
  3269. set_flag_z(Memory[address]);
  3270. set_flag_n(Memory[address]);
  3271. if(((Memory[address] & 0x80)==0x80) ^ ((Flags & FLAG_C)==FLAG_C))//overflow
  3272. {
  3273. Flags = Flags | FLAG_V;
  3274. }
  3275. else
  3276. {
  3277. Flags = Flags &(0xFF - FLAG_V);
  3278. }
  3279. break;
  3280.  
  3281. case 0x4D: //TSTA
  3282. Registers[REGISTER_A] = Registers[REGISTER_A] - 0x00;
  3283. set_flag_z(Registers[REGISTER_A]);
  3284. set_flag_n(Registers[REGISTER_A]);
  3285. Flags = Flags & (0xFF - FLAG_V);
  3286. Flags = Flags & (0xFF - FLAG_C);
  3287.  
  3288. break;
  3289.  
  3290. case 0x5D: //TSTB
  3291. Registers[REGISTER_B] = Registers[REGISTER_B] - 0x00;
  3292. set_flag_z(Registers[REGISTER_B]);
  3293. set_flag_n(Registers[REGISTER_B]);
  3294. Flags = Flags & (0xFF - FLAG_V);
  3295. Flags = Flags & (0xFF - FLAG_C);
  3296. break;
  3297.  
  3298. case 0x6D: //TST Index
  3299. address = IndexRegister + (WORD) fetch();
  3300. Memory[address] = Memory[address] - 0x00;
  3301. set_flag_z(Memory[address]);
  3302. set_flag_n(Memory[address]);
  3303. Flags = Flags & (0xFF - FLAG_V);
  3304. Flags = Flags & (0xFF - FLAG_C);
  3305. break;
  3306.  
  3307. case 0x7D: //TST Extended
  3308. hb = fetch();
  3309. lb = fetch();
  3310. address = ((WORD) hb << 8 ) + lb;
  3311. Memory[address] = Memory[address] - 0x00;
  3312. set_flag_z(Memory[address]);
  3313. set_flag_n(Memory[address]);
  3314. Flags = Flags & (0xFF - FLAG_V);
  3315. Flags = Flags & (0xFF - FLAG_C);
  3316. break;
  3317.  
  3318.  
  3319. default:
  3320. break;
  3321. }
  3322. }
  3323.  
  3324.  
  3325.  
  3326. void Group_3_TPA_TAP_NOP_Instructions(BYTE opcode)
  3327. {
  3328.  
  3329. BYTE regA;
  3330. BYTE regB;
  3331. BYTE lb;
  3332. BYTE hb;
  3333. BYTE byte_address;
  3334. WORD wdata;
  3335. WORD hi_address, lo_address;
  3336. WORD address;
  3337. WORD temp_word;
  3338.  
  3339. switch (opcode)
  3340. {
  3341.  
  3342. case 0x06: //TAP inher
  3343. Flags = Registers[REGISTER_A];
  3344. break;
  3345.  
  3346. case 0x07: //TPA inher
  3347. Registers[REGISTER_A] = Flags;
  3348. break;
  3349.  
  3350. case 0x01: // NOP
  3351. break;
  3352.  
  3353.  
  3354. default:
  3355. break;
  3356. }
  3357.  
  3358.  
  3359. }
  3360.  
  3361.  
  3362. void Group_4_Condition_Code_Instructions(BYTE opcode)
  3363. {
  3364. BYTE regA;
  3365. BYTE regB;
  3366. BYTE lb;
  3367. BYTE hb;
  3368. BYTE byte_address;
  3369. WORD wdata;
  3370. WORD hi_address, lo_address;
  3371. WORD address;
  3372. WORD temp_word;
  3373. WORD offset;
  3374.  
  3375. switch (opcode)
  3376. {
  3377.  
  3378. case 0x0C: // CLC inher
  3379. Flags = Flags & (0xFF - FLAG_C);
  3380. break;
  3381.  
  3382. case 0x0E: // CLI inher
  3383. Flags = Flags & (0xFF - FLAG_I);
  3384. break;
  3385.  
  3386. case 0x0A: // CLV inher
  3387. Flags = Flags & (0xFF - FLAG_V);
  3388. break;
  3389.  
  3390. case 0x0D: //SEC inher
  3391. Flags = Flags | FLAG_C;
  3392. break;
  3393.  
  3394. case 0x0F: //SEI inher
  3395. Flags = Flags | FLAG_I;
  3396. break;
  3397.  
  3398. case 0x0B: //SEV inher
  3399. Flags = Flags | FLAG_V;
  3400. break;
  3401.  
  3402. case 0x08: //INX
  3403. IndexRegister++;
  3404. if (IndexRegister == 0)
  3405. {
  3406. Flags = Flags | FLAG_Z;
  3407. }
  3408. else
  3409. {
  3410. Flags = Flags & (0xFF - FLAG_Z);
  3411. }
  3412. break;
  3413.  
  3414. case 0x09: //DEX
  3415. IndexRegister--;
  3416. if (IndexRegister == 0)
  3417. {
  3418. Flags = Flags | FLAG_Z;
  3419. }
  3420. else
  3421. {
  3422. Flags = Flags & (0xFF - FLAG_Z);
  3423. }
  3424. break;
  3425.  
  3426.  
  3427.  
  3428.  
  3429.  
  3430.  
  3431. default:
  3432. break;
  3433. }
  3434. }
  3435.  
  3436.  
  3437. void Group_5_Accumulator_Instructions(BYTE opcode)
  3438. {
  3439. BYTE regA, lb, hb;
  3440. WORD temp_word;
  3441. switch(opcode)
  3442. {
  3443.  
  3444. case 0x10: //SBA
  3445. regA = Registers[REGISTER_A];
  3446. Registers[REGISTER_A] = Registers[REGISTER_A] - Registers[REGISTER_B];
  3447. //flags
  3448. set_carry_flag(Registers[REGISTER_A]);
  3449. set_flag_n(Registers[REGISTER_A]);
  3450. set_flag_z(Registers[REGISTER_A]);
  3451. set_flag_v(regA, Registers[REGISTER_B], Registers[REGISTER_A]);
  3452.  
  3453. break;
  3454.  
  3455. case 0x1B: //ABA Inher
  3456. regA = Registers[REGISTER_A];
  3457. temp_word = (WORD) Registers[REGISTER_A] + (WORD)Registers[REGISTER_B];
  3458. set_carry_flag(temp_word);
  3459. set_flag_n((BYTE)temp_word);
  3460. set_flag_z((BYTE)temp_word);
  3461. set_flag_v(regA, Registers[REGISTER_B], (BYTE)temp_word);
  3462. Registers[REGISTER_A] = (BYTE)temp_word;
  3463. break;
  3464.  
  3465. case 0x11: //CBA
  3466. regA = Registers[REGISTER_A];
  3467. temp_word = Registers[REGISTER_A] - Registers[REGISTER_B];
  3468. //flags
  3469. set_carry_flag(temp_word);
  3470. set_flag_n(temp_word);
  3471. set_flag_z(temp_word);
  3472. set_flag_v(regA, Registers[REGISTER_B], temp_word);
  3473. break;
  3474.  
  3475. case 0x19: // DAA inherent
  3476. temp_word = Registers[REGISTER_A];
  3477. lb = Registers[REGISTER_A] & 0x0F;
  3478. hb = Registers[REGISTER_A] >> 4;
  3479. if ((lb > 9) || (Flags & FLAG_C) == FLAG_C) {
  3480. lb = lb + 6;
  3481. }
  3482. if ((hb > 9) || (Flags & FLAG_C) == FLAG_C) {
  3483. hb = hb + 6;
  3484. }
  3485. Registers[REGISTER_A] = lb + (hb << 4);
  3486. temp_word = Registers[REGISTER_A];
  3487. set_flag_n((BYTE)temp_word);
  3488. set_flag_z((BYTE)temp_word);
  3489. set_flag_v(lb, hb, (BYTE)temp_word);
  3490. break;
  3491.  
  3492. case 0x16: //TAB
  3493. Registers[REGISTER_B] = Registers[REGISTER_A];
  3494. Flags = Flags & (0xFF - FLAG_V);
  3495. set_flag_n((BYTE)Registers[REGISTER_B]);
  3496. set_flag_z((BYTE)Registers[REGISTER_B]);
  3497. break;
  3498.  
  3499. case 0x17: //TBA
  3500. Registers[REGISTER_A] = Registers[REGISTER_B];
  3501. Flags = Flags & (0xFF - FLAG_V);
  3502. set_flag_n((BYTE)Registers[REGISTER_A]);
  3503. set_flag_z((BYTE)Registers[REGISTER_A]);
  3504. break;
  3505.  
  3506. default:
  3507. break;
  3508. }
  3509. }
  3510.  
  3511.  
  3512. void Group_6_Branch_Instructions(BYTE opcode)
  3513. {
  3514. BYTE regA;
  3515. BYTE regB;
  3516. BYTE lb,N,Z,V,C;
  3517. BYTE hb;
  3518. BYTE byte_address;
  3519. WORD wdata;
  3520. WORD hi_address, lo_address;
  3521. WORD address;
  3522. WORD temp_word;
  3523. WORD offset;
  3524.  
  3525. if ((Flags & FLAG_N) != 0)
  3526. {
  3527. N = 1;
  3528. }
  3529. else
  3530. {
  3531. N = 0;
  3532. }
  3533.  
  3534. if ((Flags & FLAG_Z) != 0)
  3535. {
  3536. Z = 1;
  3537. }
  3538. else
  3539. {
  3540. Z = 0;
  3541. }
  3542.  
  3543. if ((Flags & FLAG_V) != 0)
  3544. {
  3545. V = 1;
  3546. }
  3547. else
  3548. {
  3549. V = 0;
  3550. }
  3551.  
  3552. if ((Flags & FLAG_C) != 0)
  3553. {
  3554. C = 1;
  3555. }
  3556. else
  3557. {
  3558. C = 0;
  3559. }
  3560.  
  3561. switch (opcode)
  3562. {
  3563.  
  3564.  
  3565. case 0x20: //BRA Direct
  3566. lb = fetch();
  3567. offset = (WORD) lb;
  3568. if((offset & 0x80) !=0) // need to sign extend
  3569. {
  3570. offset = offset + 0xFF00;
  3571. }
  3572. address = ProgramCounter + offset;
  3573. ProgramCounter = address;
  3574. break;
  3575.  
  3576. case 0x24: //BCC Direct
  3577. lb = fetch();
  3578. if ((Flags & FLAG_C) != FLAG_C)
  3579. {
  3580. offset = (WORD) lb;
  3581. if((offset & 0x80) !=0)
  3582. {
  3583. offset = offset + 0xFF00;
  3584. }
  3585. address = ProgramCounter + offset;
  3586. ProgramCounter = address;
  3587. }
  3588. break;
  3589.  
  3590. case 0x25: //BCS Direct
  3591. lb = fetch();
  3592. if ((Flags & FLAG_C) != FLAG_C)
  3593. {
  3594. offset = (WORD) lb;
  3595. if((offset & 0x80) !=1)
  3596. {
  3597. offset = offset + 0xFF00;
  3598. }
  3599. address = ProgramCounter + offset;
  3600. ProgramCounter = address;
  3601. }
  3602. break;
  3603.  
  3604. case 0x27: //BEQ Direct
  3605. lb = fetch();
  3606. if ((Flags & FLAG_Z) != FLAG_Z)
  3607. {
  3608. offset = (WORD) lb;
  3609. if((offset & 0x80) !=1)
  3610. {
  3611. offset = offset + 0xFF00;
  3612. }
  3613. address = ProgramCounter + offset;
  3614. ProgramCounter = address;
  3615. }
  3616. break;
  3617.  
  3618. case 0x2C: //BGE Direct
  3619. lb = fetch();
  3620. if ((N ^V) == 0)
  3621. {
  3622. offset = (WORD) lb;
  3623. if((offset & 0x80) !=0)
  3624. {
  3625. offset = offset + 0xFF00;
  3626. }
  3627. address = ProgramCounter + offset;
  3628. ProgramCounter = address;
  3629. }
  3630. break;
  3631.  
  3632. case 0x2E: //BGT Direct
  3633. lb = fetch();
  3634. if ((Z | N ^ V) == 1)
  3635. {
  3636. offset = (WORD) lb;
  3637. if((offset & 0x80) !=0)
  3638. {
  3639. offset = offset + 0xFF00;
  3640. }
  3641. address = ProgramCounter + offset;
  3642. ProgramCounter = address;
  3643. }
  3644. break;
  3645.  
  3646. case 0x22: //BHI Direct
  3647. lb = fetch();
  3648. if (C | Z == 1)
  3649. {
  3650. offset = (WORD) lb;
  3651. if((offset & 0x80) !=0)
  3652. {
  3653. offset = offset + 0xFF00;
  3654. }
  3655. address = ProgramCounter + offset;
  3656. ProgramCounter = address;
  3657. }
  3658. break;
  3659.  
  3660. case 0x2F: //BLE Direct
  3661. lb = fetch();
  3662. if ((Z | N ^ V) == 1)
  3663. {
  3664. offset = (WORD) lb;
  3665. if((offset & 0x80) !=1)
  3666. {
  3667. offset = offset + 0xFF00;
  3668. }
  3669. address = ProgramCounter + offset;
  3670. ProgramCounter = address;
  3671. }
  3672. break;
  3673.  
  3674. case 0x23: //BLS Direct
  3675. lb = fetch();
  3676. if (C | Z ==1)
  3677. {
  3678. offset = (WORD) lb;
  3679. if((offset & 0x80) !=1)
  3680. {
  3681. offset = offset + 0xFF00;
  3682. }
  3683. address = ProgramCounter + offset;
  3684. ProgramCounter = address;
  3685. }
  3686.  
  3687. case 0x2D: //BLT DIRECT
  3688. lb = fetch();
  3689. if ( N ^ V == 1)
  3690. {
  3691. offset = (WORD) lb;
  3692. if((offset & 0x80) !=1)
  3693. {
  3694. offset = offset + 0xFF00;
  3695. }
  3696. address = ProgramCounter + offset;
  3697. ProgramCounter = address;
  3698. }
  3699. break;
  3700.  
  3701. case 0x2B: //BMI Direct
  3702. lb = fetch();
  3703. if ((Flags & FLAG_N) != FLAG_N)
  3704. {
  3705. offset = (WORD) lb;
  3706. if((offset & 0x80) !=1)
  3707. {
  3708. offset = offset + 0xFF00;
  3709. }
  3710. address = ProgramCounter + offset;
  3711. ProgramCounter = address;
  3712. }
  3713. break;
  3714.  
  3715. case 0x26: //BNE Direct
  3716. lb = fetch();
  3717. if ((Flags & FLAG_Z) != FLAG_Z)
  3718. {
  3719. offset = (WORD) lb;
  3720. if((offset & 0x80) !=0)
  3721. {
  3722. offset = offset + 0xFF00;
  3723. }
  3724. address = ProgramCounter + offset;
  3725. ProgramCounter = address;
  3726. }
  3727. break;
  3728.  
  3729. case 0x28: //BVC Direct
  3730. lb = fetch();
  3731. if ((Flags & FLAG_V) != FLAG_V)
  3732. {
  3733. offset = (WORD) lb;
  3734. if((offset & 0x80) !=0)
  3735. {
  3736. offset = offset + 0xFF00;
  3737. }
  3738. address = ProgramCounter + offset;
  3739. ProgramCounter = address;
  3740. }
  3741. break;
  3742.  
  3743. case 0x29: //BVS
  3744. lb = fetch();
  3745. if ((Flags & FLAG_V) != FLAG_V)
  3746. {
  3747. offset = (WORD) lb;
  3748. if((offset & 0x80) !=0)
  3749. {
  3750. offset = offset + 0xFF00;
  3751. }
  3752. address = ProgramCounter + offset;
  3753. ProgramCounter = address;
  3754. }
  3755. break;
  3756.  
  3757. case 0x2A: //BPL Direct
  3758. lb = fetch();
  3759. if ((Flags & FLAG_N) != FLAG_N)
  3760. {
  3761. offset = (WORD) lb;
  3762. if((offset & 0x80) !=0)
  3763. {
  3764. offset = offset + 0xFF00;
  3765. }
  3766. address = ProgramCounter + offset;
  3767. ProgramCounter = address;
  3768. }
  3769. break;
  3770.  
  3771.  
  3772.  
  3773. default:
  3774. break;
  3775.  
  3776. }
  3777. }
  3778.  
  3779.  
  3780.  
  3781.  
  3782. void Group_7_Stack_and_Index_Register_Instructions(BYTE opcode)
  3783. {
  3784. switch (opcode)
  3785. {
  3786.  
  3787. case 0x35: // TXS Inher
  3788. StackPointer=IndexRegister-1;
  3789. break;
  3790.  
  3791. case 0x30: // TSX inher
  3792. StackPointer=IndexRegister+1;
  3793. break;
  3794.  
  3795. case 0x36: //PSHA inher
  3796. if((StackPointer >= 1) && (StackPointer < MEMORY_SIZE))
  3797. {
  3798. Memory[StackPointer] = Registers[REGISTER_A];
  3799. StackPointer--;
  3800. }
  3801. break;
  3802.  
  3803. case 0x37: //PSHB inher
  3804. if((StackPointer >= 1) && (StackPointer < MEMORY_SIZE))
  3805. {
  3806. Memory[StackPointer] = Registers[REGISTER_B];
  3807. StackPointer--;
  3808. }
  3809. break;
  3810.  
  3811. case 0x32: //PULA inher
  3812. if((StackPointer >= 0) && (StackPointer < MEMORY_SIZE-1))
  3813. {
  3814. StackPointer++;
  3815. Registers[REGISTER_A] = Memory[StackPointer];
  3816.  
  3817. }
  3818. break;
  3819.  
  3820. case 0x33: //PULB inher
  3821. if((StackPointer >= 0) && (StackPointer < MEMORY_SIZE-1))
  3822. {
  3823. StackPointer++;
  3824. Registers[REGISTER_B] = Memory[StackPointer];
  3825.  
  3826. }
  3827. break;
  3828.  
  3829. case 0x34: //DES
  3830. StackPointer--;
  3831. break;
  3832.  
  3833. case 0x31: //INS
  3834. StackPointer++;
  3835. break;
  3836.  
  3837. default:
  3838. break;
  3839. }
  3840. }
  3841.  
  3842.  
  3843. void Group_8_Interrupt_and_Subroutine_Instructions(BYTE opcode)
  3844. {
  3845. BYTE regA;
  3846. BYTE regB;
  3847. BYTE lb;
  3848. BYTE hb;
  3849. BYTE byte_address;
  3850. BYTE hi_prog, lo_prog, hi_index, lo_index;
  3851. WORD wdata;
  3852. WORD hi_address, lo_address;
  3853. WORD address;
  3854. WORD temp_word;
  3855. WORD offset;
  3856.  
  3857.  
  3858. switch(opcode)
  3859. {
  3860. case 0x3E: // WAI
  3861. halt = true;
  3862. break;
  3863.  
  3864. case 0x39: //RTS
  3865. if((StackPointer >= 0) && (StackPointer < (MEMORY_SIZE-2)))
  3866. {
  3867. StackPointer++;
  3868. hb = Memory[StackPointer];
  3869. StackPointer++;
  3870. lb = Memory[StackPointer];
  3871. ProgramCounter = ((WORD)hb << 8) + (WORD)lb;
  3872. }
  3873.  
  3874. break;
  3875.  
  3876. case 0x3B: //RTI Inher
  3877. address = IndexRegister + (WORD)fetch();
  3878.  
  3879.  
  3880. if (StackPointer > IndexRegister)
  3881. {
  3882. StackPointer++;
  3883. Flags = Memory[StackPointer];
  3884. StackPointer++;
  3885. Registers[REGISTER_B] = Memory[StackPointer];
  3886. StackPointer++;
  3887. Registers[REGISTER_A] = Memory[StackPointer];
  3888. StackPointer++;
  3889. hi_index = Memory[StackPointer];
  3890. StackPointer++;
  3891. lo_index = Memory[StackPointer];
  3892. StackPointer++;
  3893. hi_prog = Memory[StackPointer];
  3894. StackPointer++;
  3895. lo_prog = Memory[StackPointer];
  3896. StackPointer++;
  3897.  
  3898.  
  3899. }
  3900. ProgramCounter = (WORD) ((hi_prog << 8) + lo_prog);
  3901. IndexRegister = (WORD) ((hi_index << 8) + lo_index);
  3902. break;
  3903.  
  3904. case 0x3F: //SWI Inher
  3905. address = IndexRegister + (WORD)fetch();
  3906. hi_prog = (BYTE) ProgramCounter >> 8;
  3907. lo_prog = (BYTE) ProgramCounter;
  3908.  
  3909. hi_index = (BYTE) IndexRegister >> 8;
  3910. lo_index = (BYTE) IndexRegister;
  3911.  
  3912. if (StackPointer > IndexRegister)
  3913. {
  3914.  
  3915. Memory[StackPointer] = lo_prog;
  3916. StackPointer--;
  3917. Memory[StackPointer] = hi_prog;
  3918. StackPointer--;
  3919. Memory[StackPointer] = lo_index;
  3920. StackPointer--;
  3921. Memory[StackPointer] = hi_index;
  3922. StackPointer--;
  3923. Memory[StackPointer] = Registers[REGISTER_A];
  3924. StackPointer--;
  3925. Memory[StackPointer] = Registers[REGISTER_B];
  3926. StackPointer--;
  3927. Memory[StackPointer] = Flags;
  3928. StackPointer--;
  3929. }
  3930. break;
  3931.  
  3932. default:
  3933. break;
  3934. }
  3935. }
  3936.  
  3937.  
  3938.  
  3939.  
  3940.  
  3941.  
  3942.  
  3943. void execute(BYTE opcode)
  3944. {
  3945. BYTE high_nibble;
  3946. BYTE low_nibble;
  3947.  
  3948. high_nibble = (opcode >> 4) & 0xFF;
  3949. low_nibble = opcode & 0xFF;
  3950.  
  3951. if ((opcode & 0x80) == 0x80) // Group 1: Dual Operand Instructions
  3952. {
  3953. Group_1_Dual_Operand_Instructions(opcode);
  3954. }
  3955. else if ((opcode & 0xC0) == 0x40) // Group 2: Single Operand Instructions
  3956. {
  3957. Group_2_Single_Operand_Instructions(opcode);
  3958. }
  3959. else if ((opcode & 0xF8) == 0x00) // Group 3: TPA, TAP, NOP Instructions
  3960. {
  3961. Group_3_TPA_TAP_NOP_Instructions(opcode);
  3962. }
  3963. else if ((opcode & 0xF8) == 0x08) // Group 4: Condition Code Instructions
  3964. {
  3965. Group_4_Condition_Code_Instructions(opcode);
  3966. }
  3967. else if ((opcode & 0xF0) == 0x10) // Group 5: Accumulator Instructions
  3968. {
  3969. Group_5_Accumulator_Instructions(opcode);
  3970. }
  3971. else if ((opcode & 0xF0) == 0x20) // Group 6: Branch Instructions
  3972. {
  3973. Group_6_Branch_Instructions(opcode);
  3974. }
  3975. else if ((opcode & 0xF8) == 0x30) // Group 7: Stack and Index Register Instructions
  3976. {
  3977. Group_7_Stack_and_Index_Register_Instructions(opcode);
  3978. }
  3979. else if ((opcode & 0xF8) == 0x38) // Group 8: Interrupt and Subroutine Instructions
  3980. {
  3981. Group_8_Interrupt_and_Subroutine_Instructions(opcode);
  3982. }
  3983. else
  3984. {
  3985. printf("ERROR> Unrecognised Op-code %X\n", opcode);
  3986. }
  3987. }
  3988.  
  3989.  
  3990. void emulate_6800()
  3991. {
  3992. BYTE opcode;
  3993.  
  3994. ProgramCounter = 0;
  3995. halt = false;
  3996. memory_in_range = true;
  3997.  
  3998. printf(" A B IX SP\n");
  3999.  
  4000. while ((!halt) && (memory_in_range))
  4001. {
  4002. printf("%04X ", ProgramCounter); // Print current address
  4003.  
  4004. opcode = fetch();
  4005. execute(opcode);
  4006.  
  4007. printf("%s ", opcode_mneumonics[opcode]); // Print current opcode
  4008.  
  4009. printf("%02X ", Registers[REGISTER_A]); // Print Accumulator
  4010. printf("%02X ", Registers[REGISTER_B]); // Print Register B
  4011.  
  4012. printf("%04X ", IndexRegister); // Print Stack Pointer
  4013.  
  4014. printf("%04X ", StackPointer); // Print Stack Pointer
  4015.  
  4016. if ((Flags & FLAG_H) == FLAG_H) // Print Half Carry Flag
  4017. {
  4018. printf("H=1 ");
  4019. }
  4020. else
  4021. {
  4022. printf("H=0 ");
  4023. }
  4024.  
  4025. if ((Flags & FLAG_I) == FLAG_I) // Print Interrupt Flag
  4026. {
  4027. printf("I=1 ");
  4028. }
  4029. else
  4030. {
  4031. printf("I=0 ");
  4032. }
  4033.  
  4034. if ((Flags & FLAG_N) == FLAG_N) // Print Sign Flag
  4035. {
  4036. printf("N=1 ");
  4037. }
  4038. else
  4039. {
  4040. printf("N=0 ");
  4041. }
  4042.  
  4043. if ((Flags & FLAG_Z) == FLAG_Z) // Print Zero Flag
  4044. {
  4045. printf("Z=1 ");
  4046. }
  4047. else
  4048. {
  4049. printf("Z=0 ");
  4050. }
  4051.  
  4052. if ((Flags & FLAG_V) == FLAG_V) // Print Overflow Flag
  4053. {
  4054. printf("V=1 ");
  4055. }
  4056. else
  4057. {
  4058. printf("V=0 ");
  4059. }
  4060.  
  4061. if ((Flags & FLAG_C) == FLAG_C) // Print Carry Flag
  4062. {
  4063. printf("C=1 ");
  4064. }
  4065. else
  4066. {
  4067. printf("C=0 ");
  4068. }
  4069.  
  4070. printf("\n"); // New line
  4071. }
  4072.  
  4073. printf("\n"); // New line
  4074. }
  4075.  
  4076.  
  4077.  
  4078.  
  4079. ////////////////////////////////////////////////////////////////////////////////
  4080. // Intel 6800 Simulator/Emulator (End) //
  4081. ////////////////////////////////////////////////////////////////////////////////
  4082.  
  4083.  
  4084.  
  4085.  
  4086.  
  4087.  
  4088.  
  4089.  
  4090.  
  4091.  
  4092.  
  4093.  
  4094.  
  4095. void initialise_filenames()
  4096. {
  4097. int i;
  4098.  
  4099. for (i=0; i<MAX_FILENAME_SIZE; i++)
  4100. {
  4101. hex_file [i] = '\0';
  4102. trc_file [i] = '\0';
  4103. }
  4104. }
  4105.  
  4106.  
  4107.  
  4108.  
  4109. int find_dot_position(char *filename)
  4110. {
  4111. int dot_position;
  4112. int i;
  4113. char chr;
  4114.  
  4115. dot_position = 0;
  4116. i = 0;
  4117. chr = filename[i];
  4118.  
  4119. while (chr != '\0')
  4120. {
  4121. if (chr == '.')
  4122. {
  4123. dot_position = i;
  4124. }
  4125. i++;
  4126. chr = filename[i];
  4127. }
  4128.  
  4129. return (dot_position);
  4130. }
  4131.  
  4132.  
  4133. int find_end_position(char *filename)
  4134. {
  4135. int end_position;
  4136. int i;
  4137. char chr;
  4138.  
  4139. end_position = 0;
  4140. i = 0;
  4141. chr = filename[i];
  4142.  
  4143. while (chr != '\0')
  4144. {
  4145. end_position = i;
  4146. i++;
  4147. chr = filename[i];
  4148. }
  4149.  
  4150. return (end_position);
  4151. }
  4152.  
  4153.  
  4154. bool file_exists(char *filename)
  4155. {
  4156. bool exists;
  4157. FILE *ifp;
  4158.  
  4159. exists = false;
  4160.  
  4161. if ( ( ifp = fopen( filename, "r" ) ) != NULL )
  4162. {
  4163. exists = true;
  4164.  
  4165. fclose(ifp);
  4166. }
  4167.  
  4168. return (exists);
  4169. }
  4170.  
  4171.  
  4172.  
  4173. void create_file(char *filename)
  4174. {
  4175. FILE *ofp;
  4176.  
  4177. if ( ( ofp = fopen( filename, "w" ) ) != NULL )
  4178. {
  4179. fclose(ofp);
  4180. }
  4181. }
  4182.  
  4183.  
  4184.  
  4185. bool getline(FILE *fp, char *buffer)
  4186. {
  4187. bool rc;
  4188. bool collect;
  4189. char c;
  4190. int i;
  4191.  
  4192. rc = false;
  4193. collect = true;
  4194.  
  4195. i = 0;
  4196. while (collect)
  4197. {
  4198. c = getc(fp);
  4199.  
  4200. switch (c)
  4201. {
  4202. case EOF:
  4203. if (i > 0)
  4204. {
  4205. rc = true;
  4206. }
  4207. collect = false;
  4208. break;
  4209.  
  4210. case '\n':
  4211. if (i > 0)
  4212. {
  4213. rc = true;
  4214. collect = false;
  4215. buffer[i] = '\0';
  4216. }
  4217. break;
  4218.  
  4219. default:
  4220. buffer[i] = c;
  4221. i++;
  4222. break;
  4223. }
  4224. }
  4225.  
  4226. return (rc);
  4227. }
  4228.  
  4229.  
  4230.  
  4231.  
  4232.  
  4233. void load_and_run()
  4234. {
  4235. char chr;
  4236. int ln;
  4237. int dot_position;
  4238. int end_position;
  4239. long i;
  4240. FILE *ifp;
  4241. long address;
  4242. long load_at;
  4243. int code;
  4244.  
  4245. // Prompt for the .hex file
  4246.  
  4247. printf("\n");
  4248. printf("Enter the hex filename (.hex): ");
  4249.  
  4250. ln = 0;
  4251. chr = '\0';
  4252. while (chr != '\n')
  4253. {
  4254. chr = getchar();
  4255.  
  4256. switch(chr)
  4257. {
  4258. case '\n':
  4259. break;
  4260. default:
  4261. if (ln < MAX_FILENAME_SIZE)
  4262. {
  4263. hex_file [ln] = chr;
  4264. trc_file [ln] = chr;
  4265. ln++;
  4266. }
  4267. break;
  4268. }
  4269. }
  4270.  
  4271. // Tidy up the file names
  4272.  
  4273. dot_position = find_dot_position(hex_file);
  4274. if (dot_position == 0)
  4275. {
  4276. end_position = find_end_position(hex_file);
  4277.  
  4278. hex_file[end_position + 1] = '.';
  4279. hex_file[end_position + 2] = 'h';
  4280. hex_file[end_position + 3] = 'e';
  4281. hex_file[end_position + 4] = 'x';
  4282. hex_file[end_position + 5] = '\0';
  4283. }
  4284. else
  4285. {
  4286. hex_file[dot_position + 0] = '.';
  4287. hex_file[dot_position + 1] = 'h';
  4288. hex_file[dot_position + 2] = 'e';
  4289. hex_file[dot_position + 3] = 'x';
  4290. hex_file[dot_position + 4] = '\0';
  4291. }
  4292.  
  4293. dot_position = find_dot_position(trc_file);
  4294. if (dot_position == 0)
  4295. {
  4296. end_position = find_end_position(trc_file);
  4297.  
  4298. trc_file[end_position + 1] = '.';
  4299. trc_file[end_position + 2] = 't';
  4300. trc_file[end_position + 3] = 'r';
  4301. trc_file[end_position + 4] = 'c';
  4302. trc_file[end_position + 5] = '\0';
  4303. }
  4304. else
  4305. {
  4306. trc_file[dot_position + 0] = '.';
  4307. trc_file[dot_position + 1] = 't';
  4308. trc_file[dot_position + 2] = 'r';
  4309. trc_file[dot_position + 3] = 'c';
  4310. trc_file[dot_position + 4] = '\0';
  4311. }
  4312.  
  4313. if (file_exists(hex_file))
  4314. {
  4315. // Clear Registers and Memory
  4316.  
  4317. Flags = 0;
  4318. ProgramCounter = 0;
  4319. StackPointer = 0;
  4320. IndexRegister = 0;
  4321. for (i=0; i<2; i++)
  4322. {
  4323. Registers[i] = 0;
  4324. }
  4325. for (i=0; i<MEMORY_SIZE; i++)
  4326. {
  4327. Memory[i] = 0xFF;
  4328. }
  4329.  
  4330. // Load hex file
  4331.  
  4332. if ( ( ifp = fopen( hex_file, "r" ) ) != NULL )
  4333. {
  4334. printf("Loading file...\n\n");
  4335.  
  4336. load_at = 0;
  4337.  
  4338. while (getline(ifp, InputBuffer))
  4339. {
  4340. if (sscanf(InputBuffer, "L=%x", &address) == 1)
  4341. {
  4342. load_at = address;
  4343. }
  4344. else if (sscanf(InputBuffer, "%x", &code) == 1)
  4345. {
  4346. if ((load_at >= 0) && (load_at <= MEMORY_SIZE))
  4347. {
  4348. Memory[load_at] = (BYTE)code;
  4349. }
  4350. load_at++;
  4351. }
  4352. else
  4353. {
  4354. printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
  4355. }
  4356. }
  4357.  
  4358. fclose(ifp);
  4359. }
  4360.  
  4361. // Emulate the 6800
  4362.  
  4363. emulate_6800();
  4364. }
  4365. else
  4366. {
  4367. printf("\n");
  4368. printf("ERROR> Input file %s does not exist!\n", hex_file);
  4369. printf("\n");
  4370. }
  4371. }
  4372.  
  4373.  
  4374.  
  4375.  
  4376. void test_and_mark()
  4377. {
  4378. char buffer[1024];
  4379. bool testing_complete;
  4380. int len = sizeof(SOCKADDR);
  4381. char chr;
  4382. int i;
  4383. int j;
  4384. bool end_of_program;
  4385. long address;
  4386. long load_at;
  4387. int code;
  4388. int mark;
  4389.  
  4390. printf("\n");
  4391. printf("Automatic Testing and Marking\n");
  4392. printf("\n");
  4393.  
  4394. testing_complete = false;
  4395.  
  4396. sprintf(buffer, "Test Student %s", STUDENT_NUMBER);
  4397. sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
  4398.  
  4399. while (!testing_complete)
  4400. {
  4401. memset(buffer, '\0', sizeof(buffer));
  4402.  
  4403. if (recvfrom(sock, buffer, sizeof(buffer)-1, 0, (SOCKADDR *)&client_addr, &len) != SOCKET_ERROR)
  4404. {
  4405. printf("Incoming Data: %s \n", buffer);
  4406.  
  4407. //if (strcmp(buffer, "Testing complete") == 0)
  4408. if (sscanf(buffer, "Testing complete %d", &mark) == 1)
  4409. {
  4410. testing_complete = true;
  4411. printf("Current mark = %d\n", mark);
  4412. }
  4413. else if (strcmp(buffer, "Error") == 0)
  4414. {
  4415. printf("ERROR> Testing abnormally terminated\n");
  4416. testing_complete = true;
  4417. }
  4418. else
  4419. {
  4420. // Clear Registers and Memory
  4421.  
  4422. Flags = 0;
  4423. ProgramCounter = 0;
  4424. StackPointer = 0;
  4425. for (i=0; i<2; i++)
  4426. {
  4427. Registers[i] = 0;
  4428. }
  4429. for (i=0; i<MEMORY_SIZE; i++)
  4430. {
  4431. Memory[i] = 0;
  4432. }
  4433.  
  4434. // Load hex file
  4435.  
  4436. i = 0;
  4437. j = 0;
  4438. load_at = 0;
  4439. end_of_program = false;
  4440. while (!end_of_program)
  4441. {
  4442. chr = buffer[i];
  4443. switch (chr)
  4444. {
  4445. case '\0':
  4446. end_of_program = true;
  4447.  
  4448. case ',':
  4449. if (sscanf(InputBuffer, "L=%x", &address) == 1)
  4450. {
  4451. load_at = address;
  4452. }
  4453. else if (sscanf(InputBuffer, "%x", &code) == 1)
  4454. {
  4455. if ((load_at >= 0) && (load_at <= MEMORY_SIZE))
  4456. {
  4457. Memory[load_at] = (BYTE)code;
  4458. }
  4459. load_at++;
  4460. }
  4461. else
  4462. {
  4463. printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
  4464. }
  4465. j = 0;
  4466. break;
  4467.  
  4468. default:
  4469. InputBuffer[j] = chr;
  4470. j++;
  4471. break;
  4472. }
  4473. i++;
  4474. }
  4475.  
  4476. // Emulate the 6800
  4477.  
  4478. if (load_at > 1)
  4479. {
  4480. emulate_6800();
  4481.  
  4482. // Send results
  4483.  
  4484. sprintf(buffer, "%02X%02X %02X%02X %04X %04X %02X%02X %02X%02X", Registers[REGISTER_A], Registers[REGISTER_B], Flags, Memory[TEST_ADDRESS_1], IndexRegister, StackPointer, Memory[TEST_ADDRESS_2], Memory[TEST_ADDRESS_3], Memory[TEST_ADDRESS_4], Memory[TEST_ADDRESS_5]);
  4485. sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
  4486. }
  4487. }
  4488. }
  4489. }
  4490. }
  4491.  
  4492.  
  4493.  
  4494. int _tmain(int argc, _TCHAR* argv[])
  4495. {
  4496. char chr;
  4497. char dummy;
  4498.  
  4499. printf("\n");
  4500. printf("Intel 6800 Microprocessor Emulator\n");
  4501. printf("UWE Computer and Network Systems Assignment 1 (2014-15)\n");
  4502. printf("\n");
  4503.  
  4504. initialise_filenames();
  4505.  
  4506. if (WSAStartup(MAKEWORD(2, 2), &data) != 0) return(0);
  4507.  
  4508. sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); // Here we create our socket, which will be a UDP socket (SOCK_DGRAM).
  4509. if (!sock)
  4510. {
  4511. // Creation failed!
  4512. }
  4513.  
  4514. memset(&server_addr, 0, sizeof(SOCKADDR_IN));
  4515. server_addr.sin_family = AF_INET;
  4516. server_addr.sin_addr.s_addr = inet_addr(IP_ADDRESS_SERVER);
  4517. server_addr.sin_port = htons(PORT_SERVER);
  4518.  
  4519. memset(&client_addr, 0, sizeof(SOCKADDR_IN));
  4520. client_addr.sin_family = AF_INET;
  4521. client_addr.sin_addr.s_addr = inet_addr("127.0.0.1");
  4522. client_addr.sin_port = htons(PORT_CLIENT);
  4523.  
  4524. //int ret = bind(sock, (SOCKADDR *)&client_addr, sizeof(SOCKADDR));
  4525. //if (ret)
  4526. //{
  4527. // //printf("Bind failed! \n"); // Bind failed!
  4528. //}
  4529.  
  4530.  
  4531.  
  4532. chr = '\0';
  4533. while ((chr != 'e') && (chr != 'E'))
  4534. {
  4535. printf("\n");
  4536. printf("Please select option\n");
  4537. printf("L - Load and run a hex file\n");
  4538. printf("T - Have the server test and mark your emulator\n");
  4539. printf("E - Exit\n");
  4540. printf("Enter option: ");
  4541. chr = getchar();
  4542. if (chr != 0x0A)
  4543. {
  4544. dummy = getchar(); // read in the <CR>
  4545. }
  4546. printf("\n");
  4547.  
  4548. switch (chr)
  4549. {
  4550. case 'L':
  4551. case 'l':
  4552. load_and_run();
  4553. break;
  4554.  
  4555. case 'T':
  4556. case 't':
  4557. test_and_mark();
  4558. break;
  4559.  
  4560. default:
  4561. break;
  4562. }
  4563. }
  4564.  
  4565. closesocket(sock);
  4566. WSACleanup();
  4567.  
  4568.  
  4569. return 0;
  4570. }
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