API tools faq
paste
Advertisement
Guest User

CoreBoot_SunUltra40M2

a guest
Oct 31st, 2011
98
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 16.32 KB | None | 0 0
raw download clone embed print report
  1. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
  2. *sysinfo range: [000cf000,000cf730]
  3. bsp_apicid=00
  4. Enabling routing table for node 00 done.
  5. Enabling SMP settings
  6. (0,1) link=00
  7. (1,0) link=02
  8. setup_remote_node: done
  9. Renaming current temporary node to 01 done.
  10. Enabling routing table for node 01 done.
  11. 02 nodes initialized.
  12. coherent_ht_finalize
  13. done
  14. core0 started: 01
  15. started ap apicid: * AP 01started
  16. * AP 03started
  17.  
  18. SBLink=01
  19. NC node|link=01
  20. NC node|link=02
  21. busn=40
  22. entering optimize_link_incoherent_ht
  23. sysinfo->link_pair_num=0x2
  24. entering ht_optimize_link
  25. pos=0xaa, unfiltered freq_cap=0x8075
  26. pos=0xaa, filtered freq_cap=0x75
  27. pos=0x52, unfiltered freq_cap=0x7f
  28. pos=0x52, filtered freq_cap=0x7f
  29. freq_cap1=0x75, freq_cap2=0x7f
  30. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  31. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  32. width_cap1=0x11, width_cap2=0x11
  33. dev1 input ln_width1=0x4, ln_width2=0x4
  34. dev1 input width=0x1
  35. dev1 output ln_width1=0x4, ln_width2=0x4
  36. dev1 input|output width=0x11
  37. old dev1 input|output width=0x11
  38. dev2 input|output width=0x11
  39. old dev2 input|output width=0x11
  40. after ht_optimize_link for link pair 0, reset_needed=0x0
  41. entering ht_optimize_link
  42. pos=0xca, unfiltered freq_cap=0x8075
  43. pos=0xca, filtered freq_cap=0x75
  44. pos=0x52, unfiltered freq_cap=0x7f
  45. pos=0x52, filtered freq_cap=0x7f
  46. freq_cap1=0x75, freq_cap2=0x7f
  47. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  48. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  49. width_cap1=0x11, width_cap2=0x11
  50. dev1 input ln_width1=0x4, ln_width2=0x4
  51. dev1 input width=0x1
  52. dev1 output ln_width1=0x4, ln_width2=0x4
  53. dev1 input|output width=0x11
  54. old dev1 input|output width=0x11
  55. dev2 input|output width=0x11
  56. old dev2 input|output width=0x11
  57. after ht_optimize_link for link pair 1, reset_needed=0x0
  58. after optimize_link_read_pointers_chain, reset_needed=0x0
  59. mcp55_num:01
  60. ht reset -
  61.  
  62.  
  63. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
  64. *sysinfo range: [000cf000,000cf730]
  65. bsp_apicid=00
  66. Enabling routing table for node 00 done.
  67. Enabling SMP settings
  68. (0,1) link=00
  69. (1,0) link=02
  70. setup_remote_node: done
  71. Renaming current temporary node to 01 done.
  72. Enabling routing table for node 01 done.
  73. 02 nodes initialized.
  74. coherent_ht_finalize
  75. done
  76. core0 started: 01
  77. started ap apicid: * AP 01started
  78. * AP 03started
  79.  
  80. SBLink=01
  81. NC node|link=01
  82. NC node|link=02
  83. busn=40
  84. entering optimize_link_incoherent_ht
  85. sysinfo->link_pair_num=0x2
  86. entering ht_optimize_link
  87. pos=0xaa, unfiltered freq_cap=0x8075
  88. pos=0xaa, filtered freq_cap=0x75
  89. pos=0x52, unfiltered freq_cap=0x7f
  90. pos=0x52, filtered freq_cap=0x7f
  91. freq_cap1=0x75, freq_cap2=0x7f
  92. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  93. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  94. width_cap1=0x11, width_cap2=0x11
  95. dev1 input ln_width1=0x4, ln_width2=0x4
  96. dev1 input width=0x1
  97. dev1 output ln_width1=0x4, ln_width2=0x4
  98. dev1 input|output width=0x11
  99. old dev1 input|output width=0x11
  100. dev2 input|output width=0x11
  101. old dev2 input|output width=0x11
  102. after ht_optimize_link for link pair 0, reset_needed=0x0
  103. entering ht_optimize_link
  104. pos=0xca, unfiltered freq_cap=0x8075
  105. pos=0xca, filtered freq_cap=0x75
  106. pos=0x52, unfiltered freq_cap=0x7f
  107. pos=0x52, filtered freq_cap=0x7f
  108. freq_cap1=0x75, freq_cap2=0x7f
  109. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  110. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  111. width_cap1=0x11, width_cap2=0x11
  112. dev1 input ln_width1=0x4, ln_width2=0x4
  113. dev1 input width=0x1
  114. dev1 output ln_width1=0x4, ln_width2=0x4
  115. dev1 input|output width=0x11
  116. old dev1 input|output width=0x11
  117. dev2 input|output width=0x11
  118. old dev2 input|output width=0x11
  119. after ht_optimize_link for link pair 1, reset_needed=0x0
  120. after optimize_link_read_pointers_chain, reset_needed=0x0
  121. mcp55_num:01
  122. Ram1.00
  123. setting up CPU 00 northbridge registers
  124. done.
  125. Ram1.01
  126. setting up CPU 01 northbridge registers
  127. done.
  128. Ram2.00
  129. sdram_set_spd_registers: paramx :000cef28
  130. DIMM socket 0, channel 0 SPD device is 0x50
  131. DIMM socket 0, channel 1 SPD device is 0x51
  132. DIMM socket 1, channel 0 SPD device is 0x52
  133. DIMM socket 1, channel 1 SPD device is 0x53
  134. DIMM socket 2, channel 0 SPD device is 0x00
  135. DIMM socket 2, channel 1 SPD device is 0x00
  136. DIMM socket 3, channel 0 SPD device is 0x00
  137. DIMM socket 3, channel 1 SPD device is 0x00
  138. sdram_set_spd_registers: dimm_mask=0x22
  139. Common CAS latency bitfield: 0x38
  140. Enabling dual channel memory
  141. spd_enable_2channels: dimm_mask=0x22
  142. spd_set_ram_size: dimm_mask=0x22
  143. Registered
  144. spd_handle_unbuffered_dimms: dimm_mask=0x22
  145. 1 min_cycle_time: 00000250
  146. 1.1 dimm_mask: 00000022
  147. i: 00000000
  148. 1.1 dimm_mask: 00000022
  149. i: 00000001
  150. Channel 0 settings:
  151. latencies: 00000038
  152. index: 00000000
  153. latency: 00000003
  154. value1: 00000050
  155. value2: 00000500
  156. new_cycle_time: 00000500
  157. new_latency: 00000003
  158. index: 00000001
  159. latency: 00000004
  160. value1: 0000003d
  161. value2: 00000375
  162. new_cycle_time: 00000375
  163. new_latency: 00000004
  164. index: 00000002
  165. latency: 00000005
  166. value1: 00000030
  167. value2: 00000300
  168. new_cycle_time: 00000300
  169. new_latency: 00000005
  170. 2 min_cycle_time: 00000300
  171. 2 min_latency: 00000005
  172. Channel 1 settings:
  173. latencies: 00000038
  174. index: 00000000
  175. latency: 00000003
  176. value1: 00000050
  177. value2: 00000500
  178. new_cycle_time: 00000500
  179. new_latency: 00000003
  180. index: 00000001
  181. latency: 00000004
  182. value1: 0000003d
  183. value2: 00000375
  184. new_cycle_time: 00000375
  185. new_latency: 00000004
  186. index: 00000002
  187. latency: 00000005
  188. value1: 00000030
  189. value2: 00000300
  190. new_cycle_time: 00000300
  191. new_latency: 00000005
  192. 2 min_cycle_time: 00000300
  193. 2 min_latency: 00000005
  194. 1.1 dimm_mask: 00000022
  195. i: 00000002
  196. 1.1 dimm_mask: 00000022
  197. i: 00000003
  198. 3 min_cycle_time: 00000300
  199. 3 min_latency: 00000005
  200. 4 min_cycle_time: 00000300
  201. 333MHz
  202. 333MHz
  203. spd_set_memclk: dimm_mask=0x22
  204. spd_set_dram_timing dimm socket: 00000001
  205. trc
  206. update_dimm_Trc: tRC (41) = 0000003c
  207. update_dimm_Trc: tRC final value = 2400
  208. update_dimm_Trc: clocks = 20
  209. update_dimm_Trc: clocks after adjustment = 20
  210. trcd
  211. trrd
  212. tras
  213. update_dimm_Tras: 0 value= 0000002d
  214. update_dimm_Tras: 1 value= 00000708
  215. update_dimm_Tras: divisor= 00000078
  216. update_dimm_Tras: clocks= 0000000f
  217. trp
  218. trtp
  219. twr
  220. tref
  221. twtr
  222. trfc
  223. spd_set_dram_timing: dimm_mask=0x22
  224. Interleaved
  225. RAM end at 0x00400000 kB
  226. Adjusting lower RAM end
  227. Lower RAM end at 0x003f0000 kB
  228. Ram2.01
  229. sdram_set_spd_registers: paramx :000cef28
  230. DIMM socket 0, channel 0 SPD device is 0x54
  231. DIMM socket 0, channel 1 SPD device is 0x55
  232. DIMM socket 1, channel 0 SPD device is 0x56
  233. DIMM socket 1, channel 1 SPD device is 0x57
  234. DIMM socket 2, channel 0 SPD device is 0x00
  235. DIMM socket 2, channel 1 SPD device is 0x00
  236. DIMM socket 3, channel 0 SPD device is 0x00
  237. DIMM socket 3, channel 1 SPD device is 0x00
  238. sdram_set_spd_registers: dimm_mask=0x22
  239. Common CAS latency bitfield: 0x38
  240. Enabling dual channel memory
  241. spd_enable_2channels: dimm_mask=0x22
  242. spd_set_ram_size: dimm_mask=0x22
  243. Registered
  244. spd_handle_unbuffered_dimms: dimm_mask=0x22
  245. 1 min_cycle_time: 00000250
  246. 1.1 dimm_mask: 00000022
  247. i: 00000000
  248. 1.1 dimm_mask: 00000022
  249. i: 00000001
  250. Channel 0 settings:
  251. latencies: 00000038
  252. index: 00000000
  253. latency: 00000003
  254. value1: 00000050
  255. value2: 00000500
  256. new_cycle_time: 00000500
  257. new_latency: 00000003
  258. index: 00000001
  259. latency: 00000004
  260. value1: 0000003d
  261. value2: 00000375
  262. new_cycle_time: 00000375
  263. new_latency: 00000004
  264. index: 00000002
  265. latency: 00000005
  266. value1: 00000030
  267. value2: 00000300
  268. new_cycle_time: 00000300
  269. new_latency: 00000005
  270. 2 min_cycle_time: 00000300
  271. 2 min_latency: 00000005
  272. Channel 1 settings:
  273. latencies: 00000038
  274. index: 00000000
  275. latency: 00000003
  276. value1: 00000050
  277. value2: 00000500
  278. new_cycle_time: 00000500
  279. new_latency: 00000003
  280. index: 00000001
  281. latency: 00000004
  282. value1: 0000003d
  283. value2: 00000375
  284. new_cycle_time: 00000375
  285. new_latency: 00000004
  286. index: 00000002
  287. latency: 00000005
  288. value1: 00000030
  289. value2: 00000300
  290. new_cycle_time: 00000300
  291. new_latency: 00000005
  292. 2 min_cycle_time: 00000300
  293. 2 min_latency: 00000005
  294. 1.1 dimm_mask: 00000022
  295. i: 00000002
  296. 1.1 dimm_mask: 00000022
  297. i: 00000003
  298. 3 min_cycle_time: 00000300
  299. 3 min_latency: 00000005
  300. 4 min_cycle_time: 00000300
  301. 333MHz
  302. 333MHz
  303. spd_set_memclk: dimm_mask=0x22
  304. spd_set_dram_timing dimm socket: 00000001
  305. trc
  306. update_dimm_Trc: tRC (41) = 0000003c
  307. update_dimm_Trc: tRC final value = 2400
  308. update_dimm_Trc: clocks = 20
  309. update_dimm_Trc: clocks after adjustment = 20
  310. trcd
  311. trrd
  312. tras
  313. update_dimm_Tras: 0 value= 0000002d
  314. update_dimm_Tras: 1 value= 00000708
  315. update_dimm_Tras: divisor= 00000078
  316. update_dimm_Tras: clocks= 0000000f
  317. trp
  318. trtp
  319. twr
  320. tref
  321. twtr
  322. trfc
  323. spd_set_dram_timing: dimm_mask=0x22
  324. Interleaved
  325. RAM end at 0x00800000 kB
  326. Handling memory mapped above 4 GB
  327. Upper RAM end at 0x00800000 kB
  328. Correcting memory amount mapped below 4 GB
  329. Adjusting lower RAM end
  330. Lower RAM end at 0x003f0000 kB
  331. Ram3
  332. ECC enabled
  333. ECC enabled
  334. Initializing memory: done
  335. Initializing memory: done
  336. Handling memory hole at 0x00300000 (default)
  337. RAM end at 0x00900000 kB
  338. Handling memory mapped above 4 GB
  339. Upper RAM end at 0x00900000 kB
  340. Correcting memory amount mapped below 4 GB
  341. Adjusting lower RAM end
  342. Lower RAM end at 0x00300000 kB
  343. set DQS timing:RcvrEn:Pass1: 00
  344. ------Address debug: TrainRcvEn: buf_a:000ced20------
  345. done
  346. set DQS timing:DQSPos: 00
  347. TrainDQSRdWrPos: buf_a:000ce9a0
  348. TrainDQSPos: MutualCSPassW[48] :000ce878
  349. TrainDQSPos: MutualCSPassW[48] :000ce878
  350. TrainDQSPos: MutualCSPassW[48] :000ce878
  351. TrainDQSPos: MutualCSPassW[48] :000ce878
  352. TrainDQSPos: MutualCSPassW[48] :000ce878
  353. TrainDQSPos: MutualCSPassW[48] :000ce878
  354.  
  355.  
  356. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
  357. *sysinfo range: [000cf000,000cf730]
  358. bsp_apicid=00
  359. Enabling routing table for node 00 done.
  360. Enabling SMP settings
  361. (0,1) link=00
  362. (1,0) link=02
  363. setup_remote_node: done
  364. Renaming current temporary node to 01 done.
  365. Enabling routing table for node 01 done.
  366. 02 nodes initialized.
  367. coherent_ht_finalize
  368. done
  369. core0 started: 01
  370. started ap apicid: * AP 01started
  371. * AP 03started
  372.  
  373. SBLink=01
  374. NC node|link=01
  375. NC node|link=02
  376. busn=40
  377. entering optimize_link_incoherent_ht
  378. sysinfo->link_pair_num=0x2
  379. entering ht_optimize_link
  380. pos=0xaa, unfiltered freq_cap=0x8075
  381. pos=0xaa, filtered freq_cap=0x75
  382. pos=0x52, unfiltered freq_cap=0x7f
  383. pos=0x52, filtered freq_cap=0x7f
  384. freq_cap1=0x75, freq_cap2=0x7f
  385. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  386. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  387. width_cap1=0x11, width_cap2=0x11
  388. dev1 input ln_width1=0x4, ln_width2=0x4
  389. dev1 input width=0x1
  390. dev1 output ln_width1=0x
  391.  
  392. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
  393. *sysinfo range: [000cf000,000cf730]
  394. bsp_apicid=00
  395. Enabling routing table for node 00 done.
  396. Enabling SMP settings
  397. (0,1) link=00
  398. (1,0) link=02
  399. setup_remote_node: done
  400. Renaming current temporary node to 01 done.
  401. Enabling routing table for node 01 done.
  402. 02 nodes initialized.
  403. coherent_ht_finalize
  404. done
  405. core0 started: 01
  406. started ap apicid: * AP 01started
  407. * AP 03started
  408.  
  409. SBLink=01
  410. NC node|link=01
  411. NC node|link=02
  412. busn=40
  413. entering optimize_link_incoherent_ht
  414. sysinfo->link_pair_num=0x2
  415. entering ht_optimize_link
  416. pos=0xaa, unfiltered freq_cap=0x8075
  417. pos=0xaa, filtered freq_cap=0x75
  418. pos=0x52, unfiltered freq_cap=0x7f
  419. pos=0x52, filtered freq_cap=0x7f
  420. freq_cap1=0x75, freq_cap2=0x7f
  421. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  422. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  423. width_cap1=0x11, width_cap2=0x11
  424. dev1 input ln_width1=0x4, ln_width2=0x4
  425. dev1 input width=0x1
  426. dev1 output ln_width1=0x
  427.  
  428. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
  429. *sysinfo range: [000cf000,000cf730]
  430. bsp_apicid=00
  431. Enabling routing table for node 00 done.
  432. Enabling SMP settings
  433. (0,1) link=00
  434. (1,0) link=02
  435. setup_remote_node: done
  436. Renaming current temporary node to 01 done.
  437. Enabling routing table for node 01 done.
  438. 02 nodes initialized.
  439. coherent_ht_finalize
  440. done
  441. core0 started: 01
  442. started ap apicid: * AP 01started
  443. * AP 03started
  444.  
  445. SBLink=01
  446. NC node|link=01
  447. NC node|link=02
  448. busn=40
  449. entering optimize_link_incoherent_ht
  450. sysinfo->link_pair_num=0x2
  451. entering ht_optimize_link
  452. pos=0xaa, unfiltered freq_cap=0x8075
  453. pos=0xaa, filtered freq_cap=0x75
  454. pos=0x52, unfiltered freq_cap=0x7f
  455. pos=0x52, filtered freq_cap=0x7f
  456. freq_cap1=0x75, freq_cap2=0x7f
  457. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  458. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  459. width_cap1=0x11, width_cap2=0x11
  460. dev1 input ln_width1=0x4, ln_width2=0x4
  461. dev1 input width=0x1
  462. dev1 output ln_width1=0x
  463.  
  464. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
  465. *sysinfo range: [000cf000,000cf730]
  466. bsp_apicid=00
  467. Enabling routing table for node 00 done.
  468. Enabling SMP settings
  469. (0,1) link=00
  470. (1,0) link=02
  471. setup_remote_node: done
  472. Renaming current temporary node to 01 done.
  473. Enabling routing table for node 01 done.
  474. 02 nodes initialized.
  475. coherent_ht_finalize
  476. done
  477. core0 started: 01
  478. started ap apicid: * AP 01started
  479. * AP 03started
  480.  
  481. SBLink=01
  482. NC node|link=01
  483. NC node|link=02
  484. busn=40
  485. entering optimize_link_incoherent_ht
  486. sysinfo->link_pair_num=0x2
  487. entering ht_optimize_link
  488. pos=0xaa, unfiltered freq_cap=0x8075
  489. pos=0xaa, filtered freq_cap=0x75
  490. pos=0x52, unfiltered freq_cap=0x7f
  491. pos=0x52, filtered freq_cap=0x7f
  492. freq_cap1=0x75, freq_cap2=0x7f
  493. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  494. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  495. width_cap1=0x11, width_cap2=0x11
  496. dev1 input ln_width1=0x4, ln_width2=0x4
  497. dev1 input width=0x1
  498. dev1 output ln_width1=0x
  499.  
  500. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
  501. *sysinfo range: [000cf000,000cf730]
  502. bsp_apicid=00
  503. Enabling routing table for node 00 done.
  504. Enabling SMP settings
  505. (0,1) link=00
  506. (1,0) link=02
  507. setup_remote_node: done
  508. Renaming current temporary node to 01 done.
  509. Enabling routing table for node 01 done.
  510. 02 nodes initialized.
  511. coherent_ht_finalize
  512. done
  513. core0 started: 01
  514. started ap apicid: * AP 01started
  515. * AP 03started
  516.  
  517. SBLink=01
  518. NC node|link=01
  519. NC node|link=02
  520. busn=40
  521. entering optimize_link_incoherent_ht
  522. sysinfo->link_pair_num=0x2
  523. entering ht_optimize_link
  524. pos=0xaa, unfiltered freq_cap=0x8075
  525. pos=0xaa, filtered freq_cap=0x75
  526. pos=0x52, unfiltered freq_cap=0x7f
  527. pos=0x52, filtered freq_cap=0x7f
  528. freq_cap1=0x75, freq_cap2=0x7f
  529. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  530. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  531. width_cap1=0x11, width_cap2=0x11
  532. dev1 input ln_width1=0x4, ln_width2=0x4
  533. dev1 input width=0x1
  534. dev1 output ln_width1=0x
  535.  
  536. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
  537. *sysinfo range: [000cf000,000cf730]
  538. bsp_apicid=00
  539. Enabling routing table for node 00 done.
  540. Enabling SMP settings
  541. (0,1) link=00
  542. (1,0) link=02
  543. setup_remote_node: done
  544. Renaming current temporary node to 01 done.
  545. Enabling routing table for node 01 done.
  546. 02 nodes initialized.
  547. coherent_ht_finalize
  548. done
  549. core0 started: 01
  550. started ap apicid: * AP 01started
  551. * AP 03started
  552.  
  553. SBLink=01
  554. NC node|link=01
  555. NC node|link=02
  556. busn=40
  557. entering optimize_link_incoherent_ht
  558. sysinfo->link_pair_num=0x2
  559. entering ht_optimize_link
  560. pos=0xaa, unfiltered freq_cap=0x8075
  561. pos=0xaa, filtered freq_cap=0x75
  562. pos=0x52, unfiltered freq_cap=0x7f
  563. pos=0x52, filtered freq_cap=0x7f
  564. freq_cap1=0x75, freq_cap2=0x7f
  565. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  566. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  567. width_cap1=0x11, width_cap2=0x11
  568. dev1 input ln_width1=0x4, ln_width2=0x4
  569. dev1 input width=0x1
  570. dev1 output ln_width1=0x
  571.  
  572. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 14:40:19 PDT 2011 starting...
  573. *sysinfo range: [000cf000,000cf730]
  574. bsp_apicid=00
  575. Enabling routing table for node 00 done.
  576. Enabling SMP settings
  577. (0,1) link=00
  578. (1,0) link=02
  579. setup_remote_node: done
  580. Renaming current temporary node to 01 done.
  581. Enabling routing table for node 01 done.
  582. 02 nodes initialized.
  583. coherent_ht_finalize
  584. done
  585. core0 started: 01
  586. started ap apicid: * AP 01started
  587. * AP 03started
  588.  
  589. SBLink=01
  590. NC node|link=01
  591. NC node|link=02
  592. busn=40
  593. entering optimize_link_incoherent_ht
  594. sysinfo->link_pair_num=0x2
  595. entering ht_optimize_link
  596. pos=0xaa, unfiltered freq_cap=0x8075
  597. pos=0xaa, filtered freq_cap=0x75
  598. pos=0x52, unfiltered freq_cap=0x7f
  599. pos=0x52, filtered freq_cap=0x7f
  600. freq_cap1=0x75, freq_cap2=0x7f
  601. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  602. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  603. width_cap1=0x11, width_cap2=0x11
  604. dev1 input ln_width1=0x4, ln_width2=0x4
  605. dev1 input width=0x1
  606. dev1 output ln_width1=0x
  607.  
  608.  
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!