Starting program: /home/lekernel/FPGATools/antares/build/test-router/test-router /home/lekernel/FPGATools/6slx4.acg.gz SLICE_X0Y59 A SLICE_X0Y59 A1
Reading chip database...
...done.

Chip: xc6slx4tqg144-3
Grid: 45x73
Wires: 335639
Tile types: 162
Site types: 30

Start:
  Tile: CLEXM_X1Y61
  Site type: SLICEM
  Pin is an output connected to CLEXM_X1Y61:M_A
End:
  Tile: CLEXM_X1Y61
  Site type: SLICEM
  Pin is an input connected to CLEXM_X1Y61:M_A1

Routing CLEXM_X1Y61:M_A -> CLEXM_X1Y61:M_A1...
Routing succeeded in 4 iterations:
pip CLEXM_X1Y61 CLEXM_LOGICIN_B29CLEXM_LOGICIN_B29 -> M_A1
pip INT_X1Y61 LOGICOUT13 -> LOGICIN_B29
pip CLEXM_X1Y61 M_AMUX -> CLEXM_LOGICOUT13CLEXM_LOGICOUT13
pip CLEXM_X1Y61 M_A -> M_AMUX