Z80 - Click / LongPress detect with debounce and 20s activation timeout

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PORT        .EQU    0
RAMTOP      .EQU    32767
BITMASK_X0  .EQU    %00000001       ; X0 INPUT (0 = BUTTON PRESSED)
BITMASK_SYN .EQU    %10000000       ; 100 Hz SYNC INPUT
BITMASK_V1  .EQU    %00000001       ; OUTPUT V1 (1 = ON)
BITMASK_V2  .EQU    %00000010       ; OUTPUT V2 (1 = ON)

VARS        .EQU    300             ; START OF 7 BYTE STATIC VARS
_OUTVAL_    .EQU    VARS            ; COMMON OUTPUT VARIABLE
_X0_        .EQU    VARS+1          ; FILTERED INPUT
_SHIFT_     .EQU    VARS+2          ; DEBOUNCE SHIFT REGISTER
_TIME_      .EQU    VARS+3          ; 16 BIT TIME COUNTER
_PHASE_     .EQU    VARS+5          ; 16 BIT STATE ADDR

;---------------------------------------------------------------------

  .ORG 0

;---------------------------------------------------------------------

SETUP:
  DI                    ; NO INTERRUPT
  XOR  A                ; CLEAR A
  OUT  (PORT),A
  LD   SP,RAMTOP+1      ; STACK AT RAM END
  LD   (_OUTVAL_),A     ; INIT VARS
  LD   (_SHIFT_),A
  LD   (_X0_),A
  LD   HL,IDLE          ; INITIAL STATE
  LD   (_PHASE_),HL

MAINLOOP:
  CALL SYNC             ; 10 ms TIMING
  CALL READIN
  CALL MACHINE
  JP   MAINLOOP

;---------------------------------------------------------------------

SYNC:
  IN   A,(PORT)
  AND  BITMASK_SYN
  JP   NZ,SYNC          ; WAIT N-FRONT

J000:
  IN   A,(PORT)
  AND  BITMASK_SYN
  JP   Z,J000           ; WAIT P-FRONT
  RET

;---------------------------------------------------------------------

READIN:
  IN   A,(PORT)
  CPL                   ; POSITIVE LOGIC
  AND  BITMASK_X0       ; TEST INPUT BIT
  CALL BOOL             ; REDUCE TO 0/1
  CALL DEBOUNCE         ; 50 ms LOW PASS FILTER
  LD   (_X0_),A         ; STORE FILTERED INPUT
  RET

;---------------------------------------------------------------------

BOOL:
  AND  A                ; 0 ?
  RET  Z                ; YES, RETURN
  LD   A,1              ; NO, SET TO 1
  RET

;---------------------------------------------------------------------

DEBOUNCE:
  RRA
  LD   A,(_SHIFT_)
  RLA
  AND  %00111111
  LD   (_SHIFT_),A
  AND  A                ; ALL 0 ?
  RET  Z                ; YES, RETURN 0
  CP   %00111111        ; ALL 1 ?
  LD   A,1
  RET  Z                ; YES, RETURN 1
  LD   A,(_X0_)         ; NO, MAINTAIN
  RET

;---------------------------------------------------------------------

MACHINE:
  LD   HL,(_TIME_)
  INC  HL
  LD   (_TIME_),HL
  LD   IY,(_PHASE_)     ; LOAD ACTIVE STATE ADDR
  CALL J020
  LD   (_PHASE_),IY     ; STORE NEW STATE ADDR
  RET

J020:
  JP   (IY)             ; JUMP TO ACTIVE STATE


IDLE:
  LD   A,(_X0_)         ; READ INPUT _X0_
  AND  A                ; PRESSED ?
  RET  Z                ; NO, RETURN
  CALL RESTIME          ; RESET TIME FOR LONG PRESS DETECT
  LD   IY,S_1           ; PHASE S_1
  RET


S_1:
  LD   A,(_X0_)         ; READ INPUT _X0_
  AND  A                ; RELEASED ?
  JP   Z,S_1_1          ; YES, JUMP
  LD   DE,70
  CALL ELAPSED          ; ELAPSED 0,7 s ?
  RET  C                ; NO, RETURN
  CALL ONV2             ; LONG PRESS DETECT
  CALL RESTIME          ; RESET TIME FOR 20 s TIMEOUT
  LD   IY,S_2           ; PHASE S_2
  RET
S_1_1:
  CALL ONV1             ; CLICK DETECT
  CALL RESTIME          ; RESET TIME FOR 20 s TIMEOUT
  LD   IY,S_3           ; PHASE S_3
  RET


S_2:
  LD   A,(_X0_)         ; READ INPUT _X0_
  AND  A                ; RELEASED ?
  LD   IY,S_3
  RET  Z                ; YES, PHASE 3
  LD   IY,(_PHASE_)
  LD   DE,2000
  CALL ELAPSED          ; ELAPSED 20 s ?
  RET  C                ; NO, RETURN SAME PHASE
  CALL OFF              ; YES, OFF
  LD   IY,S_4           ; PHASE 4
  RET


S_3:
  LD   A,(_X0_)
  AND  A                ; PRESSED ?
  JP   NZ,S_3_1         ; YES, JUMP
  LD   DE,2000
  CALL ELAPSED          ; ELAPSED 20 s ?
  RET  C                ; NO, RETURN
S_3_1:
  CALL OFF              ; PRESS OR TIMEOUT DETECT
  LD   IY,S_4
  RET


S_4:
  LD   A,(_X0_)         ; READ INPUT _X0_
  AND  A                ; RELEASED ?
  RET  NZ               ; NO, RETURN
  LD   IY,IDLE          ; YES, IDLE PHASE
  RET

;---------------------------------------------------------------------

ELAPSED:
  LD   HL,(_TIME_)      ; LOAD TIME
  AND  A                ; CLEAR CARRY
  SBC  HL,DE            ; Cf SET IF NO ELAPSED
  RET

;---------------------------------------------------------------------

RESTIME:
  LD   HL,0
  LD   (_TIME_),HL      ; CLEAR TIME COUNTER
  RET

;---------------------------------------------------------------------

ONV1:
  LD   A,(_OUTVAL_)
  OR   BITMASK_V1       ; SET V1 BIT
  JP   J050

ONV2:
  LD   A,(_OUTVAL_)
  OR   BITMASK_V2       ; SET V2 BIT
  JP   J050

OFF:
  LD   A,BITMASK_V1
  OR   BITMASK_V2
  CPL
  LD   E,A
  LD   A,(_OUTVAL_)
  AND  E                ; RESET ONLY V1 AND V2 BITS

J050:
  LD   (_OUTVAL_),A     ; COMMON OUTPUT UPDATE
  OUT  (PORT),A         ; OUTPUT UPDATE
  RET

;---------------------------------------------------------------------

  .END

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