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1536MHz with Pine64

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Mar 1st, 2016
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  1. /dts-v1/;
  2.  
  3. /memreserve/ 0x0000000045000000 0x0000000000200000;
  4. /memreserve/ 0x0000000041010000 0x0000000000010000;
  5. /memreserve/ 0x0000000041020000 0x0000000000000800;
  6. /memreserve/ 0x0000000040100000 0x0000000000004000;
  7. /memreserve/ 0x0000000040104000 0x0000000000001000;
  8. /memreserve/ 0x0000000040105000 0x0000000000001000;
  9. / {
  10. model = "sun50iw1p1";
  11. compatible = "arm,sun50iw1p1", "arm,sun50iw1p1";
  12. interrupt-parent = <0x1>;
  13. #address-cells = <0x2>;
  14. #size-cells = <0x2>;
  15.  
  16. clocks {
  17. compatible = "allwinner,sunxi-clk-init";
  18. device_type = "clocks";
  19. #address-cells = <0x2>;
  20. #size-cells = <0x2>;
  21. ranges;
  22. reg = <0x0 0x1c20000 0x0 0x320 0x0 0x1f01400 0x0 0xb0 0x0 0x1f00060 0x0 0x4>;
  23.  
  24. losc {
  25. #clock-cells = <0x0>;
  26. compatible = "allwinner,fixed-clock";
  27. clock-frequency = <0x8000>;
  28. clock-output-names = "losc";
  29. linux,phandle = <0xc>;
  30. phandle = <0xc>;
  31. };
  32.  
  33. iosc {
  34. #clock-cells = <0x0>;
  35. compatible = "allwinner,fixed-clock";
  36. clock-frequency = <0xf42400>;
  37. clock-output-names = "iosc";
  38. linux,phandle = <0xd>;
  39. phandle = <0xd>;
  40. };
  41.  
  42. hosc {
  43. #clock-cells = <0x0>;
  44. compatible = "allwinner,fixed-clock";
  45. clock-frequency = <0x16e3600>;
  46. clock-output-names = "hosc";
  47. linux,phandle = <0x6>;
  48. phandle = <0x6>;
  49. };
  50.  
  51. pll_cpu {
  52. #clock-cells = <0x0>;
  53. compatible = "allwinner,sunxi-pll-clock";
  54. lock-mode = "new";
  55. clock-output-names = "pll_cpu";
  56. };
  57.  
  58. pll_audio {
  59. #clock-cells = <0x0>;
  60. compatible = "allwinner,sunxi-pll-clock";
  61. lock-mode = "new";
  62. assigned-clock-rates = <0x1770000>;
  63. clock-output-names = "pll_audio";
  64. linux,phandle = <0x2>;
  65. phandle = <0x2>;
  66. };
  67.  
  68. pll_video0 {
  69. #clock-cells = <0x0>;
  70. compatible = "allwinner,sunxi-pll-clock";
  71. lock-mode = "new";
  72. assigned-clock-rates = <0x11b3dc40>;
  73. clock-output-names = "pll_video0";
  74. linux,phandle = <0x3>;
  75. phandle = <0x3>;
  76. };
  77.  
  78. pll_ve {
  79. #clock-cells = <0x0>;
  80. compatible = "allwinner,sunxi-pll-clock";
  81. lock-mode = "new";
  82. clock-output-names = "pll_ve";
  83. linux,phandle = <0x16>;
  84. phandle = <0x16>;
  85. };
  86.  
  87. pll_ddr0 {
  88. #clock-cells = <0x0>;
  89. compatible = "allwinner,sunxi-pll-clock";
  90. lock-mode = "new";
  91. clock-output-names = "pll_ddr0";
  92. linux,phandle = <0x93>;
  93. phandle = <0x93>;
  94. };
  95.  
  96. pll_periph0 {
  97. #clock-cells = <0x0>;
  98. compatible = "allwinner,sunxi-pll-clock";
  99. lock-mode = "new";
  100. clock-output-names = "pll_periph0";
  101. linux,phandle = <0x4>;
  102. phandle = <0x4>;
  103. };
  104.  
  105. pll_periph1 {
  106. #clock-cells = <0x0>;
  107. compatible = "allwinner,sunxi-pll-clock";
  108. lock-mode = "new";
  109. clock-output-names = "pll_periph1";
  110. linux,phandle = <0x5>;
  111. phandle = <0x5>;
  112. };
  113.  
  114. pll_video1 {
  115. #clock-cells = <0x0>;
  116. compatible = "allwinner,sunxi-pll-clock";
  117. lock-mode = "new";
  118. assigned-clock-rates = <0x11b3dc40>;
  119. clock-output-names = "pll_video1";
  120. };
  121.  
  122. pll_gpu {
  123. #clock-cells = <0x0>;
  124. compatible = "allwinner,sunxi-pll-clock";
  125. lock-mode = "new";
  126. clock-output-names = "pll_gpu";
  127. linux,phandle = <0x96>;
  128. phandle = <0x96>;
  129. };
  130.  
  131. pll_mipi {
  132. #clock-cells = <0x0>;
  133. compatible = "allwinner,sunxi-pll-clock";
  134. lock-mode = "new";
  135. clock-output-names = "pll_mipi";
  136. linux,phandle = <0x8>;
  137. phandle = <0x8>;
  138. };
  139.  
  140. pll_hsic {
  141. #clock-cells = <0x0>;
  142. compatible = "allwinner,sunxi-pll-clock";
  143. lock-mode = "new";
  144. clock-output-names = "pll_hsic";
  145. linux,phandle = <0x3a>;
  146. phandle = <0x3a>;
  147. };
  148.  
  149. pll_de {
  150. #clock-cells = <0x0>;
  151. compatible = "allwinner,sunxi-pll-clock";
  152. lock-mode = "new";
  153. assigned-clock-rates = <0x11b3dc40>;
  154. clock-output-names = "pll_de";
  155. linux,phandle = <0x7>;
  156. phandle = <0x7>;
  157. };
  158.  
  159. pll_ddr1 {
  160. #clock-cells = <0x0>;
  161. compatible = "allwinner,sunxi-pll-clock";
  162. lock-mode = "new";
  163. clock-output-names = "pll_ddr1";
  164. linux,phandle = <0x94>;
  165. phandle = <0x94>;
  166. };
  167.  
  168. pll_audiox8 {
  169. #clock-cells = <0x0>;
  170. compatible = "allwinner,fixed-factor-clock";
  171. clocks = <0x2>;
  172. clock-mult = <0x8>;
  173. clock-div = <0x1>;
  174. clock-output-names = "pll_audiox8";
  175. };
  176.  
  177. pll_audiox4 {
  178. #clock-cells = <0x0>;
  179. compatible = "allwinner,fixed-factor-clock";
  180. clocks = <0x2>;
  181. clock-mult = <0x8>;
  182. clock-div = <0x2>;
  183. clock-output-names = "pll_audiox4";
  184. linux,phandle = <0x3c>;
  185. phandle = <0x3c>;
  186. };
  187.  
  188. pll_audiox2 {
  189. #clock-cells = <0x0>;
  190. compatible = "allwinner,fixed-factor-clock";
  191. clocks = <0x2>;
  192. clock-mult = <0x8>;
  193. clock-div = <0x4>;
  194. clock-output-names = "pll_audiox2";
  195. };
  196.  
  197. pll_video0x2 {
  198. #clock-cells = <0x0>;
  199. compatible = "allwinner,fixed-factor-clock";
  200. clocks = <0x3>;
  201. clock-mult = <0x2>;
  202. clock-div = <0x1>;
  203. clock-output-names = "pll_video0x2";
  204. };
  205.  
  206. pll_periph0x2 {
  207. #clock-cells = <0x0>;
  208. compatible = "allwinner,fixed-factor-clock";
  209. clocks = <0x4>;
  210. clock-mult = <0x2>;
  211. clock-div = <0x1>;
  212. clock-output-names = "pll_periph0x2";
  213. linux,phandle = <0x7b>;
  214. phandle = <0x7b>;
  215. };
  216.  
  217. pll_periph1x2 {
  218. #clock-cells = <0x0>;
  219. compatible = "allwinner,fixed-factor-clock";
  220. clocks = <0x5>;
  221. clock-mult = <0x2>;
  222. clock-div = <0x1>;
  223. clock-output-names = "pll_periph1x2";
  224. linux,phandle = <0x5a>;
  225. phandle = <0x5a>;
  226. };
  227.  
  228. pll_periph0d2 {
  229. #clock-cells = <0x0>;
  230. compatible = "allwinner,fixed-factor-clock";
  231. clocks = <0x4>;
  232. clock-mult = <0x1>;
  233. clock-div = <0x2>;
  234. clock-output-names = "pll_periph0d2";
  235. };
  236.  
  237. hoscd2 {
  238. #clock-cells = <0x0>;
  239. compatible = "allwinner,fixed-factor-clock";
  240. clocks = <0x6>;
  241. clock-mult = <0x1>;
  242. clock-div = <0x2>;
  243. clock-output-names = "hoscd2";
  244. };
  245.  
  246. cpu {
  247. #clock-cells = <0x0>;
  248. compatible = "allwinner,sunxi-periph-clock";
  249. clock-output-names = "cpu";
  250. };
  251.  
  252. cpuapb {
  253. #clock-cells = <0x0>;
  254. compatible = "allwinner,sunxi-periph-clock";
  255. clock-output-names = "cpuapb";
  256. };
  257.  
  258. axi {
  259. #clock-cells = <0x0>;
  260. compatible = "allwinner,sunxi-periph-clock";
  261. clock-output-names = "axi";
  262. };
  263.  
  264. pll_periphahb0 {
  265. #clock-cells = <0x0>;
  266. compatible = "allwinner,sunxi-periph-clock";
  267. clock-output-names = "pll_periphahb0";
  268. };
  269.  
  270. ahb1 {
  271. #clock-cells = <0x0>;
  272. compatible = "allwinner,sunxi-periph-clock";
  273. clock-output-names = "ahb1";
  274. linux,phandle = <0x95>;
  275. phandle = <0x95>;
  276. };
  277.  
  278. apb1 {
  279. #clock-cells = <0x0>;
  280. compatible = "allwinner,sunxi-periph-clock";
  281. clock-output-names = "apb1";
  282. };
  283.  
  284. apb2 {
  285. #clock-cells = <0x0>;
  286. compatible = "allwinner,sunxi-periph-clock";
  287. clock-output-names = "apb2";
  288. linux,phandle = <0x7e>;
  289. phandle = <0x7e>;
  290. };
  291.  
  292. ahb2 {
  293. #clock-cells = <0x0>;
  294. compatible = "allwinner,sunxi-periph-clock";
  295. clock-output-names = "ahb2";
  296. };
  297.  
  298. ths {
  299. #clock-cells = <0x0>;
  300. compatible = "allwinner,sunxi-periph-clock";
  301. clock-output-names = "ths";
  302. linux,phandle = <0x84>;
  303. phandle = <0x84>;
  304. };
  305.  
  306. nand {
  307. #clock-cells = <0x0>;
  308. compatible = "allwinner,sunxi-periph-clock";
  309. clock-output-names = "nand";
  310. linux,phandle = <0x80>;
  311. phandle = <0x80>;
  312. };
  313.  
  314. sdmmc0_mod {
  315. #clock-cells = <0x0>;
  316. compatible = "allwinner,sunxi-periph-clock";
  317. clock-output-names = "sdmmc0_mod";
  318. linux,phandle = <0x60>;
  319. phandle = <0x60>;
  320. };
  321.  
  322. sdmmc0_bus {
  323. #clock-cells = <0x0>;
  324. compatible = "allwinner,sunxi-periph-clock";
  325. clock-output-names = "sdmmc0_bus";
  326. linux,phandle = <0x61>;
  327. phandle = <0x61>;
  328. };
  329.  
  330. sdmmc0_rst {
  331. #clock-cells = <0x0>;
  332. compatible = "allwinner,sunxi-periph-clock";
  333. clock-output-names = "sdmmc0_rst";
  334. linux,phandle = <0x62>;
  335. phandle = <0x62>;
  336. };
  337.  
  338. sdmmc1_mod {
  339. #clock-cells = <0x0>;
  340. compatible = "allwinner,sunxi-periph-clock";
  341. clock-output-names = "sdmmc1_mod";
  342. linux,phandle = <0x65>;
  343. phandle = <0x65>;
  344. };
  345.  
  346. sdmmc1_bus {
  347. #clock-cells = <0x0>;
  348. compatible = "allwinner,sunxi-periph-clock";
  349. clock-output-names = "sdmmc1_bus";
  350. linux,phandle = <0x66>;
  351. phandle = <0x66>;
  352. };
  353.  
  354. sdmmc1_rst {
  355. #clock-cells = <0x0>;
  356. compatible = "allwinner,sunxi-periph-clock";
  357. clock-output-names = "sdmmc1_rst";
  358. linux,phandle = <0x67>;
  359. phandle = <0x67>;
  360. };
  361.  
  362. sdmmc2_mod {
  363. #clock-cells = <0x0>;
  364. compatible = "allwinner,sunxi-periph-clock";
  365. clock-output-names = "sdmmc2_mod";
  366. linux,phandle = <0x5b>;
  367. phandle = <0x5b>;
  368. };
  369.  
  370. sdmmc2_bus {
  371. #clock-cells = <0x0>;
  372. compatible = "allwinner,sunxi-periph-clock";
  373. clock-output-names = "sdmmc2_bus";
  374. linux,phandle = <0x5c>;
  375. phandle = <0x5c>;
  376. };
  377.  
  378. sdmmc2_rst {
  379. #clock-cells = <0x0>;
  380. compatible = "allwinner,sunxi-periph-clock";
  381. clock-output-names = "sdmmc2_rst";
  382. linux,phandle = <0x5d>;
  383. phandle = <0x5d>;
  384. };
  385.  
  386. ts {
  387. #clock-cells = <0x0>;
  388. compatible = "allwinner,sunxi-periph-clock";
  389. clock-output-names = "ts";
  390. };
  391.  
  392. ce {
  393. #clock-cells = <0x0>;
  394. compatible = "allwinner,sunxi-periph-clock";
  395. clock-output-names = "ce";
  396. linux,phandle = <0x7a>;
  397. phandle = <0x7a>;
  398. };
  399.  
  400. spi0 {
  401. #clock-cells = <0x0>;
  402. compatible = "allwinner,sunxi-periph-clock";
  403. clock-output-names = "spi0";
  404. linux,phandle = <0x52>;
  405. phandle = <0x52>;
  406. };
  407.  
  408. spi1 {
  409. #clock-cells = <0x0>;
  410. compatible = "allwinner,sunxi-periph-clock";
  411. clock-output-names = "spi1";
  412. linux,phandle = <0x56>;
  413. phandle = <0x56>;
  414. };
  415.  
  416. i2s0 {
  417. #clock-cells = <0x0>;
  418. compatible = "allwinner,sunxi-periph-clock";
  419. clock-output-names = "i2s0";
  420. linux,phandle = <0x42>;
  421. phandle = <0x42>;
  422. };
  423.  
  424. i2s1 {
  425. #clock-cells = <0x0>;
  426. compatible = "allwinner,sunxi-periph-clock";
  427. clock-output-names = "i2s1";
  428. linux,phandle = <0x47>;
  429. phandle = <0x47>;
  430. };
  431.  
  432. i2s2 {
  433. #clock-cells = <0x0>;
  434. compatible = "allwinner,sunxi-periph-clock";
  435. clock-output-names = "i2s2";
  436. linux,phandle = <0x48>;
  437. phandle = <0x48>;
  438. };
  439.  
  440. spdif {
  441. #clock-cells = <0x0>;
  442. compatible = "allwinner,sunxi-periph-clock";
  443. clock-output-names = "spdif";
  444. linux,phandle = <0x49>;
  445. phandle = <0x49>;
  446. };
  447.  
  448. usbphy0 {
  449. #clock-cells = <0x0>;
  450. compatible = "allwinner,sunxi-periph-clock";
  451. clock-output-names = "usbphy0";
  452. linux,phandle = <0x32>;
  453. phandle = <0x32>;
  454. };
  455.  
  456. usbphy1 {
  457. #clock-cells = <0x0>;
  458. compatible = "allwinner,sunxi-periph-clock";
  459. clock-output-names = "usbphy1";
  460. linux,phandle = <0x36>;
  461. phandle = <0x36>;
  462. };
  463.  
  464. usbhsic {
  465. #clock-cells = <0x0>;
  466. compatible = "allwinner,sunxi-periph-clock";
  467. clock-output-names = "usbhsic";
  468. linux,phandle = <0x38>;
  469. phandle = <0x38>;
  470. };
  471.  
  472. usbhsic12m {
  473. #clock-cells = <0x0>;
  474. compatible = "allwinner,sunxi-periph-clock";
  475. clock-output-names = "usbhsic12m";
  476. linux,phandle = <0x39>;
  477. phandle = <0x39>;
  478. };
  479.  
  480. usbohci1 {
  481. #clock-cells = <0x0>;
  482. compatible = "allwinner,sunxi-periph-clock";
  483. clock-output-names = "usbohci1";
  484. linux,phandle = <0x3b>;
  485. phandle = <0x3b>;
  486. };
  487.  
  488. usbohci0 {
  489. #clock-cells = <0x0>;
  490. compatible = "allwinner,sunxi-periph-clock";
  491. clock-output-names = "usbohci0";
  492. linux,phandle = <0x35>;
  493. phandle = <0x35>;
  494. };
  495.  
  496. de {
  497. #clock-cells = <0x0>;
  498. compatible = "allwinner,sunxi-periph-clock";
  499. assigned-clock-parents = <0x7>;
  500. assigned-clock-rates = <0x11b3dc40>;
  501. clock-output-names = "de";
  502. linux,phandle = <0x6a>;
  503. phandle = <0x6a>;
  504. };
  505.  
  506. tcon0 {
  507. #clock-cells = <0x0>;
  508. compatible = "allwinner,sunxi-periph-clock";
  509. assigned-clock-parents = <0x8>;
  510. clock-output-names = "tcon0";
  511. linux,phandle = <0x6b>;
  512. phandle = <0x6b>;
  513. };
  514.  
  515. tcon1 {
  516. #clock-cells = <0x0>;
  517. compatible = "allwinner,sunxi-periph-clock";
  518. assigned-clock-parents = <0x3>;
  519. clock-output-names = "tcon1";
  520. linux,phandle = <0x6e>;
  521. phandle = <0x6e>;
  522. };
  523.  
  524. deinterlace {
  525. #clock-cells = <0x0>;
  526. compatible = "allwinner,sunxi-periph-clock";
  527. clock-output-names = "deinterlace";
  528. linux,phandle = <0x7c>;
  529. phandle = <0x7c>;
  530. };
  531.  
  532. csi_s {
  533. #clock-cells = <0x0>;
  534. compatible = "allwinner,sunxi-periph-clock";
  535. clock-output-names = "csi_s";
  536. linux,phandle = <0x73>;
  537. phandle = <0x73>;
  538. };
  539.  
  540. csi_m {
  541. #clock-cells = <0x0>;
  542. compatible = "allwinner,sunxi-periph-clock";
  543. clock-output-names = "csi_m";
  544. linux,phandle = <0x74>;
  545. phandle = <0x74>;
  546. };
  547.  
  548. csi_misc {
  549. #clock-cells = <0x0>;
  550. compatible = "allwinner,sunxi-periph-clock";
  551. clock-output-names = "csi_misc";
  552. linux,phandle = <0x75>;
  553. phandle = <0x75>;
  554. };
  555.  
  556. ve {
  557. #clock-cells = <0x0>;
  558. compatible = "allwinner,sunxi-periph-clock";
  559. clock-output-names = "ve";
  560. linux,phandle = <0x17>;
  561. phandle = <0x17>;
  562. };
  563.  
  564. adda {
  565. #clock-cells = <0x0>;
  566. compatible = "allwinner,sunxi-periph-clock";
  567. clock-output-names = "adda";
  568. linux,phandle = <0x41>;
  569. phandle = <0x41>;
  570. };
  571.  
  572. addax4 {
  573. #clock-cells = <0x0>;
  574. compatible = "allwinner,sunxi-periph-clock";
  575. clock-output-names = "addax4";
  576. };
  577.  
  578. avs {
  579. #clock-cells = <0x0>;
  580. compatible = "allwinner,sunxi-periph-clock";
  581. clock-output-names = "avs";
  582. };
  583.  
  584. hdmi {
  585. #clock-cells = <0x0>;
  586. compatible = "allwinner,sunxi-periph-clock";
  587. assigned-clock-parents = <0x3>;
  588. clock-output-names = "hdmi";
  589. linux,phandle = <0x6f>;
  590. phandle = <0x6f>;
  591. };
  592.  
  593. hdmi_slow {
  594. #clock-cells = <0x0>;
  595. compatible = "allwinner,sunxi-periph-clock";
  596. clock-output-names = "hdmi_slow";
  597. linux,phandle = <0x70>;
  598. phandle = <0x70>;
  599. };
  600.  
  601. mbus {
  602. #clock-cells = <0x0>;
  603. compatible = "allwinner,sunxi-periph-clock";
  604. clock-output-names = "mbus";
  605. };
  606.  
  607. mipidsi {
  608. #clock-cells = <0x0>;
  609. compatible = "allwinner,sunxi-periph-clock";
  610. clock-output-names = "mipidsi";
  611. linux,phandle = <0x6d>;
  612. phandle = <0x6d>;
  613. };
  614.  
  615. gpu {
  616. #clock-cells = <0x0>;
  617. compatible = "allwinner,sunxi-periph-clock";
  618. clock-output-names = "gpu";
  619. linux,phandle = <0x97>;
  620. phandle = <0x97>;
  621. };
  622.  
  623. usbehci_16 {
  624. #clock-cells = <0x0>;
  625. compatible = "allwinner,sunxi-periph-clock";
  626. clock-output-names = "usbohci_16";
  627. };
  628.  
  629. usbehci1 {
  630. #clock-cells = <0x0>;
  631. compatible = "allwinner,sunxi-periph-clock";
  632. clock-output-names = "usbehci1";
  633. linux,phandle = <0x37>;
  634. phandle = <0x37>;
  635. };
  636.  
  637. usbehci0 {
  638. #clock-cells = <0x0>;
  639. compatible = "allwinner,sunxi-periph-clock";
  640. clock-output-names = "usbehci0";
  641. linux,phandle = <0x34>;
  642. phandle = <0x34>;
  643. };
  644.  
  645. usbotg {
  646. #clock-cells = <0x0>;
  647. compatible = "allwinner,sunxi-periph-clock";
  648. clock-output-names = "usbotg";
  649. linux,phandle = <0x33>;
  650. phandle = <0x33>;
  651. };
  652.  
  653. gmac {
  654. #clock-cells = <0x0>;
  655. compatible = "allwinner,sunxi-periph-clock";
  656. clock-output-names = "gmac";
  657. linux,phandle = <0x8f>;
  658. phandle = <0x8f>;
  659. };
  660.  
  661. sdram {
  662. #clock-cells = <0x0>;
  663. compatible = "allwinner,sunxi-periph-clock";
  664. clock-output-names = "sdram";
  665. };
  666.  
  667. dma {
  668. #clock-cells = <0x0>;
  669. compatible = "allwinner,sunxi-periph-clock";
  670. clock-output-names = "dma";
  671. linux,phandle = <0xb>;
  672. phandle = <0xb>;
  673. };
  674.  
  675. hwspinlock_rst {
  676. #clock-cells = <0x0>;
  677. compatible = "allwinner,sunxi-periph-clock";
  678. clock-output-names = "hwspinlock_rst";
  679. linux,phandle = <0xf>;
  680. phandle = <0xf>;
  681. };
  682.  
  683. hwspinlock_bus {
  684. #clock-cells = <0x0>;
  685. compatible = "allwinner,sunxi-periph-clock";
  686. clock-output-names = "hwspinlock_bus";
  687. linux,phandle = <0x10>;
  688. phandle = <0x10>;
  689. };
  690.  
  691. msgbox {
  692. #clock-cells = <0x0>;
  693. compatible = "allwinner,sunxi-periph-clock";
  694. clock-output-names = "msgbox";
  695. linux,phandle = <0xe>;
  696. phandle = <0xe>;
  697. };
  698.  
  699. lvds {
  700. #clock-cells = <0x0>;
  701. compatible = "allwinner,sunxi-periph-clock";
  702. clock-output-names = "lvds";
  703. linux,phandle = <0x6c>;
  704. phandle = <0x6c>;
  705. };
  706.  
  707. uart0 {
  708. #clock-cells = <0x0>;
  709. compatible = "allwinner,sunxi-periph-clock";
  710. clock-output-names = "uart0";
  711. linux,phandle = <0x18>;
  712. phandle = <0x18>;
  713. };
  714.  
  715. uart1 {
  716. #clock-cells = <0x0>;
  717. compatible = "allwinner,sunxi-periph-clock";
  718. clock-output-names = "uart1";
  719. linux,phandle = <0x1b>;
  720. phandle = <0x1b>;
  721. };
  722.  
  723. uart2 {
  724. #clock-cells = <0x0>;
  725. compatible = "allwinner,sunxi-periph-clock";
  726. clock-output-names = "uart2";
  727. linux,phandle = <0x1e>;
  728. phandle = <0x1e>;
  729. };
  730.  
  731. uart3 {
  732. #clock-cells = <0x0>;
  733. compatible = "allwinner,sunxi-periph-clock";
  734. clock-output-names = "uart3";
  735. linux,phandle = <0x21>;
  736. phandle = <0x21>;
  737. };
  738.  
  739. uart4 {
  740. #clock-cells = <0x0>;
  741. compatible = "allwinner,sunxi-periph-clock";
  742. clock-output-names = "uart4";
  743. linux,phandle = <0x24>;
  744. phandle = <0x24>;
  745. };
  746.  
  747. scr {
  748. #clock-cells = <0x0>;
  749. compatible = "allwinner,sunxi-periph-clock";
  750. clock-output-names = "scr";
  751. linux,phandle = <0x7d>;
  752. phandle = <0x7d>;
  753. };
  754.  
  755. twi0 {
  756. #clock-cells = <0x0>;
  757. compatible = "allwinner,sunxi-periph-clock";
  758. clock-output-names = "twi0";
  759. linux,phandle = <0x27>;
  760. phandle = <0x27>;
  761. };
  762.  
  763. twi1 {
  764. #clock-cells = <0x0>;
  765. compatible = "allwinner,sunxi-periph-clock";
  766. clock-output-names = "twi1";
  767. linux,phandle = <0x2a>;
  768. phandle = <0x2a>;
  769. };
  770.  
  771. twi2 {
  772. #clock-cells = <0x0>;
  773. compatible = "allwinner,sunxi-periph-clock";
  774. clock-output-names = "twi2";
  775. linux,phandle = <0x2d>;
  776. phandle = <0x2d>;
  777. };
  778.  
  779. twi3 {
  780. #clock-cells = <0x0>;
  781. compatible = "allwinner,sunxi-periph-clock";
  782. clock-output-names = "twi3";
  783. };
  784.  
  785. pio {
  786. #clock-cells = <0x0>;
  787. compatible = "allwinner,sunxi-periph-clock";
  788. clock-output-names = "pio";
  789. linux,phandle = <0xa>;
  790. phandle = <0xa>;
  791. };
  792.  
  793. cpurcir {
  794. #clock-cells = <0x0>;
  795. compatible = "allwinner,sunxi-periph-cpus-clock";
  796. clock-output-names = "cpurcir";
  797. linux,phandle = <0x12>;
  798. phandle = <0x12>;
  799. };
  800.  
  801. cpurpio {
  802. #clock-cells = <0x0>;
  803. compatible = "allwinner,sunxi-periph-cpus-clock";
  804. clock-output-names = "cpurpio";
  805. linux,phandle = <0x9>;
  806. phandle = <0x9>;
  807. };
  808.  
  809. cpurpll_peri0 {
  810. #clock-cells = <0x0>;
  811. compatible = "allwinner,sunxi-periph-cpus-clock";
  812. clock-output-names = "cpurpll_peri0";
  813. };
  814.  
  815. cpurcpus {
  816. #clock-cells = <0x0>;
  817. compatible = "allwinner,sunxi-periph-cpus-clock";
  818. clock-output-names = "cpurcpus";
  819. };
  820.  
  821. cpurahbs {
  822. #clock-cells = <0x0>;
  823. compatible = "allwinner,sunxi-periph-cpus-clock";
  824. clock-output-names = "cpurahbs";
  825. };
  826.  
  827. cpurapbs {
  828. #clock-cells = <0x0>;
  829. compatible = "allwinner,sunxi-periph-cpus-clock";
  830. clock-output-names = "cpurapbs";
  831. };
  832.  
  833. losc_out {
  834. #clock-cells = <0x0>;
  835. compatible = "allwinner,sunxi-periph-cpus-clock";
  836. clock-output-names = "losc_out";
  837. linux,phandle = <0x98>;
  838. phandle = <0x98>;
  839. };
  840. };
  841.  
  842. soc@01c00000 {
  843. compatible = "simple-bus";
  844. #address-cells = <0x2>;
  845. #size-cells = <0x2>;
  846. ranges;
  847. device_type = "soc";
  848.  
  849. pinctrl@01f02c00 {
  850. compatible = "allwinner,sun50i-r-pinctrl";
  851. reg = <0x0 0x1f02c00 0x0 0x400>;
  852. interrupts = <0x0 0x2d 0x4>;
  853. clocks = <0x9>;
  854. device_type = "r_pio";
  855. gpio-controller;
  856. interrupt-controller;
  857. #interrupt-cells = <0x2>;
  858. #size-cells = <0x0>;
  859. #gpio-cells = <0x6>;
  860. linux,phandle = <0x79>;
  861. phandle = <0x79>;
  862.  
  863. s_cir0@0 {
  864. allwinner,pins = "PL11";
  865. allwinner,function = "s_cir0";
  866. allwinner,muxsel = <0x2>;
  867. allwinner,drive = <0x2>;
  868. allwinner,pull = <0x1>;
  869. linux,phandle = <0x11>;
  870. phandle = <0x11>;
  871. };
  872.  
  873. spwm0@0 {
  874. linux,phandle = <0xaf>;
  875. phandle = <0xaf>;
  876. allwinner,pins = "PL10";
  877. allwinner,function = "spwm0";
  878. allwinner,pname = "pwm_positive";
  879. allwinner,muxsel = <0x2>;
  880. allwinner,pull = <0x0>;
  881. allwinner,drive = <0xffffffff>;
  882. allwinner,data = <0xffffffff>;
  883. };
  884.  
  885. spwm0@1 {
  886. linux,phandle = <0xb0>;
  887. phandle = <0xb0>;
  888. allwinner,pins = "PL10";
  889. allwinner,function = "spwm0";
  890. allwinner,pname = "pwm_positive";
  891. allwinner,muxsel = <0x7>;
  892. allwinner,pull = <0x0>;
  893. allwinner,drive = <0xffffffff>;
  894. allwinner,data = <0xffffffff>;
  895. };
  896.  
  897. s_uart0@0 {
  898. linux,phandle = <0xb6>;
  899. phandle = <0xb6>;
  900. allwinner,pins = "PL2", "PL3";
  901. allwinner,function = "s_uart0";
  902. allwinner,pname = "s_uart0_tx", "s_uart0_rx";
  903. allwinner,muxsel = <0x2>;
  904. allwinner,pull = <0xffffffff>;
  905. allwinner,drive = <0xffffffff>;
  906. allwinner,data = <0xffffffff>;
  907. };
  908.  
  909. s_rsb0@0 {
  910. linux,phandle = <0xb7>;
  911. phandle = <0xb7>;
  912. allwinner,pins = "PL0", "PL1";
  913. allwinner,function = "s_rsb0";
  914. allwinner,pname = "s_rsb0_sck", "s_rsb0_sda";
  915. allwinner,muxsel = <0x2>;
  916. allwinner,pull = <0x1>;
  917. allwinner,drive = <0x2>;
  918. allwinner,data = <0xffffffff>;
  919. };
  920.  
  921. s_jtag0@0 {
  922. linux,phandle = <0xb8>;
  923. phandle = <0xb8>;
  924. allwinner,pins = "PL4", "PL5", "PL6", "PL7";
  925. allwinner,function = "s_jtag0";
  926. allwinner,pname = "s_jtag0_tms", "s_jtag0_tck", "s_jtag0_tdo", "s_jtag0_tdi";
  927. allwinner,muxsel = <0x2>;
  928. allwinner,pull = <0x1>;
  929. allwinner,drive = <0x2>;
  930. allwinner,data = <0xffffffff>;
  931. };
  932. };
  933.  
  934. pinctrl@01c20800 {
  935. compatible = "allwinner,sun50i-pinctrl";
  936. reg = <0x0 0x1c20800 0x0 0x400>;
  937. interrupts = <0x0 0xb 0x4 0x0 0x11 0x4 0x0 0x15 0x4>;
  938. device_type = "pio";
  939. clocks = <0xa>;
  940. gpio-controller;
  941. interrupt-controller;
  942. #interrupt-cells = <0x2>;
  943. #size-cells = <0x0>;
  944. #gpio-cells = <0x6>;
  945. linux,phandle = <0x30>;
  946. phandle = <0x30>;
  947.  
  948. uart0@1 {
  949. allwinner,pins = "PB8", "PB9";
  950. allwinner,function = "io_disabled";
  951. allwinner,muxsel = <0x7>;
  952. allwinner,drive = <0x1>;
  953. allwinner,pull = <0x1>;
  954. linux,phandle = <0x1a>;
  955. phandle = <0x1a>;
  956. };
  957.  
  958. uart1@1 {
  959. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  960. allwinner,function = "io_disabled";
  961. allwinner,muxsel = <0x7>;
  962. allwinner,drive = <0x1>;
  963. allwinner,pull = <0x1>;
  964. linux,phandle = <0x1d>;
  965. phandle = <0x1d>;
  966. };
  967.  
  968. uart2@1 {
  969. allwinner,pins = "PB0", "PB1", "PB2", "PB3";
  970. allwinner,function = "io_disabled";
  971. allwinner,muxsel = <0x7>;
  972. allwinner,drive = <0x1>;
  973. allwinner,pull = <0x1>;
  974. linux,phandle = <0x20>;
  975. phandle = <0x20>;
  976. };
  977.  
  978. uart3@1 {
  979. allwinner,pins = "PH4", "PH5", "PH6", "PH7";
  980. allwinner,function = "io_disabled";
  981. allwinner,muxsel = <0x7>;
  982. allwinner,drive = <0x1>;
  983. allwinner,pull = <0x1>;
  984. linux,phandle = <0x23>;
  985. phandle = <0x23>;
  986. };
  987.  
  988. uart4@1 {
  989. allwinner,pins = "PD2", "PD3", "PD4", "PD5";
  990. allwinner,function = "io_disabled";
  991. allwinner,muxsel = <0x7>;
  992. allwinner,drive = <0x1>;
  993. allwinner,pull = <0x1>;
  994. linux,phandle = <0x26>;
  995. phandle = <0x26>;
  996. };
  997.  
  998. twi0@1 {
  999. allwinner,pins = "PH0", "PH1";
  1000. allwinner,function = "io_disabled";
  1001. allwinner,muxsel = <0x7>;
  1002. allwinner,drive = <0x1>;
  1003. allwinner,pull = <0x0>;
  1004. linux,phandle = <0x29>;
  1005. phandle = <0x29>;
  1006. };
  1007.  
  1008. twi1@1 {
  1009. allwinner,pins = "PH2", "PH3";
  1010. allwinner,function = "io_disabled";
  1011. allwinner,muxsel = <0x7>;
  1012. allwinner,drive = <0x1>;
  1013. allwinner,pull = <0x0>;
  1014. linux,phandle = <0x2c>;
  1015. phandle = <0x2c>;
  1016. };
  1017.  
  1018. twi2@1 {
  1019. allwinner,pins = "PE14", "PE15";
  1020. allwinner,function = "io_disabled";
  1021. allwinner,muxsel = <0x7>;
  1022. allwinner,drive = <0x1>;
  1023. allwinner,pull = <0x0>;
  1024. linux,phandle = <0x2f>;
  1025. phandle = <0x2f>;
  1026. };
  1027.  
  1028. spi0@2 {
  1029. allwinner,pins = "PC3", "PC2", "PC0", "PC1";
  1030. allwinner,function = "io_disabled";
  1031. allwinner,muxsel = <0x7>;
  1032. allwinner,drive = <0x1>;
  1033. allwinner,pull = <0x0>;
  1034. linux,phandle = <0x55>;
  1035. phandle = <0x55>;
  1036. };
  1037.  
  1038. spi1@2 {
  1039. allwinner,pins = "PD0", "PD1", "PD2", "PD3";
  1040. allwinner,function = "io_disabled";
  1041. allwinner,muxsel = <0x7>;
  1042. allwinner,drive = <0x1>;
  1043. allwinner,pull = <0x0>;
  1044. linux,phandle = <0x59>;
  1045. phandle = <0x59>;
  1046. };
  1047.  
  1048. sdc0@1 {
  1049. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1050. allwinner,function = "io_disabled";
  1051. allwinner,muxsel = <0x7>;
  1052. allwinner,drive = <0x1>;
  1053. allwinner,pull = <0x1>;
  1054. linux,phandle = <0x64>;
  1055. phandle = <0x64>;
  1056. };
  1057.  
  1058. sdc1@1 {
  1059. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  1060. allwinner,function = "io_disabled";
  1061. allwinner,muxsel = <0x7>;
  1062. allwinner,drive = <0x1>;
  1063. allwinner,pull = <0x1>;
  1064. linux,phandle = <0x69>;
  1065. phandle = <0x69>;
  1066. };
  1067.  
  1068. sdc2@1 {
  1069. allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1070. allwinner,function = "io_disabled";
  1071. allwinner,muxsel = <0x7>;
  1072. allwinner,drive = <0x1>;
  1073. allwinner,pull = <0x1>;
  1074. linux,phandle = <0x5f>;
  1075. phandle = <0x5f>;
  1076. };
  1077.  
  1078. daudio0@0 {
  1079. allwinner,pins = "PB6", "PB3", "PB4", "PB5", "PB7";
  1080. allwinner,function = "pcm0";
  1081. allwinner,muxsel = <0x3>;
  1082. allwinner,drive = <0x1>;
  1083. allwinner,pull = <0x0>;
  1084. linux,phandle = <0x43>;
  1085. phandle = <0x43>;
  1086. };
  1087.  
  1088. daudio0_sleep@0 {
  1089. allwinner,pins = "PB6", "PB3", "PB4", "PB5", "PB7";
  1090. allwinner,function = "io_disabled";
  1091. allwinner,muxsel = <0x7>;
  1092. allwinner,drive = <0x1>;
  1093. allwinner,pull = <0x0>;
  1094. linux,phandle = <0x44>;
  1095. phandle = <0x44>;
  1096. };
  1097.  
  1098. daudio1@0 {
  1099. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  1100. allwinner,function = "pcm1";
  1101. allwinner,muxsel = <0x3>;
  1102. allwinner,drive = <0x1>;
  1103. allwinner,pull = <0x0>;
  1104. linux,phandle = <0x45>;
  1105. phandle = <0x45>;
  1106. };
  1107.  
  1108. daudio1_sleep@0 {
  1109. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  1110. allwinner,function = "io_disabled";
  1111. allwinner,muxsel = <0x7>;
  1112. allwinner,drive = <0x1>;
  1113. allwinner,pull = <0x0>;
  1114. linux,phandle = <0x46>;
  1115. phandle = <0x46>;
  1116. };
  1117.  
  1118. aif3@0 {
  1119. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  1120. allwinner,function = "aif3";
  1121. allwinner,muxsel = <0x2>;
  1122. allwinner,drive = <0x1>;
  1123. allwinner,pull = <0x0>;
  1124. linux,phandle = <0x3e>;
  1125. phandle = <0x3e>;
  1126. };
  1127.  
  1128. aif2_sleep@0 {
  1129. allwinner,pins = "PB6", "PB4", "PB5", "PB7";
  1130. allwinner,function = "io_disabled";
  1131. allwinner,muxsel = <0x7>;
  1132. allwinner,drive = <0x1>;
  1133. allwinner,pull = <0x0>;
  1134. linux,phandle = <0x3f>;
  1135. phandle = <0x3f>;
  1136. };
  1137.  
  1138. aif3_sleep@0 {
  1139. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  1140. allwinner,function = "io_disabled";
  1141. allwinner,muxsel = <0x7>;
  1142. allwinner,drive = <0x1>;
  1143. allwinner,pull = <0x0>;
  1144. linux,phandle = <0x40>;
  1145. phandle = <0x40>;
  1146. };
  1147.  
  1148. spdif@0 {
  1149. allwinner,pins = "PH8";
  1150. allwinner,function = "spdif0";
  1151. allwinner,muxsel = <0x2>;
  1152. allwinner,drive = <0x1>;
  1153. allwinner,pull = <0x0>;
  1154. linux,phandle = <0x4a>;
  1155. phandle = <0x4a>;
  1156. };
  1157.  
  1158. spdif_sleep@0 {
  1159. allwinner,pins = "PH8";
  1160. allwinner,function = "io_disabled";
  1161. allwinner,muxsel = <0x7>;
  1162. allwinner,drive = <0x1>;
  1163. allwinner,pull = <0x0>;
  1164. linux,phandle = <0x4b>;
  1165. phandle = <0x4b>;
  1166. };
  1167.  
  1168. csi0_sleep@0 {
  1169. allwinner,pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", "PE12", "PE13";
  1170. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7", "csi0_sck", "csi0_sda";
  1171. allwinner,function = "io_disabled";
  1172. allwinner,muxsel = <0x7>;
  1173. allwinner,drive = <0x1>;
  1174. allwinner,pull = <0x0>;
  1175. allwinner,data = <0x0>;
  1176. linux,phandle = <0x77>;
  1177. phandle = <0x77>;
  1178. };
  1179.  
  1180. smartcard@0 {
  1181. allwinner,pins = "PB1", "PB4", "PB5", "PB6", "PB7";
  1182. allwinner,function = "sim0";
  1183. allwinner,muxsel = <0x5>;
  1184. allwinner,drive = <0x1>;
  1185. allwinner,pull = <0x1>;
  1186. linux,phandle = <0x7f>;
  1187. phandle = <0x7f>;
  1188. };
  1189.  
  1190. nand0@2 {
  1191. allwinner,pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16", "PC17", "PC18";
  1192. allwinner,function = "io_disabled";
  1193. allwinner,muxsel = <0x7>;
  1194. allwinner,drive = <0x1>;
  1195. allwinner,pull = <0x0>;
  1196. linux,phandle = <0x83>;
  1197. phandle = <0x83>;
  1198. };
  1199.  
  1200. card0_boot_para@0 {
  1201. linux,phandle = <0x99>;
  1202. phandle = <0x99>;
  1203. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1204. allwinner,function = "card0_boot_para";
  1205. allwinner,pname = "sdc_d1", "sdc_d0", "sdc_clk", "sdc_cmd", "sdc_d3", "sdc_d2";
  1206. allwinner,muxsel = <0x2>;
  1207. allwinner,pull = <0x1>;
  1208. allwinner,drive = <0x2>;
  1209. allwinner,data = <0xffffffff>;
  1210. };
  1211.  
  1212. card2_boot_para@0 {
  1213. linux,phandle = <0x9a>;
  1214. phandle = <0x9a>;
  1215. allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1216. allwinner,function = "card2_boot_para";
  1217. allwinner,pname = "sdc_ds", "sdc_clk", "sdc_cmd", "sdc_d0", "sdc_d1", "sdc_d2", "sdc_d3", "sdc_d4", "sdc_d5", "sdc_d6", "sdc_d7", "sdc_emmc_rst";
  1218. allwinner,muxsel = <0x3>;
  1219. allwinner,pull = <0x1>;
  1220. allwinner,drive = <0x3>;
  1221. allwinner,data = <0xffffffff>;
  1222. };
  1223.  
  1224. twi_para@0 {
  1225. linux,phandle = <0x9b>;
  1226. phandle = <0x9b>;
  1227. allwinner,pins = "PH0", "PH1";
  1228. allwinner,function = "twi_para";
  1229. allwinner,pname = "twi_scl", "twi_sda";
  1230. allwinner,muxsel = <0x2>;
  1231. allwinner,pull = <0xffffffff>;
  1232. allwinner,drive = <0xffffffff>;
  1233. allwinner,data = <0xffffffff>;
  1234. };
  1235.  
  1236. uart_para@0 {
  1237. linux,phandle = <0x9c>;
  1238. phandle = <0x9c>;
  1239. allwinner,pins = "PB8", "PB9";
  1240. allwinner,function = "uart_para";
  1241. allwinner,pname = "uart_debug_tx", "uart_debug_rx";
  1242. allwinner,muxsel = <0x4>;
  1243. allwinner,pull = <0x1>;
  1244. allwinner,drive = <0xffffffff>;
  1245. allwinner,data = <0xffffffff>;
  1246. };
  1247.  
  1248. jtag_para@0 {
  1249. linux,phandle = <0x9d>;
  1250. phandle = <0x9d>;
  1251. allwinner,pins = "PB0", "PB1", "PB2", "PB3";
  1252. allwinner,function = "jtag_para";
  1253. allwinner,pname = "jtag_ms", "jtag_ck", "jtag_do", "jtag_di";
  1254. allwinner,muxsel = <0x4>;
  1255. allwinner,pull = <0xffffffff>;
  1256. allwinner,drive = <0xffffffff>;
  1257. allwinner,data = <0xffffffff>;
  1258. };
  1259.  
  1260. gmac0@0 {
  1261. linux,phandle = <0x9e>;
  1262. phandle = <0x9e>;
  1263. allwinner,pins = "PD18", "PD17", "PD16", "PD15", "PD20", "PD19", "PD11", "PD10", "PD9", "PD8", "PD13", "PD12", "PD21", "PD22", "PD23";
  1264. allwinner,function = "gmac0";
  1265. allwinner,pname = "gmac_txd0", "gmac_txd1", "gmac_txd2", "gmac_txd3", "gmac_txen", "gmac_gtxclk", "gmac_rxd0", "gmac_rxd1", "gmac_rxd2", "gmac_rxd3", "gmac_rxdv", "gmac_rxclk", "gmac_clkin", "gmac_mdc", "gmac_mdio";
  1266. allwinner,muxsel = <0x4>;
  1267. allwinner,pull = <0xffffffff>;
  1268. allwinner,drive = <0xffffffff>;
  1269. allwinner,data = <0xffffffff>;
  1270. };
  1271.  
  1272. twi0@0 {
  1273. linux,phandle = <0x9f>;
  1274. phandle = <0x9f>;
  1275. allwinner,pins = "PH0", "PH1";
  1276. allwinner,function = "twi0";
  1277. allwinner,pname = "twi0_scl", "twi0_sda";
  1278. allwinner,muxsel = <0x2>;
  1279. allwinner,pull = <0xffffffff>;
  1280. allwinner,drive = <0xffffffff>;
  1281. allwinner,data = <0xffffffff>;
  1282. };
  1283.  
  1284. twi1@0 {
  1285. linux,phandle = <0xa0>;
  1286. phandle = <0xa0>;
  1287. allwinner,pins = "PH2", "PH3";
  1288. allwinner,function = "twi1";
  1289. allwinner,pname = "twi1_scl", "twi1_sda";
  1290. allwinner,muxsel = <0x2>;
  1291. allwinner,pull = <0xffffffff>;
  1292. allwinner,drive = <0xffffffff>;
  1293. allwinner,data = <0xffffffff>;
  1294. };
  1295.  
  1296. twi2@0 {
  1297. linux,phandle = <0xa1>;
  1298. phandle = <0xa1>;
  1299. allwinner,pins = "PE14", "PE15";
  1300. allwinner,function = "twi2";
  1301. allwinner,pname = "twi2_scl", "twi2_sda";
  1302. allwinner,muxsel = <0x3>;
  1303. allwinner,pull = <0xffffffff>;
  1304. allwinner,drive = <0xffffffff>;
  1305. allwinner,data = <0xffffffff>;
  1306. };
  1307.  
  1308. uart0@0 {
  1309. linux,phandle = <0xa2>;
  1310. phandle = <0xa2>;
  1311. allwinner,pins = "PB8", "PB9";
  1312. allwinner,function = "uart0";
  1313. allwinner,pname = "uart0_tx", "uart0_rx";
  1314. allwinner,muxsel = <0x4>;
  1315. allwinner,pull = <0x1>;
  1316. allwinner,drive = <0xffffffff>;
  1317. allwinner,data = <0xffffffff>;
  1318. };
  1319.  
  1320. uart1@0 {
  1321. linux,phandle = <0xa3>;
  1322. phandle = <0xa3>;
  1323. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  1324. allwinner,function = "uart1";
  1325. allwinner,pname = "uart1_tx", "uart1_rx", "uart1_rts", "uart1_cts";
  1326. allwinner,muxsel = <0x2>;
  1327. allwinner,pull = <0x1>;
  1328. allwinner,drive = <0xffffffff>;
  1329. allwinner,data = <0xffffffff>;
  1330. };
  1331.  
  1332. uart2@0 {
  1333. linux,phandle = <0xa4>;
  1334. phandle = <0xa4>;
  1335. allwinner,pins = "PB0", "PB1", "PB2", "PB3";
  1336. allwinner,function = "uart2";
  1337. allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
  1338. allwinner,muxsel = <0x2>;
  1339. allwinner,pull = <0x1>;
  1340. allwinner,drive = <0xffffffff>;
  1341. allwinner,data = <0xffffffff>;
  1342. };
  1343.  
  1344. uart3@0 {
  1345. linux,phandle = <0xa5>;
  1346. phandle = <0xa5>;
  1347. allwinner,pins = "PH4", "PH5", "PH6", "PH7";
  1348. allwinner,function = "uart3";
  1349. allwinner,pname = "uart3_tx", "uart3_rx", "uart3_rts", "uart3_cts";
  1350. allwinner,muxsel = <0x2>;
  1351. allwinner,pull = <0x1>;
  1352. allwinner,drive = <0xffffffff>;
  1353. allwinner,data = <0xffffffff>;
  1354. };
  1355.  
  1356. uart4@0 {
  1357. linux,phandle = <0xa6>;
  1358. phandle = <0xa6>;
  1359. allwinner,pins = "PD2", "PD3", "PD4", "PD5";
  1360. allwinner,function = "uart4";
  1361. allwinner,pname = "uart4_tx", "uart4_rx", "uart4_rts", "uart4_cts";
  1362. allwinner,muxsel = <0x3>;
  1363. allwinner,pull = <0x1>;
  1364. allwinner,drive = <0xffffffff>;
  1365. allwinner,data = <0xffffffff>;
  1366. };
  1367.  
  1368. spi0@0 {
  1369. linux,phandle = <0xa7>;
  1370. phandle = <0xa7>;
  1371. allwinner,pins = "PC3";
  1372. allwinner,function = "spi0";
  1373. allwinner,pname = "spi0_cs0";
  1374. allwinner,muxsel = <0x4>;
  1375. allwinner,pull = <0x1>;
  1376. allwinner,drive = <0xffffffff>;
  1377. allwinner,data = <0xffffffff>;
  1378. };
  1379.  
  1380. spi0@1 {
  1381. linux,phandle = <0xa8>;
  1382. phandle = <0xa8>;
  1383. allwinner,pins = "PC2", "PC0", "PC1";
  1384. allwinner,function = "spi0";
  1385. allwinner,pname = "spi0_sclk", "spi0_mosi", "spi0_miso";
  1386. allwinner,muxsel = <0x4>;
  1387. allwinner,pull = <0xffffffff>;
  1388. allwinner,drive = <0xffffffff>;
  1389. allwinner,data = <0xffffffff>;
  1390. };
  1391.  
  1392. spi1@0 {
  1393. linux,phandle = <0xa9>;
  1394. phandle = <0xa9>;
  1395. allwinner,pins = "PD0";
  1396. allwinner,function = "spi1";
  1397. allwinner,pname = "spi1_cs0";
  1398. allwinner,muxsel = <0x4>;
  1399. allwinner,pull = <0x1>;
  1400. allwinner,drive = <0xffffffff>;
  1401. allwinner,data = <0xffffffff>;
  1402. };
  1403.  
  1404. spi1@1 {
  1405. linux,phandle = <0xaa>;
  1406. phandle = <0xaa>;
  1407. allwinner,pins = "PD1", "PD2", "PD3";
  1408. allwinner,function = "spi1";
  1409. allwinner,pname = "spi1_sclk", "spi1_mosi", "spi1_miso";
  1410. allwinner,muxsel = <0x4>;
  1411. allwinner,pull = <0xffffffff>;
  1412. allwinner,drive = <0xffffffff>;
  1413. allwinner,data = <0xffffffff>;
  1414. };
  1415.  
  1416. nand0@0 {
  1417. linux,phandle = <0xab>;
  1418. phandle = <0xab>;
  1419. allwinner,pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1420. allwinner,function = "nand0";
  1421. allwinner,pname = "nand0_we", "nand0_ale", "nand0_cle", "nand0_nre", "nand0_d0", "nand0_d1", "nand0_d2", "nand0_d3", "nand0_d4", "nand0_d5", "nand0_d6", "nand0_d7", "nand0_ndqs";
  1422. allwinner,muxsel = <0x2>;
  1423. allwinner,pull = <0x0>;
  1424. allwinner,drive = <0x1>;
  1425. allwinner,data = <0xffffffff>;
  1426. };
  1427.  
  1428. nand0@1 {
  1429. linux,phandle = <0xac>;
  1430. phandle = <0xac>;
  1431. allwinner,pins = "PC3", "PC4", "PC6", "PC7", "PC17", "PC18";
  1432. allwinner,function = "nand0";
  1433. allwinner,pname = "nand0_ce1", "nand0_ce0", "nand0_rb0", "nand0_rb1", "nand0_ce2", "nand0_ce3";
  1434. allwinner,muxsel = <0x2>;
  1435. allwinner,pull = <0x1>;
  1436. allwinner,drive = <0x1>;
  1437. allwinner,data = <0xffffffff>;
  1438. };
  1439.  
  1440. pwm0@0 {
  1441. linux,phandle = <0xad>;
  1442. phandle = <0xad>;
  1443. allwinner,pins = "PD22";
  1444. allwinner,function = "pwm0";
  1445. allwinner,pname = "pwm_positive";
  1446. allwinner,muxsel = <0x2>;
  1447. allwinner,pull = <0x0>;
  1448. allwinner,drive = <0xffffffff>;
  1449. allwinner,data = <0xffffffff>;
  1450. };
  1451.  
  1452. pwm0@1 {
  1453. linux,phandle = <0xae>;
  1454. phandle = <0xae>;
  1455. allwinner,pins = "PD22";
  1456. allwinner,function = "pwm0";
  1457. allwinner,pname = "pwm_positive";
  1458. allwinner,muxsel = <0x7>;
  1459. allwinner,pull = <0x0>;
  1460. allwinner,drive = <0xffffffff>;
  1461. allwinner,data = <0xffffffff>;
  1462. };
  1463.  
  1464. csi0@0 {
  1465. linux,phandle = <0xb1>;
  1466. phandle = <0xb1>;
  1467. allwinner,pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", "PE12", "PE13";
  1468. allwinner,function = "csi0";
  1469. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7", "csi0_sck", "csi0_sda";
  1470. allwinner,muxsel = <0x2>;
  1471. allwinner,pull = <0xffffffff>;
  1472. allwinner,drive = <0xffffffff>;
  1473. allwinner,data = <0xffffffff>;
  1474. };
  1475.  
  1476. sdc0@0 {
  1477. linux,phandle = <0xb2>;
  1478. phandle = <0xb2>;
  1479. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1480. allwinner,function = "sdc0";
  1481. allwinner,pname = "sdc0_d1", "sdc0_d0", "sdc0_clk", "sdc0_cmd", "sdc0_d3", "sdc0_d2";
  1482. allwinner,muxsel = <0x2>;
  1483. allwinner,pull = <0x1>;
  1484. allwinner,drive = <0x2>;
  1485. allwinner,data = <0xffffffff>;
  1486. };
  1487.  
  1488. sdc1@0 {
  1489. linux,phandle = <0xb3>;
  1490. phandle = <0xb3>;
  1491. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  1492. allwinner,function = "sdc1";
  1493. allwinner,pname = "sdc1_clk", "sdc1_cmd", "sdc1_d0", "sdc1_d1", "sdc1_d2", "sdc1_d3";
  1494. allwinner,muxsel = <0x2>;
  1495. allwinner,pull = <0x1>;
  1496. allwinner,drive = <0x3>;
  1497. allwinner,data = <0xffffffff>;
  1498. };
  1499.  
  1500. sdc2@0 {
  1501. linux,phandle = <0xb4>;
  1502. phandle = <0xb4>;
  1503. allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1504. allwinner,function = "sdc2";
  1505. allwinner,pname = "sdc2_ds", "sdc2_clk", "sdc2_cmd", "sdc2_d0", "sdc2_d1", "sdc2_d2", "sdc2_d3", "sdc2_d4", "sdc2_d5", "sdc2_d6", "sdc2_d7", "sdc2_emmc_rst";
  1506. allwinner,muxsel = <0x3>;
  1507. allwinner,pull = <0x1>;
  1508. allwinner,drive = <0x3>;
  1509. allwinner,data = <0xffffffff>;
  1510. };
  1511.  
  1512. codec@0 {
  1513. linux,phandle = <0xb5>;
  1514. phandle = <0xb5>;
  1515. allwinner,pins = "PH7";
  1516. allwinner,function = "codec";
  1517. allwinner,pname = "gpio-spk";
  1518. allwinner,muxsel = <0x2>;
  1519. allwinner,pull = <0x1>;
  1520. allwinner,drive = <0xffffffff>;
  1521. allwinner,data = <0xffffffff>;
  1522. };
  1523.  
  1524. Vdevice@0 {
  1525. linux,phandle = <0xb9>;
  1526. phandle = <0xb9>;
  1527. allwinner,pins = "PB1", "PB2";
  1528. allwinner,function = "Vdevice";
  1529. allwinner,pname = "Vdevice_0", "Vdevice_1";
  1530. allwinner,muxsel = <0x4>;
  1531. allwinner,pull = <0x1>;
  1532. allwinner,drive = <0x2>;
  1533. allwinner,data = <0xffffffff>;
  1534. };
  1535. };
  1536.  
  1537. pinctrl@0 {
  1538. compatible = "allwinner,axp-pinctrl";
  1539. gpio-controller;
  1540. #size-cells = <0x0>;
  1541. #gpio-cells = <0x6>;
  1542. device_type = "axp_pio";
  1543. linux,phandle = <0x31>;
  1544. phandle = <0x31>;
  1545. };
  1546.  
  1547. dma-controller@01c02000 {
  1548. compatible = "allwinner,sun50i-dma";
  1549. reg = <0x0 0x1c02000 0x0 0x1000>;
  1550. interrupts = <0x0 0x32 0x4>;
  1551. clocks = <0xb>;
  1552. #dma-cells = <0x1>;
  1553. };
  1554.  
  1555. mbus-controller@01c62000 {
  1556. compatible = "allwinner,sun50i-mbus";
  1557. reg = <0x0 0x1c62000 0x0 0x110>;
  1558. #mbus-cells = <0x1>;
  1559. };
  1560.  
  1561. arisc {
  1562. compatible = "allwinner,sunxi-arisc";
  1563. #address-cells = <0x2>;
  1564. #size-cells = <0x2>;
  1565. clocks = <0xc 0xd 0x6 0x4>;
  1566. clock-names = "losc", "iosc", "hosc", "pll_periph0";
  1567. powchk_used = <0x0>;
  1568. power_reg = <0x2309621>;
  1569. system_power = <0x32>;
  1570. };
  1571.  
  1572. arisc_space {
  1573. compatible = "allwinner,arisc_space";
  1574. space1 = <0x40000 0x0 0x14000>;
  1575. space2 = <0x40100000 0x18000 0x4000>;
  1576. space3 = <0x40104000 0x0 0x1000>;
  1577. space4 = <0x40105000 0x0 0x1000>;
  1578. };
  1579.  
  1580. standby_space {
  1581. compatible = "allwinner,standby_space";
  1582. space1 = <0x41020000 0x0 0x800>;
  1583. };
  1584.  
  1585. msgbox@1c17000 {
  1586. compatible = "allwinner,msgbox";
  1587. clocks = <0xe>;
  1588. clock-names = "clk_msgbox";
  1589. reg = <0x0 0x1c17000 0x0 0x1000>;
  1590. interrupts = <0x0 0x31 0x1>;
  1591. status = "okay";
  1592. };
  1593.  
  1594. hwspinlock@1c18000 {
  1595. compatible = "allwinner,sunxi-hwspinlock";
  1596. clocks = <0xf 0x10>;
  1597. clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
  1598. reg = <0x0 0x1c18000 0x0 0x1000>;
  1599. status = "okay";
  1600. num-locks = <0x8>;
  1601. };
  1602.  
  1603. s_cir@1f02000 {
  1604. compatible = "allwinner,s_cir";
  1605. reg = <0x0 0x1f02000 0x0 0x400>;
  1606. interrupts = <0x0 0x25 0x4>;
  1607. pinctrl-names = "default";
  1608. pinctrl-0 = <0x11>;
  1609. clocks = <0x6 0x12>;
  1610. supply = "vcc-pl";
  1611. ir_power_key_code = <0x4d>;
  1612. ir_addr_code = <0x4040>;
  1613. status = "okay";
  1614. device_type = "s_cir0";
  1615. };
  1616.  
  1617. s_uart@1f02800 {
  1618. compatible = "allwinner,s_uart";
  1619. reg = <0x0 0x1f02800 0x0 0x400>;
  1620. interrupts = <0x0 0x26 0x4>;
  1621. pinctrl-names = "default";
  1622. status = "okay";
  1623. device_type = "s_uart0";
  1624. pinctrl-0 = <0xb6>;
  1625. };
  1626.  
  1627. s_rsb@1f03400 {
  1628. compatible = "allwinner,s_rsb";
  1629. reg = <0x0 0x1f03400 0x0 0x400>;
  1630. interrupts = <0x0 0x27 0x4>;
  1631. pinctrl-names = "default";
  1632. status = "okay";
  1633. device_type = "s_rsb0";
  1634. pinctrl-0 = <0xb7>;
  1635. };
  1636.  
  1637. s_jtag0 {
  1638. compatible = "allwinner,s_jtag";
  1639. pinctrl-names = "default";
  1640. status = "disabled";
  1641. device_type = "s_jtag0";
  1642. pinctrl-0 = <0xb8>;
  1643. };
  1644.  
  1645. timer@1c20c00 {
  1646. compatible = "allwinner,sunxi-timer";
  1647. device_type = "timer";
  1648. reg = <0x0 0x1c20c00 0x0 0x90>;
  1649. interrupts = <0x0 0x12 0x1>;
  1650. clock-frequency = <0x16e3600>;
  1651. timer-prescale = <0x10>;
  1652. };
  1653.  
  1654. rtc@01f00000 {
  1655. compatible = "allwinner,sun50i-rtc";
  1656. device_type = "rtc";
  1657. reg = <0x0 0x1f00000 0x0 0x218>;
  1658. interrupts = <0x0 0x28 0x4>;
  1659. gpr_offset = <0x100>;
  1660. gpr_len = <0x4>;
  1661. };
  1662.  
  1663. ve@01c0e000 {
  1664. compatible = "allwinner,sunxi-cedar-ve";
  1665. reg = <0x0 0x1c0e000 0x0 0x1000 0x0 0x1c00000 0x0 0x10 0x0 0x1c20000 0x0 0x800>;
  1666. interrupts = <0x0 0x3a 0x4>;
  1667. clocks = <0x16 0x17>;
  1668. };
  1669.  
  1670. uart@01c28000 {
  1671. compatible = "allwinner,sun50i-uart";
  1672. device_type = "uart0";
  1673. reg = <0x0 0x1c28000 0x0 0x400>;
  1674. interrupts = <0x0 0x0 0x4>;
  1675. clocks = <0x18>;
  1676. pinctrl-names = "default", "sleep";
  1677. pinctrl-1 = <0x1a>;
  1678. uart0_port = <0x0>;
  1679. uart0_type = <0x2>;
  1680. status = "okay";
  1681. pinctrl-0 = <0xa2>;
  1682. };
  1683.  
  1684. uart@01c28400 {
  1685. compatible = "allwinner,sun50i-uart";
  1686. device_type = "uart1";
  1687. reg = <0x0 0x1c28400 0x0 0x400>;
  1688. interrupts = <0x0 0x1 0x4>;
  1689. clocks = <0x1b>;
  1690. pinctrl-names = "default", "sleep";
  1691. pinctrl-1 = <0x1d>;
  1692. uart1_port = <0x1>;
  1693. uart1_type = <0x4>;
  1694. status = "okay";
  1695. pinctrl-0 = <0xa3>;
  1696. };
  1697.  
  1698. uart@01c28800 {
  1699. compatible = "allwinner,sun50i-uart";
  1700. device_type = "uart2";
  1701. reg = <0x0 0x1c28800 0x0 0x400>;
  1702. interrupts = <0x0 0x2 0x4>;
  1703. clocks = <0x1e>;
  1704. pinctrl-names = "default", "sleep";
  1705. pinctrl-1 = <0x20>;
  1706. uart2_port = <0x2>;
  1707. uart2_type = <0x4>;
  1708. status = "disabled";
  1709. pinctrl-0 = <0xa4>;
  1710. };
  1711.  
  1712. uart@01c28c00 {
  1713. compatible = "allwinner,sun50i-uart";
  1714. device_type = "uart3";
  1715. reg = <0x0 0x1c28c00 0x0 0x400>;
  1716. interrupts = <0x0 0x3 0x4>;
  1717. clocks = <0x21>;
  1718. pinctrl-names = "default", "sleep";
  1719. pinctrl-1 = <0x23>;
  1720. uart3_port = <0x3>;
  1721. uart3_type = <0x4>;
  1722. status = "disabled";
  1723. pinctrl-0 = <0xa5>;
  1724. };
  1725.  
  1726. uart@01c29000 {
  1727. compatible = "allwinner,sun50i-uart";
  1728. device_type = "uart4";
  1729. reg = <0x0 0x1c29000 0x0 0x400>;
  1730. interrupts = <0x0 0x4 0x4>;
  1731. clocks = <0x24>;
  1732. pinctrl-names = "default", "sleep";
  1733. pinctrl-1 = <0x26>;
  1734. uart4_port = <0x4>;
  1735. uart4_type = <0x4>;
  1736. status = "disabled";
  1737. pinctrl-0 = <0xa6>;
  1738. };
  1739.  
  1740. twi@0x01c2ac00 {
  1741. #address-cells = <0x1>;
  1742. #size-cells = <0x0>;
  1743. compatible = "allwinner,sun50i-twi";
  1744. device_type = "twi0";
  1745. reg = <0x0 0x1c2ac00 0x0 0x400>;
  1746. interrupts = <0x0 0x6 0x4>;
  1747. clocks = <0x27>;
  1748. clock-frequency = <0x61a80>;
  1749. pinctrl-names = "default", "sleep";
  1750. pinctrl-1 = <0x29>;
  1751. status = "okay";
  1752. pinctrl-0 = <0x9f>;
  1753. };
  1754.  
  1755. twi@0x01c2b000 {
  1756. #address-cells = <0x1>;
  1757. #size-cells = <0x0>;
  1758. compatible = "allwinner,sun50i-twi";
  1759. device_type = "twi1";
  1760. reg = <0x0 0x1c2b000 0x0 0x400>;
  1761. interrupts = <0x0 0x7 0x4>;
  1762. clocks = <0x2a>;
  1763. clock-frequency = <0x30d40>;
  1764. pinctrl-names = "default", "sleep";
  1765. pinctrl-1 = <0x2c>;
  1766. status = "okay";
  1767. pinctrl-0 = <0xa0>;
  1768. };
  1769.  
  1770. twi@0x01c2b400 {
  1771. #address-cells = <0x1>;
  1772. #size-cells = <0x0>;
  1773. compatible = "allwinner,sun50i-twi";
  1774. device_type = "twi2";
  1775. reg = <0x0 0x1c2b400 0x0 0x400>;
  1776. interrupts = <0x0 0x8 0x4>;
  1777. clocks = <0x2d>;
  1778. clock-frequency = <0x30d40>;
  1779. pinctrl-names = "default", "sleep";
  1780. pinctrl-1 = <0x2f>;
  1781. status = "disabled";
  1782. pinctrl-0 = <0xa1>;
  1783. };
  1784.  
  1785. usbc0@0 {
  1786. device_type = "usbc0";
  1787. compatible = "allwinner,sunxi-otg-manager";
  1788. usb_port_type = <0x1>;
  1789. usb_detect_type = <0x0>;
  1790. usb_host_init_state = <0x1>;
  1791. usb_regulator_io = "nocare";
  1792. usb_wakeup_suspend = <0x1>;
  1793. usb_luns = <0x3>;
  1794. usb_serial_unique = <0x1>;
  1795. usb_serial_number = "20080411";
  1796. rndis_wceis = <0x1>;
  1797. status = "okay";
  1798. usb_id_gpio;
  1799. usb_det_vbus_gpio;
  1800. usb_drv_vbus_gpio;
  1801. };
  1802.  
  1803. udc-controller@0x01c19000 {
  1804. compatible = "allwinner,sunxi-udc";
  1805. reg = <0x0 0x1c19000 0x0 0x1000 0x0 0x1c00000 0x0 0x100>;
  1806. interrupts = <0x0 0x47 0x4>;
  1807. clocks = <0x32 0x33>;
  1808. status = "okay";
  1809. };
  1810.  
  1811. ehci0-controller@0x01c1a000 {
  1812. compatible = "allwinner,sunxi-ehci0";
  1813. reg = <0x0 0x1c1a000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1814. interrupts = <0x0 0x48 0x4>;
  1815. clocks = <0x32 0x34>;
  1816. hci_ctrl_no = <0x0>;
  1817. status = "okay";
  1818. };
  1819.  
  1820. ohci0-controller@0x01c1a400 {
  1821. compatible = "allwinner,sunxi-ohci0";
  1822. reg = <0x0 0x1c1a000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1823. interrupts = <0x0 0x49 0x4>;
  1824. clocks = <0x32 0x35>;
  1825. hci_ctrl_no = <0x0>;
  1826. status = "okay";
  1827. };
  1828.  
  1829. usbc1@0 {
  1830. device_type = "usbc1";
  1831. usb_host_init_state = <0x1>;
  1832. usb_regulator_io = "nocare";
  1833. usb_wakeup_suspend = <0x1>;
  1834. usb_hsic_used = <0x0>;
  1835. usb_hsic_regulator_io = "vcc-hsic-12";
  1836. usb_hsic_ctrl = <0x0>;
  1837. usb_hsic_usb3503_flag = <0x0>;
  1838. status = "okay";
  1839. usb_port_type = <0x1>;
  1840. usb_detect_type = <0x0>;
  1841. usb_drv_vbus_gpio;
  1842. usb_hsic_rdy_gpio;
  1843. usb_hsic_hub_connect_gpio;
  1844. usb_hsic_int_n_gpio;
  1845. usb_hsic_reset_n_gpio;
  1846. };
  1847.  
  1848. ehci1-controller@0x01c1b000 {
  1849. compatible = "allwinner,sunxi-ehci1";
  1850. reg = <0x0 0x1c1b000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1851. interrupts = <0x0 0x4a 0x4>;
  1852. clocks = <0x36 0x37 0x38 0x39 0x3a>;
  1853. hci_ctrl_no = <0x1>;
  1854. status = "okay";
  1855. };
  1856.  
  1857. ohci1-controller@0x01c1b400 {
  1858. compatible = "allwinner,sunxi-ohci1";
  1859. reg = <0x0 0x1c1b000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1860. interrupts = <0x0 0x4b 0x4>;
  1861. clocks = <0x36 0x3b>;
  1862. hci_ctrl_no = <0x1>;
  1863. status = "okay";
  1864. };
  1865.  
  1866. codec@0x01c22c00 {
  1867. compatible = "allwinner,sunxi-internal-codec";
  1868. reg = <0x0 0x1c22c00 0x0 0x478 0x0 0x1f015c0 0x0 0x0>;
  1869. clocks = <0x3c>;
  1870. pinctrl-names = "aif2-default", "aif3-default", "aif2-sleep", "aif3-sleep";
  1871. pinctrl-1 = <0x3e>;
  1872. pinctrl-2 = <0x3f>;
  1873. pinctrl-3 = <0x40>;
  1874. gpio-spk = <0x30 0x7 0x7 0x1 0x1 0x1 0x1>;
  1875. headphonevol = <0x3b>;
  1876. spkervol = <0x1a>;
  1877. earpiecevol = <0x1e>;
  1878. maingain = <0x4>;
  1879. headsetmicgain = <0x4>;
  1880. adcagc_cfg = <0x0>;
  1881. adcdrc_cfg = <0x0>;
  1882. adchpf_cfg = <0x0>;
  1883. dacdrc_cfg = <0x0>;
  1884. dachpf_cfg = <0x0>;
  1885. aif1_lrlk_div = <0x40>;
  1886. aif2_lrlk_div = <0x40>;
  1887. aif2config = <0x0>;
  1888. aif3config = <0x0>;
  1889. pa_sleep_time = <0x15e>;
  1890. dac_digital_vol = <0xa0a0>;
  1891. status = "okay";
  1892. linux,phandle = <0x4d>;
  1893. phandle = <0x4d>;
  1894. device_type = "codec";
  1895. pinctrl-0 = <0xb5>;
  1896. };
  1897.  
  1898. i2s0-controller@0x01c22c00 {
  1899. compatible = "allwinner,sunxi-internal-i2s";
  1900. reg = <0x0 0x1c22c00 0x0 0x478>;
  1901. clocks = <0x2 0x41>;
  1902. status = "okay";
  1903. linux,phandle = <0x4c>;
  1904. phandle = <0x4c>;
  1905. device_type = "i2s";
  1906. };
  1907.  
  1908. daudio@0x01c22000 {
  1909. compatible = "allwinner,sunxi-daudio";
  1910. reg = <0x0 0x1c22000 0x0 0x58>;
  1911. clocks = <0x2 0x42>;
  1912. pinctrl-names = "default", "sleep";
  1913. pinctrl-0 = <0x43>;
  1914. pinctrl-1 = <0x44>;
  1915. pcm_lrck_period = <0x20>;
  1916. pcm_lrckr_period = <0x1>;
  1917. slot_width_select = <0x20>;
  1918. pcm_lsb_first = <0x0>;
  1919. tx_data_mode = <0x0>;
  1920. rx_data_mode = <0x0>;
  1921. daudio_master = <0x4>;
  1922. audio_format = <0x1>;
  1923. signal_inversion = <0x1>;
  1924. frametype = <0x0>;
  1925. tdm_config = <0x1>;
  1926. tdm_num = <0x0>;
  1927. status = "disabled";
  1928. linux,phandle = <0x4e>;
  1929. phandle = <0x4e>;
  1930. device_type = "daudio0";
  1931. };
  1932.  
  1933. daudio@0x01c22400 {
  1934. compatible = "allwinner,sunxi-daudio";
  1935. reg = <0x0 0x1c22400 0x0 0x58>;
  1936. pinctrl-names = "default", "sleep";
  1937. pinctrl-0 = <0x45>;
  1938. pinctrl-1 = <0x46>;
  1939. clocks = <0x2 0x47>;
  1940. pcm_lrck_period = <0x20>;
  1941. pcm_lrckr_period = <0x1>;
  1942. slot_width_select = <0x20>;
  1943. pcm_lsb_first = <0x0>;
  1944. tx_data_mode = <0x0>;
  1945. rx_data_mode = <0x0>;
  1946. daudio_master = <0x4>;
  1947. audio_format = <0x1>;
  1948. signal_inversion = <0x1>;
  1949. frametype = <0x0>;
  1950. tdm_config = <0x1>;
  1951. tdm_num = <0x1>;
  1952. status = "disabled";
  1953. linux,phandle = <0x4f>;
  1954. phandle = <0x4f>;
  1955. device_type = "daudio1";
  1956. };
  1957.  
  1958. daudio@0x01c22800 {
  1959. compatible = "allwinner,sunxi-tdmhdmi";
  1960. reg = <0x0 0x1c22800 0x0 0x58>;
  1961. clocks = <0x2 0x48>;
  1962. status = "okay";
  1963. linux,phandle = <0x50>;
  1964. phandle = <0x50>;
  1965. device_type = "daudio2";
  1966. };
  1967.  
  1968. spdif-controller@0x01c21000 {
  1969. compatible = "allwinner,sunxi-spdif";
  1970. reg = <0x0 0x1c21000 0x0 0x38>;
  1971. clocks = <0x2 0x49>;
  1972. pinctrl-names = "default", "sleep";
  1973. pinctrl-0 = <0x4a>;
  1974. pinctrl-1 = <0x4b>;
  1975. status = "disabled";
  1976. linux,phandle = <0x51>;
  1977. phandle = <0x51>;
  1978. device_type = "spdif";
  1979. };
  1980.  
  1981. sound@0 {
  1982. compatible = "allwinner,sunxi-codec-machine";
  1983. interrupts = <0x0 0x1c 0x4>;
  1984. sunxi,i2s-controller = <0x4c>;
  1985. sunxi,audio-codec = <0x4d>;
  1986. aif2fmt = <0x3>;
  1987. aif3fmt = <0x3>;
  1988. aif2master = <0x1>;
  1989. hp_detect_case = <0x1>;
  1990. status = "okay";
  1991. device_type = "sndcodec";
  1992. };
  1993.  
  1994. sound@1 {
  1995. compatible = "allwinner,sunxi-daudio0-machine";
  1996. sunxi,daudio0-controller = <0x4e>;
  1997. status = "disabled";
  1998. device_type = "snddaudio0";
  1999. };
  2000.  
  2001. sound@2 {
  2002. compatible = "allwinner,sunxi-daudio1-machine";
  2003. sunxi,daudio1-controller = <0x4f>;
  2004. status = "disabled";
  2005. device_type = "snddaudio1";
  2006. };
  2007.  
  2008. sound@3 {
  2009. compatible = "allwinner,sunxi-hdmi-machine";
  2010. sunxi,hdmi-controller = <0x50>;
  2011. status = "okay";
  2012. device_type = "sndhdmi";
  2013. };
  2014.  
  2015. sound@4 {
  2016. compatible = "allwinner,sunxi-spdif-machine";
  2017. sunxi,spdif-controller = <0x51>;
  2018. status = "disabled";
  2019. device_type = "sndspdif";
  2020. };
  2021.  
  2022. spi@01c68000 {
  2023. #address-cells = <0x1>;
  2024. #size-cells = <0x0>;
  2025. compatible = "allwinner,sun50i-spi";
  2026. device_type = "spi0";
  2027. reg = <0x0 0x1c68000 0x0 0x1000>;
  2028. interrupts = <0x0 0x41 0x4>;
  2029. clocks = <0x4 0x52>;
  2030. clock-frequency = <0x5f5e100>;
  2031. pinctrl-names = "default", "sleep";
  2032. pinctrl-1 = <0x55>;
  2033. spi0_cs_number = <0x1>;
  2034. spi0_cs_bitmap = <0x1>;
  2035. status = "disabled";
  2036. pinctrl-0 = <0xa7 0xa8>;
  2037. };
  2038.  
  2039. spi@01c69000 {
  2040. #address-cells = <0x1>;
  2041. #size-cells = <0x0>;
  2042. compatible = "allwinner,sun50i-spi";
  2043. device_type = "spi1";
  2044. reg = <0x0 0x1c69000 0x0 0x1000>;
  2045. interrupts = <0x0 0x42 0x4>;
  2046. clocks = <0x4 0x56>;
  2047. clock-frequency = <0x5f5e100>;
  2048. pinctrl-names = "default", "sleep";
  2049. pinctrl-1 = <0x59>;
  2050. spi1_cs_number = <0x1>;
  2051. spi1_cs_bitmap = <0x1>;
  2052. status = "disabled";
  2053. pinctrl-0 = <0xa9 0xaa>;
  2054. };
  2055.  
  2056. sdmmc@01C11000 {
  2057. compatible = "allwinner,sun50i-sdmmc2";
  2058. device_type = "sdc2";
  2059. reg = <0x0 0x1c11000 0x0 0x1000>;
  2060. interrupts = <0x0 0x3e 0x104>;
  2061. clocks = <0x6 0x5a 0x5b 0x5c 0x5d>;
  2062. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2063. pinctrl-names = "default", "sleep";
  2064. pinctrl-1 = <0x5f>;
  2065. bus-width = <0x8>;
  2066. max-frequency = <0x5f5e100>;
  2067. sdc_tm4_sm0_freq0 = <0x0>;
  2068. sdc_tm4_sm0_freq1 = <0x0>;
  2069. sdc_tm4_sm1_freq0 = <0x0>;
  2070. sdc_tm4_sm1_freq1 = <0x0>;
  2071. sdc_tm4_sm2_freq0 = <0x0>;
  2072. sdc_tm4_sm2_freq1 = <0x0>;
  2073. sdc_tm4_sm3_freq0 = <0x5000000>;
  2074. sdc_tm4_sm3_freq1 = <0x405>;
  2075. sdc_tm4_sm4_freq0 = <0x50000>;
  2076. sdc_tm4_sm4_freq1 = <0x408>;
  2077. status = "disabled";
  2078. non-removable;
  2079. pinctrl-0 = <0xb4>;
  2080. cd-gpios;
  2081. sunxi-power-save-mode;
  2082. sunxi-dis-signal-vol-sw;
  2083. mmc-ddr-1_8v;
  2084. mmc-hs200-1_8v;
  2085. mmc-hs400-1_8v;
  2086. vmmc = "vcc-emmc";
  2087. vqmmc = "vcc-lpddr";
  2088. vdmmc = "none";
  2089. };
  2090.  
  2091. sdmmc@01c0f000 {
  2092. compatible = "allwinner,sun50i-sdmmc0";
  2093. device_type = "sdc0";
  2094. reg = <0x0 0x1c0f000 0x0 0x1000>;
  2095. interrupts = <0x0 0x3c 0x104>;
  2096. clocks = <0x6 0x5a 0x60 0x61 0x62>;
  2097. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2098. pinctrl-names = "default", "sleep";
  2099. pinctrl-1 = <0x64>;
  2100. max-frequency = <0x2faf080>;
  2101. bus-width = <0x4>;
  2102. broken-cd;
  2103. status = "okay";
  2104. pinctrl-0 = <0xb2>;
  2105. cd-gpios = <0x30 0x5 0x6 0x0 0x1 0x2 0xffffffff>;
  2106. sunxi-power-save-mode;
  2107. vmmc = "none";
  2108. vqmmc = "none";
  2109. vdmmc = "vcc-sdc";
  2110. };
  2111.  
  2112. sdmmc@1C10000 {
  2113. compatible = "allwinner,sun50i-sdmmc1";
  2114. device_type = "sdc1";
  2115. reg = <0x0 0x1c10000 0x0 0x1000>;
  2116. interrupts = <0x0 0x3d 0x104>;
  2117. clocks = <0x6 0x5a 0x65 0x66 0x67>;
  2118. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2119. pinctrl-names = "default", "sleep";
  2120. pinctrl-1 = <0x69>;
  2121. max-frequency = <0x8f0d180>;
  2122. bus-width = <0x4>;
  2123. sunxi-dly-52M-ddr4 = <0x1 0x0 0x0 0x0 0x2>;
  2124. sunxi-dly-104M = <0x1 0x0 0x0 0x0 0x1>;
  2125. sunxi-dly-208M = <0x1 0x0 0x0 0x0 0x1>;
  2126. status = "okay";
  2127. pinctrl-0 = <0xb3>;
  2128. sd-uhs-sdr50;
  2129. sd-uhs-ddr50;
  2130. sd-uhs-sdr104;
  2131. cap-sdio-irq;
  2132. keep-power-in-suspend;
  2133. ignore-pm-notify;
  2134. };
  2135.  
  2136. disp@01000000 {
  2137. fb_base = <0x47400000>;
  2138. boot_disp = <0x40a>;
  2139. compatible = "allwinner,sun50i-disp";
  2140. reg = <0x0 0x1000000 0x0 0x300000 0x0 0x1c0c000 0x0 0x17fc 0x0 0x1ca0000 0x0 0x10fc>;
  2141. interrupts = <0x0 0x56 0x104 0x0 0x57 0x104 0x0 0x59 0x104>;
  2142. clocks = <0x6a 0x6b 0x6c 0x6d 0x6e>;
  2143. status = "okay";
  2144. device_type = "disp";
  2145. disp_init_enable = <0x1>;
  2146. disp_mode = <0x0>;
  2147. screen0_output_type = <0x3>;
  2148. screen0_output_mode = <0xa>;
  2149. screen1_output_type = <0x3>;
  2150. screen1_output_mode = <0xa>;
  2151. fb0_format = <0x0>;
  2152. fb0_width = <0x0>;
  2153. fb0_height = <0x0>;
  2154. fb1_format = <0x0>;
  2155. fb1_width = <0x0>;
  2156. fb1_height = <0x0>;
  2157. };
  2158.  
  2159. lcd0@01c0c000 {
  2160. compatible = "allwinner,sunxi-lcd0";
  2161. pinctrl-names = "active", "sleep";
  2162. status = "okay";
  2163. device_type = "lcd0";
  2164. lcd_used = <0x0>;
  2165. lcd_driver_name = "mb709_mipi";
  2166. lcd_backlight = <0x32>;
  2167. lcd_if = <0x4>;
  2168. lcd_x = <0x400>;
  2169. lcd_y = <0x258>;
  2170. lcd_width = <0x0>;
  2171. lcd_height = <0x0>;
  2172. lcd_dclk_freq = <0x37>;
  2173. lcd_pwm_used = <0x1>;
  2174. lcd_pwm_ch = <0x10>;
  2175. lcd_pwm_freq = <0xc350>;
  2176. lcd_pwm_pol = <0x1>;
  2177. lcd_pwm_max_limit = <0xfa>;
  2178. lcd_hbp = <0x78>;
  2179. lcd_ht = <0x604>;
  2180. lcd_hspw = <0x14>;
  2181. lcd_vbp = <0x17>;
  2182. lcd_vt = <0x27b>;
  2183. lcd_vspw = <0x2>;
  2184. lcd_dsi_if = <0x2>;
  2185. lcd_dsi_lane = <0x4>;
  2186. lcd_dsi_format = <0x0>;
  2187. lcd_dsi_eotp = <0x0>;
  2188. lcd_dsi_vc = <0x0>;
  2189. lcd_dsi_te = <0x0>;
  2190. lcd_frm = <0x0>;
  2191. lcd_gamma_en = <0x0>;
  2192. lcd_bright_curve_en = <0x0>;
  2193. lcd_cmap_en = <0x0>;
  2194. lcd_bl_en = <0x30 0x7 0xa 0x1 0x0 0xffffffff 0x1>;
  2195. lcd_bl_en_power = "none";
  2196. lcd_power = "vcc-mipi";
  2197. lcd_fix_power = "vcc-dsi-33";
  2198. lcd_gpio_0 = <0x30 0x3 0x18 0x1 0x0 0xffffffff 0x1>;
  2199. };
  2200.  
  2201. hdmi@01ee0000 {
  2202. compatible = "allwinner,sunxi-hdmi";
  2203. reg = <0x0 0x1ee0000 0x0 0x20000>;
  2204. clocks = <0x6f 0x70>;
  2205. device_type = "hdmi";
  2206. status = "okay";
  2207. hdmi_power = "vcc-hdmi-33";
  2208. hdmi_hdcp_enable = <0x0>;
  2209. hdmi_cts_compatibility = <0x0>;
  2210. };
  2211.  
  2212. tr@01000000 {
  2213. compatible = "allwinner,sun50i-tr";
  2214. reg = <0x0 0x1000000 0x0 0x200bc>;
  2215. interrupts = <0x0 0x60 0x104>;
  2216. clocks = <0x6a>;
  2217. status = "okay";
  2218. };
  2219.  
  2220. pwm@01c21400 {
  2221. compatible = "allwinner,sunxi-pwm";
  2222. reg = <0x0 0x1c21400 0x0 0x3c>;
  2223. pwm-number = <0x1>;
  2224. pwm-base = <0x0>;
  2225. pwms = <0x71>;
  2226. };
  2227.  
  2228. pwm0@01c21400 {
  2229. compatible = "allwinner,sunxi-pwm0";
  2230. pinctrl-names = "active", "sleep";
  2231. reg_base = <0x1c21400>;
  2232. reg_busy_offset = <0x0>;
  2233. reg_busy_shift = <0x1c>;
  2234. reg_enable_offset = <0x0>;
  2235. reg_enable_shift = <0x4>;
  2236. reg_clk_gating_offset = <0x0>;
  2237. reg_clk_gating_shift = <0x6>;
  2238. reg_bypass_offset = <0x0>;
  2239. reg_bypass_shift = <0x9>;
  2240. reg_pulse_start_offset = <0x0>;
  2241. reg_pulse_start_shift = <0x8>;
  2242. reg_mode_offset = <0x0>;
  2243. reg_mode_shift = <0x7>;
  2244. reg_polarity_offset = <0x0>;
  2245. reg_polarity_shift = <0x5>;
  2246. reg_period_offset = <0x4>;
  2247. reg_period_shift = <0x10>;
  2248. reg_period_width = <0x10>;
  2249. reg_active_offset = <0x4>;
  2250. reg_active_shift = <0x0>;
  2251. reg_active_width = <0x10>;
  2252. reg_prescal_offset = <0x0>;
  2253. reg_prescal_shift = <0x0>;
  2254. reg_prescal_width = <0x4>;
  2255. linux,phandle = <0x71>;
  2256. phandle = <0x71>;
  2257. device_type = "pwm0";
  2258. pwm_used = <0x0>;
  2259. pinctrl-0 = <0xad>;
  2260. pinctrl-1 = <0xae>;
  2261. };
  2262.  
  2263. s_pwm@1f03800 {
  2264. compatible = "allwinner,sunxi-s_pwm";
  2265. reg = <0x0 0x1f03800 0x0 0x3c>;
  2266. pwm-number = <0x1>;
  2267. pwm-base = <0x10>;
  2268. pwms = <0x72>;
  2269. };
  2270.  
  2271. spwm0@0x01f03800 {
  2272. compatible = "allwinner,sunxi-pwm16";
  2273. pinctrl-names = "active", "sleep";
  2274. reg_base = <0x1f03800>;
  2275. reg_busy_offset = <0x0>;
  2276. reg_busy_shift = <0x1c>;
  2277. reg_enable_offset = <0x0>;
  2278. reg_enable_shift = <0x4>;
  2279. reg_clk_gating_offset = <0x0>;
  2280. reg_clk_gating_shift = <0x6>;
  2281. reg_bypass_offset = <0x0>;
  2282. reg_bypass_shift = <0x9>;
  2283. reg_pulse_start_offset = <0x0>;
  2284. reg_pulse_start_shift = <0x8>;
  2285. reg_mode_offset = <0x0>;
  2286. reg_mode_shift = <0x7>;
  2287. reg_polarity_offset = <0x0>;
  2288. reg_polarity_shift = <0x5>;
  2289. reg_period_offset = <0x4>;
  2290. reg_period_shift = <0x10>;
  2291. reg_period_width = <0x10>;
  2292. reg_active_offset = <0x4>;
  2293. reg_active_shift = <0x0>;
  2294. reg_active_width = <0x10>;
  2295. reg_prescal_offset = <0x0>;
  2296. reg_prescal_shift = <0x0>;
  2297. reg_prescal_width = <0x4>;
  2298. linux,phandle = <0x72>;
  2299. phandle = <0x72>;
  2300. device_type = "spwm0";
  2301. s_pwm_used = <0x1>;
  2302. pinctrl-0 = <0xaf>;
  2303. pinctrl-1 = <0xb0>;
  2304. };
  2305.  
  2306. boot_disp {
  2307. compatible = "allwinner,boot_disp";
  2308. device_type = "boot_disp";
  2309. output_disp = <0x0>;
  2310. output_type = <0x3>;
  2311. output_mode = <0xa>;
  2312. };
  2313.  
  2314. cci@0x01cb3000 {
  2315. compatible = "allwinner,sunxi-csi_cci";
  2316. reg = <0x0 0x1cb3000 0x0 0x1000>;
  2317. interrupts = <0x0 0x55 0x4>;
  2318. status = "okay";
  2319. };
  2320.  
  2321. csi_res@0x01cb0000 {
  2322. compatible = "allwinner,sunxi-csi";
  2323. reg = <0x0 0x1cb0000 0x0 0x1000>;
  2324. status = "okay";
  2325. };
  2326.  
  2327. vfe@0 {
  2328. device_type = "csi0";
  2329. compatible = "allwinner,sunxi-vfe";
  2330. interrupts = <0x0 0x54 0x4>;
  2331. clocks = <0x73 0x74 0x75 0x4 0x6 0x5>;
  2332. pinctrl-names = "default", "sleep";
  2333. pinctrl-1 = <0x77>;
  2334. csi0_sensor_list = <0x1>;
  2335. status = "okay";
  2336. pinctrl-0 = <0xb1>;
  2337. csi0_mck = <0x30 0x4 0x1 0x0 0x0 0x1 0x0>;
  2338.  
  2339. dev@0 {
  2340. csi0_dev0_mname = "hm5065";
  2341. csi0_dev0_twi_addr = <0x3e>;
  2342. csi0_dev0_pos = "rear";
  2343. csi0_dev0_isp_used = <0x1>;
  2344. csi0_dev0_fmt = <0x0>;
  2345. csi0_dev0_stby_mode = <0x1>;
  2346. csi0_dev0_vflip = <0x0>;
  2347. csi0_dev0_hflip = <0x0>;
  2348. csi0_dev0_iovdd = "iovdd-csi";
  2349. csi0_dev0_iovdd_vol = <0x2ab980>;
  2350. csi0_dev0_avdd = "avdd-csi";
  2351. csi0_dev0_avdd_vol = <0x2ab980>;
  2352. csi0_dev0_dvdd = "dvdd-csi-18";
  2353. csi0_dev0_dvdd_vol = <0x1b7740>;
  2354. csi0_dev0_flash_used = <0x0>;
  2355. csi0_dev0_flash_type = <0x2>;
  2356. csi0_dev0_flvdd = "vdd-csi-led";
  2357. csi0_dev0_flvdd_vol = <0x325aa0>;
  2358. csi0_dev0_act_used = <0x0>;
  2359. csi0_dev0_act_name = "ad5820_act";
  2360. csi0_dev0_act_slave = <0x18>;
  2361. status = "okay";
  2362. device_type = "csi0_dev0";
  2363. csi0_dev0_afvdd;
  2364. csi0_dev0_afvdd_vol;
  2365. csi0_dev0_power_en;
  2366. csi0_dev0_reset = <0x30 0x4 0xe 0x0 0x0 0x1 0x0>;
  2367. csi0_dev0_pwdn = <0x30 0x4 0xf 0x0 0x0 0x1 0x0>;
  2368. csi0_dev0_flash_en;
  2369. csi0_dev0_flash_mode;
  2370. csi0_dev0_af_pwdn;
  2371. };
  2372.  
  2373. dev@1 {
  2374. csi0_dev1_mname = "gc2145";
  2375. csi0_dev1_twi_addr = <0x78>;
  2376. csi0_dev1_pos = "front";
  2377. csi0_dev1_isp_used = <0x1>;
  2378. csi0_dev1_fmt = <0x0>;
  2379. csi0_dev1_stby_mode = <0x1>;
  2380. csi0_dev1_vflip = <0x0>;
  2381. csi0_dev1_hflip = <0x0>;
  2382. csi0_dev1_iovdd = "iovdd-csi";
  2383. csi0_dev1_iovdd_vol = <0x2ab980>;
  2384. csi0_dev1_avdd = "avdd-csi";
  2385. csi0_dev1_avdd_vol = <0x2ab980>;
  2386. csi0_dev1_dvdd = "dvdd-csi-18";
  2387. csi0_dev1_dvdd_vol = <0x1b7740>;
  2388. csi0_dev1_flash_used = <0x0>;
  2389. csi0_dev1_flash_type = <0x2>;
  2390. csi0_dev1_flvdd = "vdd-csi-led";
  2391. csi0_dev1_flvdd_vol = <0x325aa0>;
  2392. csi0_dev1_act_used = <0x0>;
  2393. csi0_dev1_act_name = "ad5820_act";
  2394. csi0_dev1_act_slave = <0x18>;
  2395. status = "okay";
  2396. device_type = "csi0_dev1";
  2397. csi0_dev1_afvdd;
  2398. csi0_dev1_afvdd_vol;
  2399. csi0_dev1_power_en;
  2400. csi0_dev1_reset = <0x30 0x4 0x10 0x0 0x0 0x1 0x0>;
  2401. csi0_dev1_pwdn = <0x30 0x4 0x11 0x0 0x0 0x1 0x0>;
  2402. csi0_dev1_flash_en;
  2403. csi0_dev1_flash_mode;
  2404. csi0_dev1_af_pwdn;
  2405. };
  2406. };
  2407.  
  2408. vdevice@0 {
  2409. compatible = "allwinner,sun50i-vdevice";
  2410. pinctrl-names = "default";
  2411. test-gpios = <0x79 0xb 0x0 0x1 0x2 0x3 0x4>;
  2412. status = "okay";
  2413. device_type = "Vdevice";
  2414. pinctrl-0 = <0xb9>;
  2415. };
  2416.  
  2417. ce@1c15000 {
  2418. compatible = "allwinner,sunxi-ce";
  2419. reg = <0x0 0x1c15000 0x0 0x80 0x0 0x1c15800 0x0 0x80>;
  2420. interrupts = <0x0 0x5e 0xff01 0x0 0x50 0xff01>;
  2421. clock-frequency = <0x11e1a300 0xbebc200>;
  2422. clocks = <0x7a 0x7b>;
  2423. };
  2424.  
  2425. deinterlace@0x01e00000 {
  2426. #address-cells = <0x1>;
  2427. #size-cells = <0x0>;
  2428. compatible = "allwinner,sunxi-deinterlace";
  2429. reg = <0x0 0x1e00000 0x0 0x77c>;
  2430. interrupts = <0x0 0x5d 0x4>;
  2431. clocks = <0x7c 0x4>;
  2432. status = "okay";
  2433. device_type = "di";
  2434. };
  2435.  
  2436. smartcard@0x01c2c400 {
  2437. #address-cells = <0x1>;
  2438. #size-cells = <0x0>;
  2439. compatible = "allwinner,sunxi-scr";
  2440. reg = <0x0 0x1c2c400 0x0 0x100>;
  2441. interrupts = <0x0 0x53 0x4>;
  2442. clocks = <0x7d 0x7e>;
  2443. clock-frequency = <0x16e3600>;
  2444. pinctrl-names = "default";
  2445. pinctrl-0 = <0x7f>;
  2446. status = "okay";
  2447. device_type = "smc";
  2448. smc_used;
  2449. smc_rst;
  2450. smc_vppen;
  2451. smc_vppp;
  2452. smc_det;
  2453. smc_vccen;
  2454. smc_sck;
  2455. smc_sda;
  2456. };
  2457.  
  2458. nmi@0x01f00c00 {
  2459. #address-cells = <0x1>;
  2460. #size-cells = <0x0>;
  2461. compatible = "allwinner,sunxi-nmi";
  2462. reg = <0x0 0x1f00c00 0x0 0x50>;
  2463. nmi_irq_ctrl = <0xc>;
  2464. nmi_irq_en = <0x40>;
  2465. nmi_irq_status = <0x10>;
  2466. nmi_irq_mask = <0x50>;
  2467. status = "okay";
  2468. };
  2469.  
  2470. pmu0@0 {
  2471. compatible = "allwinner,pmu0";
  2472. device_type = "pmu0";
  2473. pmu_batdeten = <0x1>;
  2474. pmu_init_chgend_rate = <0x14>;
  2475. pmu_init_chg_enabled = <0x1>;
  2476. pmu_init_adc_freq = <0x320>;
  2477. pmu_init_adcts_freq = <0x320>;
  2478. pmu_init_chg_pretime = <0x46>;
  2479. pmu_init_chg_csttime = <0x2d0>;
  2480. pmu_batt_cap_correct = <0x1>;
  2481. pmu_chg_end_on_en = <0x0>;
  2482. pmu_pwroff_vol = <0xce4>;
  2483. pmu_pwron_vol = <0xa28>;
  2484. pmu_powkey_off_delay_time = <0x0>;
  2485. pmu_pwrok_time = <0x40>;
  2486. pmu_reset_shutdown_en = <0x1>;
  2487. pmu_restvol_adjust_time = <0x3c>;
  2488. pmu_ocv_cou_adjust_time = <0x3c>;
  2489. pmu_vbusen_func = <0x1>;
  2490. pmu_reset = <0x0>;
  2491. pmu_IRQ_wakeup = <0x1>;
  2492. pmu_hot_shutdowm = <0x1>;
  2493. pmu_inshort = <0x0>;
  2494. pmu_bat_shutdown_ltf = <0xc80>;
  2495. pmu_bat_shutdown_htf = <0xed>;
  2496. status = "okay";
  2497. pmu_id = <0x6>;
  2498. pmu_twi_addr = <0x34>;
  2499. pmu_twi_id = <0x1>;
  2500. pmu_irq_id = <0x40>;
  2501. pmu_chg_ic_temp = <0x0>;
  2502. pmu_battery_rdc = <0x58>;
  2503. pmu_battery_cap = <0x12c0>;
  2504. pmu_runtime_chgcur = <0x1c2>;
  2505. pmu_suspend_chgcur = <0x5dc>;
  2506. pmu_shutdown_chgcur = <0x5dc>;
  2507. pmu_init_chgvol = <0x1068>;
  2508. pmu_ac_vol = <0xfa0>;
  2509. pmu_ac_cur = <0xdac>;
  2510. pmu_usbpc_vol = <0x1130>;
  2511. pmu_usbpc_cur = <0x1f4>;
  2512. pmu_battery_warning_level1 = <0xf>;
  2513. pmu_battery_warning_level2 = <0x0>;
  2514. pmu_chgled_func = <0x0>;
  2515. pmu_chgled_type = <0x0>;
  2516. pmu_bat_para1 = <0x0>;
  2517. pmu_bat_para2 = <0x0>;
  2518. pmu_bat_para3 = <0x0>;
  2519. pmu_bat_para4 = <0x0>;
  2520. pmu_bat_para5 = <0x0>;
  2521. pmu_bat_para6 = <0x0>;
  2522. pmu_bat_para7 = <0x1>;
  2523. pmu_bat_para8 = <0x1>;
  2524. pmu_bat_para9 = <0x2>;
  2525. pmu_bat_para10 = <0x3>;
  2526. pmu_bat_para11 = <0x4>;
  2527. pmu_bat_para12 = <0xa>;
  2528. pmu_bat_para13 = <0x11>;
  2529. pmu_bat_para14 = <0x1a>;
  2530. pmu_bat_para15 = <0x29>;
  2531. pmu_bat_para16 = <0x2e>;
  2532. pmu_bat_para17 = <0x33>;
  2533. pmu_bat_para18 = <0x38>;
  2534. pmu_bat_para19 = <0x3b>;
  2535. pmu_bat_para20 = <0x41>;
  2536. pmu_bat_para21 = <0x45>;
  2537. pmu_bat_para22 = <0x4b>;
  2538. pmu_bat_para23 = <0x4f>;
  2539. pmu_bat_para24 = <0x53>;
  2540. pmu_bat_para25 = <0x59>;
  2541. pmu_bat_para26 = <0x5f>;
  2542. pmu_bat_para27 = <0x62>;
  2543. pmu_bat_para28 = <0x64>;
  2544. pmu_bat_para29 = <0x64>;
  2545. pmu_bat_para30 = <0x64>;
  2546. pmu_bat_para31 = <0x64>;
  2547. pmu_bat_para32 = <0x64>;
  2548. pmu_bat_temp_enable = <0x1>;
  2549. pmu_bat_charge_ltf = <0x8d5>;
  2550. pmu_bat_charge_htf = <0x184>;
  2551. pmu_bat_temp_para1 = <0x1d2a>;
  2552. pmu_bat_temp_para2 = <0x1180>;
  2553. pmu_bat_temp_para3 = <0xdbe>;
  2554. pmu_bat_temp_para4 = <0xae2>;
  2555. pmu_bat_temp_para5 = <0x8af>;
  2556. pmu_bat_temp_para6 = <0x6fc>;
  2557. pmu_bat_temp_para7 = <0x5a8>;
  2558. pmu_bat_temp_para8 = <0x3c9>;
  2559. pmu_bat_temp_para9 = <0x298>;
  2560. pmu_bat_temp_para10 = <0x1d2>;
  2561. pmu_bat_temp_para11 = <0x189>;
  2562. pmu_bat_temp_para12 = <0x14d>;
  2563. pmu_bat_temp_para13 = <0x11b>;
  2564. pmu_bat_temp_para14 = <0xf2>;
  2565. pmu_bat_temp_para15 = <0xb3>;
  2566. pmu_bat_temp_para16 = <0x86>;
  2567. pmu_powkey_off_time = <0x1770>;
  2568. pmu_powkey_off_func = <0x0>;
  2569. pmu_powkey_off_en = <0x1>;
  2570. pmu_powkey_long_time = <0x5dc>;
  2571. pmu_powkey_on_time = <0x3e8>;
  2572. power_start = <0x0>;
  2573. };
  2574.  
  2575. regu@0 {
  2576. compatible = "allwinner,pmu0_regu";
  2577. regulator_count = <0x17>;
  2578. status = "okay";
  2579. device_type = "pmu0_regu";
  2580. regulator1 = "axp81x_dcdc1 none vcc-nand vcc-emmc vcc-sdc vcc-usb-30 vcc-io vcc-pd";
  2581. regulator2 = "axp81x_dcdc2 none vdd-cpua";
  2582. regulator3 = "axp81x_dcdc3 none";
  2583. regulator4 = "axp81x_dcdc4 none";
  2584. regulator5 = "axp81x_dcdc5 none vcc-dram";
  2585. regulator6 = "axp81x_dcdc6 none vdd-sys";
  2586. regulator7 = "axp81x_dcdc7 none";
  2587. regulator8 = "axp81x_rtc none";
  2588. regulator9 = "axp81x_aldo1 none vdd-csi-led iovdd-csi vcc-pe";
  2589. regulator10 = "axp81x_aldo2 none vcc-pl";
  2590. regulator11 = "axp81x_aldo3 none vcc-avcc vcc-pll";
  2591. regulator12 = "axp81x_dldo1 none vcc-hdmi-33";
  2592. regulator13 = "axp81x_dldo2 none vcc-mipi";
  2593. regulator14 = "axp81x_dldo3 none avdd-csi";
  2594. regulator15 = "axp81x_dldo4 none vcc-deviceio";
  2595. regulator16 = "axp81x_eldo1 none vcc-cpvdd vcc-wifi-io vcc-pc vcc-pg";
  2596. regulator17 = "axp81x_eldo2 none vcc-lcd-0";
  2597. regulator18 = "axp81x_eldo3 none dvdd-csi-18";
  2598. regulator19 = "axp81x_fldo1 none vcc-hsic-12";
  2599. regulator20 = "axp81x_fldo2 none vdd-cpus";
  2600. regulator21 = "axp81x_gpio0ldo none vcc-ctp";
  2601. regulator22 = "axp81x_gpio1ldo none";
  2602. regulator23 = "axp81x_dc1sw none vcc-lvds vcc-dsi-33";
  2603. };
  2604.  
  2605. nand0@01c03000 {
  2606. compatible = "allwinner,sun50i-nand";
  2607. device_type = "nand0";
  2608. reg = <0x0 0x1c03000 0x0 0x1000>;
  2609. interrupts = <0x0 0x46 0x4>;
  2610. clocks = <0x4 0x80>;
  2611. pinctrl-names = "default", "sleep";
  2612. pinctrl-1 = <0x83>;
  2613. nand0_regulator1 = "vcc-nand";
  2614. nand0_regulator2 = "none";
  2615. nand0_cache_level = <0x55aaaa55>;
  2616. nand0_flush_cache_num = <0x55aaaa55>;
  2617. nand0_capacity_level = <0x55aaaa55>;
  2618. nand0_id_number_ctl = <0x55aaaa55>;
  2619. nand0_print_level = <0x55aaaa55>;
  2620. nand0_p0 = <0x55aaaa55>;
  2621. nand0_p1 = <0x55aaaa55>;
  2622. nand0_p2 = <0x55aaaa55>;
  2623. nand0_p3 = <0x55aaaa55>;
  2624. status = "disabled";
  2625. nand0_support_2ch = <0x0>;
  2626. pinctrl-0 = <0xab 0xac>;
  2627. };
  2628.  
  2629. thermal_sensor {
  2630. compatible = "allwinner,thermal_sensor";
  2631. reg = <0x0 0x1c25000 0x0 0x400>;
  2632. interrupts = <0x0 0x1f 0x0>;
  2633. clocks = <0x6 0x84>;
  2634. sensor_num = <0x3>;
  2635. shut_temp = <0x78>;
  2636. status = "okay";
  2637.  
  2638. combine0 {
  2639. #thermal-sensor-cells = <0x1>;
  2640. combine_cnt = <0x3>;
  2641. combine_type = "max";
  2642. combine_chn = <0x0 0x1 0x2>;
  2643. linux,phandle = <0x85>;
  2644. phandle = <0x85>;
  2645. };
  2646. };
  2647.  
  2648. cpu_budget_cool {
  2649. compatible = "allwinner,budget_cooling";
  2650. #cooling-cells = <0x2>;
  2651. status = "okay";
  2652. state_cnt = <0x7>;
  2653. cluster_num = <0x1>;
  2654. state0 = <0x177000 0x4>;
  2655. state1 = <0x15F900 0x4>;
  2656. state2 = <0x148200 0x4>;
  2657. state3 = <0x124f80 0x4>;
  2658. state4 = <0x119400 0x4>;
  2659. state5 = <0x10d880 0x2>;
  2660. state6 = <0x10d880 0x1>;
  2661. linux,phandle = <0x87>;
  2662. phandle = <0x87>;
  2663. };
  2664.  
  2665. gpu_cooling {
  2666. compatible = "allwinner,gpu_cooling";
  2667. reg = <0x0 0x0 0x0 0x0>;
  2668. #cooling-cells = <0x2>;
  2669. status = "okay";
  2670. state_cnt = <0x3>;
  2671. state0 = <0x0>;
  2672. state1 = <0x168>;
  2673. state2 = <0x90>;
  2674. linux,phandle = <0x8c>;
  2675. phandle = <0x8c>;
  2676. };
  2677.  
  2678. thermal-zones {
  2679.  
  2680. soc_thermal {
  2681. polling-delay-passive = <0x1f4>;
  2682. polling-delay = <0x7d0>;
  2683. thermal-sensors = <0x85 0x0>;
  2684.  
  2685. trips {
  2686.  
  2687. t0 {
  2688. temperature = <0x41>;
  2689. type = "passive";
  2690. hysteresis = <0x0>;
  2691. linux,phandle = <0x86>;
  2692. phandle = <0x86>;
  2693. };
  2694.  
  2695. t1 {
  2696. temperature = <0x50>;
  2697. type = "passive";
  2698. hysteresis = <0x0>;
  2699. linux,phandle = <0x88>;
  2700. phandle = <0x88>;
  2701. };
  2702.  
  2703. t2 {
  2704. temperature = <0x5a>;
  2705. type = "passive";
  2706. hysteresis = <0x0>;
  2707. linux,phandle = <0x89>;
  2708. phandle = <0x89>;
  2709. };
  2710.  
  2711. t3 {
  2712. temperature = <0x64>;
  2713. type = "passive";
  2714. hysteresis = <0x0>;
  2715. linux,phandle = <0x8a>;
  2716. phandle = <0x8a>;
  2717. };
  2718.  
  2719. t4 {
  2720. temperature = <0x55>;
  2721. type = "passive";
  2722. hysteresis = <0x0>;
  2723. linux,phandle = <0x8b>;
  2724. phandle = <0x8b>;
  2725. };
  2726.  
  2727. t5 {
  2728. temperature = <0x5f>;
  2729. type = "passive";
  2730. hysteresis = <0x0>;
  2731. linux,phandle = <0x8d>;
  2732. phandle = <0x8d>;
  2733. };
  2734.  
  2735. t6 {
  2736. temperature = <0x6e>;
  2737. type = "critical";
  2738. hysteresis = <0x0>;
  2739. };
  2740. };
  2741.  
  2742. cooling-maps {
  2743.  
  2744. bind0 {
  2745. contribution = <0x0>;
  2746. trip = <0x86>;
  2747. cooling-device = <0x87 0x1 0x1>;
  2748. };
  2749.  
  2750. bind1 {
  2751. contribution = <0x0>;
  2752. trip = <0x88>;
  2753. cooling-device = <0x87 0x2 0x2>;
  2754. };
  2755.  
  2756. bind2 {
  2757. contribution = <0x0>;
  2758. trip = <0x89>;
  2759. cooling-device = <0x87 0x3 0x4>;
  2760. };
  2761.  
  2762. bind3 {
  2763. contribution = <0x0>;
  2764. trip = <0x8a>;
  2765. cooling-device = <0x87 0x5 0x6>;
  2766. };
  2767.  
  2768. bind4 {
  2769. contribution = <0x0>;
  2770. trip = <0x8b>;
  2771. cooling-device = <0x8c 0x1 0x1>;
  2772. };
  2773.  
  2774. bind5 {
  2775. contribution = <0x0>;
  2776. trip = <0x8d>;
  2777. cooling-device = <0x8c 0x2 0x2>;
  2778. };
  2779. };
  2780. };
  2781. };
  2782.  
  2783. keyboard {
  2784. compatible = "allwinner,keyboard_2000mv";
  2785. reg = <0x0 0x1c21800 0x0 0x400>;
  2786. interrupts = <0x0 0x1e 0x0>;
  2787. status = "okay";
  2788. key_cnt = <0x5>;
  2789. key1 = <0xf0 0x73>;
  2790. key2 = <0x1f4 0x72>;
  2791. key3 = <0x2bc 0x8b>;
  2792. key4 = <0x37a 0x1c>;
  2793. key5 = <0x7d0 0x66>;
  2794. };
  2795.  
  2796. eth@01c30000 {
  2797. compatible = "allwinner,sunxi-gmac";
  2798. reg = <0x0 0x1c30000 0x0 0x40000 0x0 0x1c00000 0x0 0x30>;
  2799. pinctrl-names = "default";
  2800. interrupts = <0x0 0x52 0x4>;
  2801. interrupt-names = "gmacirq";
  2802. clocks = <0x8f>;
  2803. clock-names = "gmac";
  2804. phy-mode = "rgmii";
  2805. tx-delay = <0x3>;
  2806. rx-delay = <0x0>;
  2807. gmac_power1 = "axp81x_dc1sw:0";
  2808. status = "okay";
  2809. device_type = "gmac0";
  2810. pinctrl-0 = <0x9e>;
  2811. gmac_power2;
  2812. gmac_power3;
  2813. };
  2814.  
  2815. product {
  2816. device_type = "product";
  2817. version = "100";
  2818. machine = "evb";
  2819. };
  2820.  
  2821. platform {
  2822. device_type = "platform";
  2823. eraseflag = <0x1>;
  2824. };
  2825.  
  2826. target {
  2827. device_type = "target";
  2828. boot_clock = <0x3f0>;
  2829. storage_type = <0xffffffff>;
  2830. burn_key = <0x0>;
  2831. };
  2832.  
  2833. power_sply {
  2834. device_type = "power_sply";
  2835. dcdc1_vol = <0xf4f24>;
  2836. dcdc2_vol = <0xf468c>;
  2837. dcdc6_vol = <0xf468c>;
  2838. aldo1_vol = <0xaf0>;
  2839. aldo2_vol = <0xf4948>;
  2840. aldo3_vol = <0xf4df8>;
  2841. dldo1_vol = <0xce4>;
  2842. dldo2_vol = <0xce4>;
  2843. dldo3_vol = <0xaf0>;
  2844. dldo4_vol = <0xf4f24>;
  2845. eldo1_vol = <0xf4948>;
  2846. eldo2_vol = <0x708>;
  2847. eldo3_vol = <0x708>;
  2848. fldo1_vol = <0x4b0>;
  2849. fldo2_vol = <0xf468c>;
  2850. gpio0_vol = <0xc1c>;
  2851. };
  2852.  
  2853. card_boot {
  2854. device_type = "card_boot";
  2855. logical_start = <0xa000>;
  2856. sprite_gpio0;
  2857. };
  2858.  
  2859. pm_para {
  2860. device_type = "pm_para";
  2861. standby_mode = <0x1>;
  2862. };
  2863.  
  2864. card0_boot_para {
  2865. device_type = "card0_boot_para";
  2866. card_ctrl = <0x0>;
  2867. card_high_speed = <0x1>;
  2868. card_line = <0x4>;
  2869. pinctrl-0 = <0x99>;
  2870. };
  2871.  
  2872. card2_boot_para {
  2873. device_type = "card2_boot_para";
  2874. sdc_io_1v8 = <0x1>;
  2875. card_ctrl = <0x2>;
  2876. card_high_speed = <0x1>;
  2877. card_line = <0x8>;
  2878. pinctrl-0 = <0x9a>;
  2879. sdc_ex_dly_used = <0x2>;
  2880. };
  2881.  
  2882. twi_para {
  2883. device_type = "twi_para";
  2884. twi_port = <0x0>;
  2885. pinctrl-0 = <0x9b>;
  2886. };
  2887.  
  2888. uart_para {
  2889. device_type = "uart_para";
  2890. uart_debug_port = <0x0>;
  2891. pinctrl-0 = <0x9c>;
  2892. };
  2893.  
  2894. jtag_para {
  2895. device_type = "jtag_para";
  2896. jtag_enable = <0x1>;
  2897. pinctrl-0 = <0x9d>;
  2898. };
  2899.  
  2900. clock {
  2901. device_type = "clock";
  2902. pll4 = <0x12c>;
  2903. pll6 = <0x258>;
  2904. pll8 = <0x168>;
  2905. pll9 = <0x129>;
  2906. pll10 = <0x108>;
  2907. };
  2908.  
  2909. rtp_para {
  2910. device_type = "rtp_para";
  2911. rtp_used = <0x0>;
  2912. rtp_screen_size = <0x5>;
  2913. rtp_regidity_level = <0x5>;
  2914. rtp_press_threshold_enable = <0x0>;
  2915. rtp_press_threshold = <0x1f40>;
  2916. rtp_sensitive_level = <0xf>;
  2917. rtp_exchange_x_y_flag = <0x0>;
  2918. };
  2919.  
  2920. ctp {
  2921. device_type = "ctp";
  2922. compatible = "allwinner,sun50i-ctp-para";
  2923. status = "disabled";
  2924. ctp_name = "gt911_DB";
  2925. ctp_twi_id = <0x0>;
  2926. ctp_twi_addr = <0x40>;
  2927. ctp_screen_max_x = <0x400>;
  2928. ctp_screen_max_y = <0x258>;
  2929. ctp_revert_x_flag = <0x1>;
  2930. ctp_revert_y_flag = <0x1>;
  2931. ctp_exchange_x_y_flag = <0x0>;
  2932. ctp_int_port = <0x30 0x7 0x4 0x6 0xffffffff 0xffffffff 0xffffffff>;
  2933. ctp_wakeup = <0x30 0x7 0xb 0x1 0xffffffff 0xffffffff 0x1>;
  2934. ctp_power_ldo = "vcc-ctp";
  2935. ctp_power_ldo_vol = <0xce4>;
  2936. ctp_power_io;
  2937. };
  2938.  
  2939. ctp_list {
  2940. device_type = "ctp_list";
  2941. compatible = "allwinner,sun50i-ctp-list";
  2942. status = "okay";
  2943. gslX680new = <0x1>;
  2944. gt9xx_ts = <0x0>;
  2945. gt9xxf_ts = <0x1>;
  2946. gt9xxnew_ts = <0x0>;
  2947. gt82x = <0x1>;
  2948. zet622x = <0x1>;
  2949. aw5306_ts = <0x1>;
  2950. };
  2951.  
  2952. tkey_para {
  2953. device_type = "tkey_para";
  2954. tkey_used = <0x0>;
  2955. tkey_twi_id;
  2956. tkey_twi_addr;
  2957. tkey_int;
  2958. };
  2959.  
  2960. motor_para {
  2961. device_type = "motor_para";
  2962. motor_used = <0x0>;
  2963. motor_shake = <0x31 0xfffe 0x3 0x1 0xffffffff 0xffffffff 0x1>;
  2964. };
  2965.  
  2966. tvout_para {
  2967. device_type = "tvout_para";
  2968. tvout_used;
  2969. tvout_channel_num;
  2970. tv_en;
  2971. };
  2972.  
  2973. tvin_para {
  2974. device_type = "tvin_para";
  2975. tvin_used;
  2976. tvin_channel_num;
  2977. };
  2978.  
  2979. serial_feature {
  2980. device_type = "serial_feature";
  2981. sn_filename = "sn.txt";
  2982. };
  2983.  
  2984. gsensor {
  2985. device_type = "gsensor";
  2986. compatible = "allwinner,sun50i-gsensor-para";
  2987. status = "okay";
  2988. gsensor_twi_id = <0x1>;
  2989. gsensor_twi_addr = <0x1d>;
  2990. gsensor_vcc_io = "vcc-deviceio";
  2991. gsensor_vcc_io_val = <0xce4>;
  2992. gsensor_int1 = <0x30 0x7 0x5 0x6 0x1 0xffffffff 0xffffffff>;
  2993. gsensor_int2 = <0x30 0x7 0x6 0x6 0x1 0xffffffff 0xffffffff>;
  2994. };
  2995.  
  2996. gsensor_list {
  2997. device_type = "gsensor_list";
  2998. compatible = "allwinner,sun50i-gsensor-list-para";
  2999. gsensor_list__used = <0x1>;
  3000. lsm9ds0_acc_mag = <0x1>;
  3001. bma250 = <0x1>;
  3002. mma8452 = <0x1>;
  3003. mma7660 = <0x1>;
  3004. mma865x = <0x1>;
  3005. afa750 = <0x1>;
  3006. lis3de_acc = <0x1>;
  3007. lis3dh_acc = <0x1>;
  3008. kxtik = <0x1>;
  3009. dmard10 = <0x0>;
  3010. dmard06 = <0x1>;
  3011. mxc622x = <0x1>;
  3012. fxos8700 = <0x1>;
  3013. lsm303d = <0x0>;
  3014. sc7a30 = <0x1>;
  3015. };
  3016.  
  3017. 3g_para {
  3018. device_type = "3g_para";
  3019. 3g_used = <0x0>;
  3020. 3g_usbc_num = <0x2>;
  3021. 3g_uart_num = <0x0>;
  3022. bb_vbat = <0x79 0xb 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  3023. bb_host_wake = <0x79 0xc 0x0 0x1 0xffffffff 0xffffffff 0x0>;
  3024. bb_on = <0x79 0xc 0x1 0x1 0xffffffff 0xffffffff 0x0>;
  3025. bb_pwr_on = <0x79 0xc 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  3026. bb_wake = <0x79 0xc 0x4 0x1 0xffffffff 0xffffffff 0x0>;
  3027. bb_rf_dis = <0x79 0xc 0x5 0x1 0xffffffff 0xffffffff 0x0>;
  3028. bb_rst = <0x79 0xc 0x6 0x1 0xffffffff 0xffffffff 0x0>;
  3029. 3g_int;
  3030. };
  3031.  
  3032. gyroscopesensor {
  3033. device_type = "gyroscopesensor";
  3034. compatible = "allwinner,sun50i-gyr_sensors-para";
  3035. status = "disabled";
  3036. gy_twi_id = <0x2>;
  3037. gy_twi_addr = <0x6a>;
  3038. gy_int1 = <0x30 0x0 0xa 0x6 0x1 0xffffffff 0xffffffff>;
  3039. gy_int2;
  3040. };
  3041.  
  3042. gy_list {
  3043. device_type = "gy_list";
  3044. compatible = "allwinner,sun50i-gyr_sensors-list-para";
  3045. status = "disabled";
  3046. lsm9ds0_gyr = <0x1>;
  3047. l3gd20_gyr = <0x0>;
  3048. bmg160_gyr = <0x1>;
  3049. };
  3050.  
  3051. lightsensor {
  3052. device_type = "lightsensor";
  3053. compatible = "allwinner,sun50i-lsensors-para";
  3054. status = "disabled";
  3055. ls_twi_id = <0x2>;
  3056. ls_twi_addr = <0x23>;
  3057. ls_int = <0x30 0x0 0xc 0x6 0x1 0xffffffff 0xffffffff>;
  3058. };
  3059.  
  3060. ls_list {
  3061. device_type = "ls_list";
  3062. compatible = "allwinner,sun50i-lsensors-list-para";
  3063. status = "disabled";
  3064. ltr_501als = <0x1>;
  3065. jsa1212 = <0x0>;
  3066. jsa1127 = <0x1>;
  3067. stk3x1x = <0x0>;
  3068. };
  3069.  
  3070. compasssensor {
  3071. device_type = "compasssensor";
  3072. compatible = "allwinner,sun50i-compass-para";
  3073. status = "disabled";
  3074. compass_twi_id = <0x2>;
  3075. compass_twi_addr = <0xd>;
  3076. compass_int = <0x30 0x0 0xb 0x6 0x1 0xffffffff 0xffffffff>;
  3077. };
  3078.  
  3079. compass_list {
  3080. device_type = "compass_list";
  3081. compatible = "allwinner,sun50i-compass-list-para";
  3082. status = "disabled";
  3083. lsm9ds0 = <0x1>;
  3084. lsm303d = <0x0>;
  3085. };
  3086.  
  3087. recovery_key {
  3088. device_type = "recovery_key";
  3089. key_max = <0xc>;
  3090. key_min = <0xa>;
  3091. };
  3092.  
  3093. fastboot_key {
  3094. device_type = "fastboot_key";
  3095. key_max = <0x6>;
  3096. key_min = <0x4>;
  3097. };
  3098. };
  3099.  
  3100. aliases {
  3101. serial0 = "/soc@01c00000/uart@01c28000";
  3102. serial1 = "/soc@01c00000/uart@01c28400";
  3103. serial2 = "/soc@01c00000/uart@01c28800";
  3104. serial3 = "/soc@01c00000/uart@01c28c00";
  3105. serial4 = "/soc@01c00000/uart@01c29000";
  3106. twi0 = "/soc@01c00000/twi@0x01c2ac00";
  3107. twi1 = "/soc@01c00000/twi@0x01c2b000";
  3108. twi2 = "/soc@01c00000/twi@0x01c2b400";
  3109. spi0 = "/soc@01c00000/spi@01c68000";
  3110. spi1 = "/soc@01c00000/spi@01c69000";
  3111. global_timer0 = "/soc@01c00000/timer@1c20c00";
  3112. cci0 = "/soc@01c00000/cci@0x01cb3000";
  3113. csi_res0 = "/soc@01c00000/csi_res@0x01cb0000";
  3114. vfe0 = "/soc@01c00000/vfe@0";
  3115. mmc0 = "/soc@01c00000/sdmmc@01c0f000";
  3116. mmc2 = "/soc@01c00000/sdmmc@01C11000";
  3117. nand0 = "/soc@01c00000/nand0@01c03000";
  3118. disp = "/soc@01c00000/disp@01000000";
  3119. lcd0 = "/soc@01c00000/lcd0@01c0c000";
  3120. hdmi = "/soc@01c00000/hdmi@01ee0000";
  3121. pwm = "/soc@01c00000/pwm@01c21400";
  3122. pwm0 = "/soc@01c00000/pwm0@01c21400";
  3123. s_pwm = "/soc@01c00000/s_pwm@1f03800";
  3124. spwm0 = "/soc@01c00000/spwm0@0x01f03800";
  3125. boot_disp = "/soc@01c00000/boot_disp";
  3126. };
  3127.  
  3128. chosen {
  3129. bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
  3130. linux,initrd-start = <0x0 0x0>;
  3131. linux,initrd-end = <0x0 0x0>;
  3132. };
  3133.  
  3134. cpus {
  3135. #address-cells = <0x2>;
  3136. #size-cells = <0x0>;
  3137.  
  3138. cpu@0 {
  3139. device_type = "cpu";
  3140. compatible = "arm,cortex-a53", "arm,armv8";
  3141. reg = <0x0 0x0>;
  3142. enable-method = "psci";
  3143. cpufreq_tbl = <0x75300 0x927c0 0xafc80 0xc7380 0xf6180 0x10d880 0x119400 0x124f80 0x148200>;
  3144. clock-latency = <0x1e8480>;
  3145. clock-frequency = <0x3c14dc00>;
  3146. cpu-idle-states = <0x90 0x91 0x92>;
  3147. };
  3148.  
  3149. cpu@1 {
  3150. device_type = "cpu";
  3151. compatible = "arm,cortex-a53", "arm,armv8";
  3152. reg = <0x0 0x1>;
  3153. enable-method = "psci";
  3154. clock-frequency = <0x3c14dc00>;
  3155. cpu-idle-states = <0x90 0x91 0x92>;
  3156. };
  3157.  
  3158. cpu@2 {
  3159. device_type = "cpu";
  3160. compatible = "arm,cortex-a53", "arm,armv8";
  3161. reg = <0x0 0x2>;
  3162. enable-method = "psci";
  3163. clock-frequency = <0x3c14dc00>;
  3164. cpu-idle-states = <0x90 0x91 0x92>;
  3165. };
  3166.  
  3167. cpu@3 {
  3168. device_type = "cpu";
  3169. compatible = "arm,cortex-a53", "arm,armv8";
  3170. reg = <0x0 0x3>;
  3171. enable-method = "psci";
  3172. clock-frequency = <0x3c14dc00>;
  3173. cpu-idle-states = <0x90 0x91 0x92>;
  3174. };
  3175.  
  3176. idle-states {
  3177. entry-method = "arm,psci";
  3178.  
  3179. cpu-sleep-0 {
  3180. compatible = "arm,idle-state";
  3181. arm,psci-suspend-param = <0x10000>;
  3182. entry-latency-us = <0x28>;
  3183. exit-latency-us = <0x64>;
  3184. min-residency-us = <0x96>;
  3185. linux,phandle = <0x90>;
  3186. phandle = <0x90>;
  3187. };
  3188.  
  3189. cluster-sleep-0 {
  3190. compatible = "arm,idle-state";
  3191. arm,psci-suspend-param = <0x1010000>;
  3192. entry-latency-us = <0x1f4>;
  3193. exit-latency-us = <0x3e8>;
  3194. min-residency-us = <0x9c4>;
  3195. linux,phandle = <0x91>;
  3196. phandle = <0x91>;
  3197. };
  3198.  
  3199. sys-sleep-0 {
  3200. compatible = "arm,idle-state";
  3201. arm,psci-suspend-param = <0x2010000>;
  3202. entry-latency-us = <0x3e8>;
  3203. exit-latency-us = <0x7d0>;
  3204. min-residency-us = <0x1194>;
  3205. linux,phandle = <0x92>;
  3206. phandle = <0x92>;
  3207. };
  3208. };
  3209. };
  3210.  
  3211. psci {
  3212. compatible = "arm,psci-0.2";
  3213. method = "smc";
  3214. psci_version = <0x84000000>;
  3215. cpu_suspend = <0xc4000001>;
  3216. cpu_off = <0x84000002>;
  3217. cpu_on = <0xc4000003>;
  3218. affinity_info = <0xc4000004>;
  3219. migrate = <0xc4000005>;
  3220. migrate_info_type = <0x84000006>;
  3221. migrate_info_up_cpu = <0xc4000007>;
  3222. system_off = <0x84000008>;
  3223. system_reset = <0x84000009>;
  3224. };
  3225.  
  3226. n_brom {
  3227. compatible = "allwinner,n-brom";
  3228. reg = <0x0 0x0 0x0 0xc000>;
  3229. };
  3230.  
  3231. s_brom {
  3232. compatible = "allwinner,s-brom";
  3233. reg = <0x0 0x0 0x0 0x10000>;
  3234. };
  3235.  
  3236. sram_a1 {
  3237. compatible = "allwinner,sram_a1";
  3238. reg = <0x0 0x10000 0x0 0x8000>;
  3239. };
  3240.  
  3241. sram_a2 {
  3242. compatible = "allwinner,sram_a2";
  3243. reg = <0x0 0x40000 0x0 0x14000>;
  3244. };
  3245.  
  3246. prcm {
  3247. compatible = "allwinner,prcm";
  3248. reg = <0x0 0x1f01400 0x0 0x400>;
  3249. };
  3250.  
  3251. cpuscfg {
  3252. compatible = "allwinner,cpuscfg";
  3253. reg = <0x0 0x1f01c00 0x0 0x400>;
  3254. };
  3255.  
  3256. ion {
  3257. compatible = "allwinner,sunxi-ion";
  3258.  
  3259. system_contig {
  3260. type = <0x1>;
  3261. };
  3262.  
  3263. cma {
  3264. type = <0x4>;
  3265. };
  3266.  
  3267. system {
  3268. type = <0x0>;
  3269. };
  3270. };
  3271.  
  3272. dram {
  3273. compatible = "allwinner,dram";
  3274. clocks = <0x93 0x94>;
  3275. clock-names = "pll_ddr0", "pll_ddr1";
  3276. dram_clk = <0x2a0>;
  3277. dram_type = <0x3>;
  3278. dram_zq = <0x3b3bdd>;
  3279. dram_odt_en = <0x1>;
  3280. dram_para1 = <0x10e40400>;
  3281. dram_para2 = <0x4000000>;
  3282. dram_mr0 = <0x1c70>;
  3283. dram_mr1 = <0x40>;
  3284. dram_mr2 = <0x18>;
  3285. dram_mr3 = <0x0>;
  3286. dram_tpr0 = <0x48a192>;
  3287. dram_tpr1 = <0x1c2418d>;
  3288. dram_tpr2 = <0x76051>;
  3289. dram_tpr3 = <0x50005dc>;
  3290. dram_tpr4 = <0x0>;
  3291. dram_tpr5 = <0x0>;
  3292. dram_tpr6 = <0x0>;
  3293. dram_tpr7 = <0x2a066198>;
  3294. dram_tpr8 = <0x0>;
  3295. dram_tpr9 = <0x0>;
  3296. dram_tpr10 = <0x8808>;
  3297. dram_tpr11 = <0x40a60066>;
  3298. dram_tpr12 = <0x55550000>;
  3299. dram_tpr13 = <0x4000903>;
  3300. device_type = "dram";
  3301. };
  3302.  
  3303. memory@40000000 {
  3304. device_type = "memory";
  3305. reg = <0x0 0x41000000 0x0 0x3f000000>;
  3306. };
  3307.  
  3308. interrupt-controller@1c81000 {
  3309. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  3310. #interrupt-cells = <0x3>;
  3311. #address-cells = <0x0>;
  3312. device_type = "gic";
  3313. interrupt-controller;
  3314. reg = <0x0 0x1c81000 0x0 0x1000 0x0 0x1c82000 0x0 0x2000 0x0 0x1c84000 0x0 0x2000 0x0 0x1c86000 0x0 0x2000>;
  3315. interrupts = <0x1 0x9 0xf04>;
  3316. linux,phandle = <0x1>;
  3317. phandle = <0x1>;
  3318. };
  3319.  
  3320. sunxi-chipid@1c14200 {
  3321. compatible = "sunxi,sun50i-chipid";
  3322. device_type = "chipid";
  3323. reg = <0x0 0x1c14200 0x0 0x400>;
  3324. };
  3325.  
  3326. timer {
  3327. compatible = "arm,armv8-timer";
  3328. interrupts = <0x1 0xd 0xff01 0x1 0xe 0xff01 0x1 0xb 0xff01 0x1 0xa 0xff01>;
  3329. clock-frequency = <0x16e3600>;
  3330. };
  3331.  
  3332. pmu {
  3333. compatible = "arm,armv8-pmuv3";
  3334. interrupts = <0x0 0x78 0x4 0x0 0x79 0x4 0x0 0x7a 0x4 0x0 0x7b 0x4>;
  3335. };
  3336.  
  3337. dvfs_table {
  3338. compatible = "allwinner,dvfs_table";
  3339. max_freq = <0x5B8D8000>;
  3340. min_freq = <0x1c9c3800>;
  3341. lv_count = <0x2>;
  3342. lv1_freq = <0x5B8D8000>;
  3343. lv1_volt = <0x5dc>;
  3344. lv2_freq = <0x1C9C3800>;
  3345. lv2_volt = <0x514>;
  3346. lv3_freq = <0x0>;
  3347. lv3_volt = <0x410>;
  3348. lv4_freq = <0x0>;
  3349. lv4_volt = <0x410>;
  3350. lv5_freq = <0x0>;
  3351. lv5_volt = <0x410>;
  3352. lv6_freq = <0x0>;
  3353. lv6_volt = <0x410>;
  3354. lv7_freq = <0x0>;
  3355. lv7_volt = <0x410>;
  3356. lv8_freq = <0x0>;
  3357. lv8_volt = <0x410>;
  3358. device_type = "dvfs_table";
  3359. };
  3360.  
  3361. dramfreq {
  3362. compatible = "allwinner,sunxi-dramfreq";
  3363. reg = <0x0 0x1c62000 0x0 0x1000 0x0 0x1c63000 0x0 0x1000 0x0 0x1c20000 0x0 0x800>;
  3364. clocks = <0x93 0x94 0x95>;
  3365. status = "okay";
  3366. };
  3367.  
  3368. uboot {
  3369. };
  3370.  
  3371. gpu@0x01c40000 {
  3372. compatible = "arm,mali-400", "arm,mali-utgard";
  3373. reg = <0x0 0x1c40000 0x0 0x10000>;
  3374. interrupts = <0x0 0x61 0x4 0x0 0x62 0x4 0x0 0x63 0x4 0x0 0x64 0x4 0x0 0x66 0x4 0x0 0x67 0x4>;
  3375. interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
  3376. clocks = <0x96 0x97>;
  3377. device_type = "gpu_mali400_0";
  3378. normal_freq = <0x198>;
  3379. scene_ctrl_status = <0x0>;
  3380. temp_ctrl_status = <0x1>;
  3381. };
  3382.  
  3383. wlan {
  3384. compatible = "allwinner,sunxi-wlan";
  3385. wlan_io_regulator = "vcc-wifi-io";
  3386. wlan_busnum = <0x1>;
  3387. status = "okay";
  3388. device_type = "wlan";
  3389. clocks;
  3390. wlan_power;
  3391. wlan_regon = <0x79 0xb 0x2 0x1 0xffffffff 0xffffffff 0x0>;
  3392. wlan_hostwake = <0x79 0xb 0x3 0x6 0xffffffff 0xffffffff 0x0>;
  3393. efuse_map_path = "wifi_efuse_8189e_for_MB1019Q5.map";
  3394. };
  3395.  
  3396. bt {
  3397. compatible = "allwinner,sunxi-bt";
  3398. bt_io_regulator = "vcc-wifi-io";
  3399. status = "okay";
  3400. device_type = "bt";
  3401. clocks;
  3402. bt_power;
  3403. bt_rst_n = <0x79 0xb 0x4 0x1 0xffffffff 0xffffffff 0x0>;
  3404. };
  3405.  
  3406. btlpm {
  3407. compatible = "allwinner,sunxi-btlpm";
  3408. uart_index = <0x1>;
  3409. status = "okay";
  3410. device_type = "btlpm";
  3411. bt_wake = <0x79 0xb 0x6 0x1 0xffffffff 0xffffffff 0x1>;
  3412. bt_hostwake = <0x79 0xb 0x5 0x6 0xffffffff 0xffffffff 0x0>;
  3413. };
  3414. };
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