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-- Company:
-- Engineer:
--
-- Create Date:    13:37:55 06/13/2016
-- Design Name:
-- Module Name:    dzielnik - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dzielnik is
	generic (N : integer := 25_000_000);
    Port ( clk_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end dzielnik;

architecture Behavioral of dzielnik is

	signal temp: STD_LOGIC;
    signal licznik : integer range 0 to N := 0;

begin

 dzielnik: process (reset, clk_in) begin
        if (reset = '1') then
            temp <= '0';
            licznik <= 0;
        elsif rising_edge(clk_in) then
            if (licznik = N) then
                temp <= NOT(temp);
                licznik <= 0;
            else
                licznik <= licznik + 1;
            end if;
        end if;
    end process;

    clk_out <= temp;

end Behavioral;