`timescale 1ns/1ps
module at_test;

reg clk, ena, reset;
logic [2:0] q;
logic [2:0] q1;


initial begin
    clk=0;
    forever #10 clk=~clk;
    end

initial
    begin
    q = 0;
    ena = 1;
    reset = 0;
    #10 reset = 1;
    for(int i = 0; i < 17; i++)
    begin
        #20 $strobe("%b -> %b ", q, q1);
            q = q1;
            if(i == 3 || i==4|| i==9 || i==10 || i==16)
                ena = ~ena;
    end
    #10 $stop;
    end

at uut_inst(clk, reset, ena, q1);

endmodule