sel2

use work.p_wires.all;

entity sel2 is
  port(s   : in  bit;
       z,w : out bit);
end sel2;

  component inv is
    port(A : in bit; S : out bit);
  end component inv;

  component nand2 is
    port(A,B : in bit; S : out bit);
  end component nand2

  signal a, c, r, p: bit;

architecture estrut of sel2 is
begin
  -- implemente com portas logicas
  Ui1: inv port map (s,a);
  Un1: nand2 port map (s,a,c);
  Udm1: demux2 port map (c,s,z);
  Udm2: demux2 port map (c,a,w);

end architecture estrut;