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Oct 22nd, 2016
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VHDL 0.79 KB | None | 0 0
  1.    Frequency_setting: process(SMCLK, RESET)
  2.  
  3.     begin
  4.        
  5.         if RESET = '1' then
  6.         time_counter <= "0000000000000000000000";      
  7.         shift_counter <= "00000000";
  8.        
  9.         elsif SMCLK'event and SMCLK = '1' then
  10.         shift_counter <=  shift_counter + "1";
  11.        
  12.         if shift_counter(7 downto 0) = "11111111" then
  13.             shift_counter <= "00000000";
  14.             flag_8b <= '1';
  15.         else
  16.             flag_8b <= '0';
  17.         end if;
  18.        
  19.             if  flag_half_sec = '0' then
  20.                 time_counter <= time_counter + "1";
  21.                  
  22.             if time_counter(21 downto 0) = "1111111111111111111111" then
  23.                         flag_half_sec <= '1';
  24.                     else
  25.                         flag_half_sec <= '0';
  26.                     end if;
  27.                 end if;
  28.             end if;
  29.  
  30.     end process Frequency_setting;
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