#!/bin/python3

from migen import *
from migen.fhdl import verilog

class crc7(Module):
    def __init__(self):
        self.crc = crc = [Signal(7) for i in range(48)]
        self.val =  val = Signal(40)

        for i in range(40):
            inv = val[39-i] ^ crc[i][6]
            self.comb += crc[i+1].eq(Cat(inv, crc[i][0], crc[i][1], crc[i][2]^inv, crc[i][3], crc[i][4], crc[i][5] ))


def counter_test(dut):
    yield dut.val.eq(0x3700000120)
    #yield dut.val.eq(0x7700000000)
    yield
    print(format((yield dut.crc[40]),'02x'))


dut = crc7()
run_simulation(dut, counter_test(dut), vcd_name="basic2.vcd")
#print(verilog.convert(crc7()))