library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity CAM is
    port( addr: in std_logic_vector(1 downto 0);
        data: in std_logic_vector(11 downto 0);
        cs: in std_logic;
        r: in std_logic;
        mv: out std_logic_vector(3 downto 0)
        hit: out std_logic);
end CAM;

architecture behav of CAM is
    signal eq: boolean;
    type states is (WT,R0,R1,R2,STO,R3);
    type CAM is array (0 to 3) of std_logic_vector(11 downto 0);
    signal newstates: states;

begin
-- State Transition Process
    process is
        variable current: states := R3;
    begin
        if clk = '1' then
            case current is
                when WT =>
                    if cs = '0' then
                        current := WT;
                    end if;
                    if (cs = '1') and (r = '1') then
                        current := R0;
                    end if;

                    if (cs = '1') and (r = '0') then
                        current := STO;
                    end if;
                when R0 =>
                    current := R1;
                when R1 =>
                    if eq = '1' then
                        current := R3;
                    end if;

                    if eq = '0' then
                        current := R2;
                    end if;

                when R2 =>
                    current := R0;
                when R3 =>
                    if cs = '1' then
                        current := R3;
                    end if;

                    if cs = '0' then
                        current := WT;
                    end if;
                when STO =>
                    if cs = '1' then
                        current := STO;
                    end if;

                    if cs = '0' then
                        current := WT;
                    end if;
            end case;
            newstates <= current;
        end if;
    wait on clk;
    end process;
-- Asserted Outputs process
    process is
        variable i: std_logic_vector(3 downto 0);
        variable CAMHolder: CAM;
        variable addrHolder: integer;
        variable iHolder: integer;
    begin
        addrHolder := to_integer(addr);
        case newstates is
            when WT =>
                i := "0000";
                mv <= "0000";
                hit <= '0';
            when R0 =>
                eq <= ( i = "0011");
            when R1 =>
            when R2 =>
                iHolder := to_integer(i);
                mv(i) <= (CAMHolder(addrHolder) := data);
                i := i + "0001";
            when R3 =>
                hit <= not(mv = "0000");
            when STO =>
                CAMHolder(addrHolder) := data;
        end case;
    wait on newstates;
    end process;


end behav;