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Jul 31st, 2014
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  1. /** Intel(R) Many Integrated Core Architecture does not support mfence and pause instructions **/
  2. #define __TBB_full_memory_fence() __asm__ __volatile__("lock; addl $0,(%%rsp)":::"memory")
  3. #define __TBB_Pause(x) _mm_delay_32(16*(x))
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