library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity maszyna2 is
Port ( SEKUNDY : in  STD_LOGIC_VECTOR(3 downto 0);
         Sec : in  STD_LOGIC_VECTOR(3 downto 0);
         SETNE : in  STD_LOGIC_VECTOR(3 downto 0);
         Set : in  STD_LOGIC_VECTOR(3 downto 0);

         clk: in STD_LOGIC;

         L : out  STD_LOGIC_VECTOR(3 downto 0);
         A : out STD_LOGIC;
       B : out STD_LOGIC
       );
end maszyna2;

architecture Behavioral of maszyna2 is

    signal SEKUNDY_t : STD_LOGIC_VECTOR(3 downto 0);
    signal Sec_t : STD_LOGIC_VECTOR(3 downto 0);
    signal SETNE_t : STD_LOGIC_VECTOR(3 downto 0);
    signal Set_t : STD_LOGIC_VECTOR(3 downto 0);
    signal LICZBA : STD_LOGIC_VECTOR(3 downto 0);
    signal BLok : STD_LOGIC_VECTOR(1 downto 0);
    type state_type is (q0, q1,q2,q3);
    signal state, next_state: state_type;
    SIGNAL ABC_LOG : STD_LOGIC;
   SIGNAL AB_a : STD_LOGIC;
   SIGNAL AB_b : STD_LOGIC;

begin

    PROCESS(SEKUNDY,Sec,SETNE,Set)
   BEGIN
   SEKUNDY_t  <=SEKUNDY;
    Sec_t  <=Sec;
    SETNE_t   <=SETNE;
    Set_t  <=Set;
   END PROCESS;


   process2 : process (clk)
        begin
            ABC_LOG <= not ABC_LOG;
            state <= next_state;
                case state is
                    when q0 =>
                    AB_a <= '0';
                    AB_b <= '0';
                    --BLok <= "00";
                    LICZBA<= SEKUNDY_t;
                    next_state <= q1;

                    when q1 =>
                    AB_a <= '1';
                    AB_b <= '0';
                    --BLok <= "01";
                    LICZBA<= Sec_t;
                    next_state <= q2;

                    when q2 =>
                    AB_a <= '0';
                    AB_b <= '1';
                    --BLok <= "10";
                    LICZBA<= SETNE_t;
                    next_state <= q3;

                    when q3 =>
                    AB_a <= '1';
                    AB_b <= '1';
                    --BLok <= "11";
                    LICZBA<= Set_t;
                    next_state <= q0;

                end case;
    end process;
  PROCESS(ABC_LOG)
  BEGIN
   A <= AB_a;
   B <= AB_b;
   L <= LICZBA;
  END PROCESS;
end Behavioral;