Counter_60

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity Counter_60 is
    Port ( CLK : in  STD_LOGIC;
           En : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Cout : out  STD_LOGIC;
           Fout : out  STD_LOGIC_VECTOR (5 downto 0));
end Counter_60;

architecture Behavioral of Counter_60 is
	signal	time	:	std_logic_vector(5 downto 0) := "000000";
begin
	TT:process(CLK,Rst,En)
	Begin
		if (CLK='1' and CLK'event) then
			if (Rst = '1') then
				time <= "000000";
				Cout <= '0';
			else
				if (En = '1') then
					if (time < "111011") then
						time <= time+1;
						if (time = "111010") then
							Cout <= '1';
						else
							Cout <= '0';
						End if;
					else
						time <= "000000";
						Cout <= '0';
					End if;
				End if;
			End if;
		End if;
	End process;
	Fout <= time;
end Behavioral;