module uart_rx(clock, uart_clock, reset, rx_pin, done, data);
    input wire clock;
    input wire uart_clock;
    input wire reset;
    input wire rx_pin;
    output reg done;
    output reg[7:0] data;

    `define UART_RX_IDLE 0
    `define UART_RX_START 1
    `define UART_RX_PRE_DATA 2
    `define UART_RX_DATA 3

    reg[2:0] state;
    reg[3:0] cur_bit;

    always @(posedge clock) begin
        if (reset == 1'b1) begin
            state <= `UART_RX_IDLE;
            data <= 0;
            done <= 0;
        end else if (uart_clock) begin
            case (state)
                `UART_RX_IDLE:
                    if (rx_pin == 1'b0)
                        state <= `UART_RX_START;
                `UART_RX_START:
                    if (rx_pin == 1'b0) begin
                        state <= `UART_RX_PRE_DATA;
                        cur_bit <= 0;
                        done <= 0;
                    end else
                        state <= `UART_RX_IDLE;
                `UART_RX_PRE_DATA:
                    state <= `UART_RX_DATA;
                `UART_RX_DATA: begin
                    data[cur_bit] = rx_pin;
                    cur_bit = cur_bit + 1'b1;
                    if (cur_bit == 4'b1000) begin
                        state <= `UART_RX_IDLE;
                        done <= 1;
                    end else
                        state <= `UART_RX_PRE_DATA;
                end
            endcase
        end
    end
endmodule

module uart_tx(clock, uart_clock, reset, tx_pin, send, busy, data);
    input wire clock;
    input wire uart_clock;
    input wire reset;
    output reg tx_pin;
    input wire send;
    output reg busy;
    input wire[7:0] data;

    `define UART_TX_IDLE 0
    `define UART_TX_START 1
    `define UART_TX_DATA 2
    `define UART_TX_STOP 3

    reg[2:0] state;
    reg[3:0] cur_bit;

    always @(posedge clock) begin
        if (reset == 1'b1) begin
            state <= `UART_TX_IDLE;
            busy <= 0;
         end else if (uart_clock) begin
            state[2] = ~state[2];
            case (state)
                `UART_TX_IDLE: begin
                    tx_pin <= 1;
                    if (send) begin
                        busy <= 1;
                        state <= `UART_TX_START;
                    end
                end
                `UART_TX_START: begin
                    tx_pin <= 0;
                    state <= `UART_TX_DATA;
                    cur_bit <= 0;
                end
                `UART_TX_DATA: begin
                    tx_pin = data[cur_bit];
                    cur_bit = cur_bit + 1'b1;
                    if (cur_bit == 4'b1000) begin
                        state <= `UART_TX_IDLE;
                        busy <= 0;
                    end
                end
                `UART_TX_STOP: begin
                    busy <= 0;
                    state <= `UART_TX_IDLE;
                end
            endcase
        end
    end
endmodule