for trisquel forms

This file is a list of the people responsible for ensuring that patches for a
particular part of LLVM are reviewed, either by themself or by someone else.
They are also the gatekeepers for their part of LLVM, with the final word on
what goes in or not.

The list is sorted by surname and formatted to allow easy grepping and
beautification by scripts.  The fields are: name (N), email (E), web-address
(W), PGP key ID and fingerprint (P), description (D), and snail-mail address
(S).

N: Joe Abbey
E: [email protected]
D: LLVM Bitcode (lib/Bitcode/* include/llvm/Bitcode/*)

N: Owen Anderson
E: [email protected]
D: SelectionDAG (lib/CodeGen/SelectionDAG/*)

N: Rafael Avila de Espindola
E: [email protected]
D: Gold plugin (tools/gold/*)

N: Chandler Carruth
E: [email protected]
E: [email protected]
D: Config, ADT, Support, inlining & related passes, SROA/mem2reg & related passes, CMake, library layering

N: Evan Cheng
E: [email protected]
D: ARM target, parts of code generator not covered by someone else

N: Renato Golin
E: [email protected]
D: ARM Linux support

N: Eric Christopher
E: [email protected]
D: Debug Information, autotools/configure/make build, inline assembly

N: Greg Clayton
D: LLDB

N: Peter Collingbourne
D: libclc

N: Anshuman Dasgupta
E: [email protected]
D: Hexagon Backend

N: Hal Finkel
E: [email protected]
D: BBVectorize, the loop reroller and the PowerPC target

N: Venkatraman Govindaraju
E: [email protected]
D: Sparc Backend (lib/Target/Sparc/*)

N: Tobias Grosser
D: Polly

N: James Grosbach
E: [email protected]
D: MC layer

N: Marshall Clow
E: [email protected]
D: libc++

N: Justin Holewinski
E: [email protected]
D: NVPTX Target (lib/Target/NVPTX/*)

N: Lang Hames
E: [email protected]
D: MCJIT, RuntimeDyld and JIT event listeners

N: Galina Kistanova
E: [email protected]
D: LLVM Buildbot

N: Anton Korobeynikov
E: [email protected]
D: Exception handling, Windows codegen, ARM EABI

N: Benjamin Kramer
E: [email protected]
D: DWARF Parser

N: Sergei Larin
E: [email protected]
D: VLIW Instruction Scheduling, Packetization

N: Chris Lattner
E: [email protected]
W: http://nondot.org/~sabre/
D: Everything not covered by someone else

N: Tim Northover
E: [email protected]
D: AArch64 backend

N: Jakob Olesen
D: Register allocators and TableGen

N: Richard Osborne
E: [email protected]
D: XCore Backend

N: Chad Rosier
E: [email protected]
D: Fast-Isel

N: Nadav Rotem
E: [email protected]
D: X86 Backend, Loop Vectorizer

N: Daniel Sanders
E: [email protected]
D: MIPS Backend (lib/Target/Mips/*)

N: Richard Sandiford
E: [email protected]
D: SystemZ Backend

N: Duncan Sands
E: [email protected]
D: DragonEgg

N: Kostya Serebryany
E: [email protected]
D: AddressSanitizer, ThreadSanitizer (LLVM parts)

N: Michael Spencer
E: [email protected]
D: Windows parts of Support, Object, ar, nm, objdump, ranlib, size

N: Tom Stellard
E: [email protected]
E: [email protected]
D: R600 Backend

N: Evgeniy Stepanov
E: [email protected]
D: MemorySanitizer (LLVM part)

N: Andrew Trick
E: [email protected]
D: IndVar Simplify, Loop Strength Reduction, Instruction Scheduling

N: Bill Wendling
E: [email protected]
D: libLTO, IR Linker

N: Peter Zotov
E: [email protected]
D: OCaml bindings