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Jun 22nd, 2016
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  1. // GPTIMER register offsets
  2. #define GPTIMER8 0x4903E000
  3. #define GPT_REG_TCLR 0x024
  4. #define GPT_REG_TCRR 0x028
  5. #define GPT_REG_TLDR 0x02c
  6. #define GPT_REG_TMAR 0x038
  7.  
  8. ...
  9.  
  10. int pwm_config_timer(guint32 resolution)
  11. {
  12.  
  13. guint8 *registers = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, mem_fd, GPTIMER8);
  14. if (registers == MAP_FAILED)
  15. {
  16. return -1;
  17. }
  18.  
  19. ...
  20.  
  21. *REG32_PTR(registers, GPT_REG_TCLR) = 0; // Turn off !!!!!
  22.  
  23.  
  24.  
  25.  
  26. *REG32_PTR(registers, GPT_REG_TCRR) = counter_start;
  27. *REG32_PTR(registers, GPT_REG_TLDR) = counter_start;
  28. *REG32_PTR(registers, GPT_REG_TMAR) = dc;
  29. *REG32_PTR(registers, GPT_REG_TCLR) = (
  30. (1 << 0) | // ST -- enable counter
  31. (1 << 1) | // AR -- autoreload on overflow
  32. (1 << 6) | // CE -- compare enabled
  33. (1 << 7) | // SCPWM -- invert pulse
  34. (2 << 10) | // TRG -- overflow and match trigger
  35. (1 << 12) // PT -- toggle PWM mode
  36. );
  37.  
  38. return munmap(registers, 4096);
  39. }
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