`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    22:50:18 01/24/2013
// Design Name:
// Module Name:    Lab3_1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Lab3_1(
    input clock,
         output en_1,
         output en_2,
         output en_3,
         output en_4,
    output a,
    output b,
    output c,
    output d,
    output e,
    output f,
    output g
    );

         parameter MSB=24;

         reg[MSB:0] count;
         reg[MSB:0] count2;
         reg[2:0] count3=3;

         reg[1:0] pos;

         reg[3:0] pstate;
         reg[6:0] loop;

         /*reg[6:0] id;
         id[7] = 5;
         id[6] = 4;
         id[5] = 3;
         id[4] = 0;
         id[3] = 4;
         id[2] = 7;
         id[1] = 4;
         id[0] = 5;*/

         reg[3:0] number;

         reg[3:0] en = 4'b1111;

         assign en_1 = en[0];
         assign en_2 = en[1];
         assign en_3 = en[2];
         assign en_4 = en[3];

         segment num(number,a,b,c,d,e,f,g);

         always@(posedge clock)
         begin
         if(count<=134217)
                count <= count + 1;
         else
                count <= 1;
         end

         always@(posedge clock)
         begin
         if(count2<33554432)
                count2 <= count2 + 1;
         else begin
                count2 <= 1;
                count3 <= count3+1;
         end
         end

         always@(posedge clock)
         begin
                if(loop == 99)
                        loop <= 0;
                else
                        loop <= loop + 1;
         end

         //เลข
         always@(posedge clock)
         begin
                if(count == 1)
                        begin
                                if(pstate == count3) begin
                                        pstate <= count3-3;
                                end
                                else
                                        pstate <= pstate + 1;
                        end
        if(count2 == 1)
            begin
                pstate<=pstate-2;
            end
         end

         //ตำแหน่ง
         always@(posedge clock)
         begin
                if(count == 1)
                        pos <= pos + 1;
         end

         always@(*)
         begin
                case(pos)
                        0       :       begin
                                                en = 4'b0111;
                                        end
                        1       :       begin
                                                en = 4'b1011;
                                        end
                        2       :       begin
                                                en = 4'b1101;
                                        end
                        3       :       begin
                                                en = 4'b1110;
                                        end
                endcase
         end

         always@(*)
         begin
                number = 0;

                case(pstate)
                        0       :       begin
                                                number = 5;
                                        end
                        1       :       begin
                                                number = 4;
                                        end
                        2       :       begin
                                                number = 3;
                                        end
                        3       :       begin
                                                number = 0;
                                        end
                        4       :       begin
                                                number = 4;
                                        end
                        5       :       begin
                                                number = 7;
                                        end
                        6       :       begin
                                                number = 4;
                                        end
                        7       :       begin
                                                number = 5;
                                        end
                endcase
        end
endmodule