neon

	.cpu cortex-a8
	.eabi_attribute 27, 3
	.fpu neon
	.eabi_attribute 23, 1
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 18, 4
	.file	"testvect_intrinsic.cpp"
	.text
	.align	2
	.global	_ZrsRSiR5matx4
	.type	_ZrsRSiR5matx4, %function
_ZrsRSiR5matx4:
	.fnstart
.LFB1000:
	@ args = 0, pretend = 0, frame = 64
	@ frame_needed = 0, uses_anonymous_args = 0
	stmfd	sp!, {r4, r5, r6, lr}
	.save {r4, r5, r6, lr}
	.pad #64
	sub	sp, sp, #64
	mov	r5, r0
	mov	r6, r1
	mov	r1, sp
	mov	r4, sp
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #4
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #8
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #12
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #16
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #20
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #24
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #28
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #32
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #36
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #40
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #44
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #48
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #52
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #56
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	add	r1, sp, #60
	mov	r0, r5
	bl	_ZNSi10_M_extractIfEERSiRT_
	ldmia	r4!, {r0, r1, r2, r3}
	mov	ip, r6
	stmia	ip!, {r0, r1, r2, r3}
	ldmia	r4!, {r0, r1, r2, r3}
	stmia	ip!, {r0, r1, r2, r3}
	ldmia	r4!, {r0, r1, r2, r3}
	stmia	ip!, {r0, r1, r2, r3}
	ldmia	r4, {r0, r1, r2, r3}
	stmia	ip, {r0, r1, r2, r3}
	mov	r0, r5
	add	sp, sp, #64
	ldmfd	sp!, {r4, r5, r6, pc}
	.fnend
	.size	_ZrsRSiR5matx4, .-_ZrsRSiR5matx4
	.align	2
	.global	_ZlsRSoRK9formatter
	.type	_ZlsRSoRK9formatter, %function
_ZlsRSoRK9formatter:
	.fnstart
.LFB1005:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	ip, [r0, #0]
	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
	.save {r4, r5, r6, r7, r8, lr}
	mov	r6, r1
	ldr	r3, [ip, #-12]
	mov	r1, #12
	mov	r4, r0
	add	r2, r0, r3
	str	r1, [r2, #8]
	ldr	r5, [ip, #-12]
	add	r5, r0, r5
	ldrb	r3, [r5, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L3:
	mov	r1, #95
	strb	r1, [r5, #116]
	flds	s15, [r6, #0]
	fcvtds	d16, s15
	mov	r0, r4
	fmrrd	r2, r3, d16
	ldmfd	sp!, {r4, r5, r6, r7, r8, lr}
	b	_ZNSo9_M_insertIdEERSoT_
.L8:
	ldr	r7, [r5, #124]
	cmp	r7, #0
	beq	.L9
	ldrb	ip, [r7, #28]	@ zero_extendqisi2
	cmp	ip, #0
	ldrneb	r0, [r7, #61]	@ zero_extendqisi2
	bne	.L6
	mov	r0, r7
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r3, [r7, #0]
	mov	r0, r7
	mov	r1, #32
	ldr	r2, [r3, #24]
	blx	r2
.L6:
	strb	r0, [r5, #116]
	mov	r0, #1
	strb	r0, [r5, #117]
	b	.L3
.L9:
	bl	_ZSt16__throw_bad_castv
	.fnend
	.size	_ZlsRSoRK9formatter, .-_ZlsRSoRK9formatter
	.align	2
	.global	_ZlsRSoRK5matx4
	.type	_ZlsRSoRK5matx4, %function
_ZlsRSoRK5matx4:
	.fnstart
.LFB1006:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	stmfd	sp!, {r4, r5, r6, r7, r8, lr}
	.save {r4, r5, r6, r7, r8, lr}
	fstmfdd	sp!, {d8}
	.vsave {d8}
	mov	r4, r1
	flds	s16, [r1, #0]
	ldr	r7, [r0, #0]
	mov	r1, #12
	.pad #8
	sub	sp, sp, #8
	mov	r5, r0
	ldr	ip, [r7, #-12]
	add	r2, r0, ip
	str	r1, [r2, #8]
	ldr	r6, [r7, #-12]
	add	r6, r0, r6
	ldrb	r3, [r6, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
.L12:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r5
	strb	r1, [r6, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r5, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r5, #0]
	flds	s16, [r4, #4]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r5, r2
	str	r1, [r2, #8]
	ldr	r6, [r3, #-12]
	add	r6, r5, r6
	ldrb	r3, [r6, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
.L17:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r5
	strb	r1, [r6, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r5, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r5, #0]
	flds	s16, [r4, #8]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r5, r2
	str	r1, [r2, #8]
	ldr	r6, [r3, #-12]
	add	r6, r5, r6
	ldrb	r3, [r6, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
.L22:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r5
	strb	r1, [r6, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #12]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r6, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
.L27:
	fcvtds	d16, s16
	add	r5, sp, #8
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	mov	r3, #10
	mov	r2, #1
	strb	r3, [r5, #-1]!
	mov	r1, r5
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	flds	s16, [r4, #16]
	mov	r1, #12
	ldr	r3, [r0, #0]
	mov	r6, r0
	ldr	r2, [r3, #-12]
	add	r2, r0, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r0, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
.L32:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #20]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r6, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L101
.L37:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #24]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r6, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L42:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #28]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r6, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L47:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	mov	r1, r5
	mov	r2, #1
	mov	r3, #10
	strb	r3, [sp, #7]
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	flds	s16, [r4, #32]
	mov	r1, #12
	ldr	r3, [r0, #0]
	mov	r6, r0
	ldr	r2, [r3, #-12]
	add	r2, r0, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r0, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
.L52:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #36]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r6, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
.L57:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #40]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r6, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L62:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #44]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r6, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L67:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	mov	r1, r5
	mov	r2, #1
	mov	r3, #10
	strb	r3, [sp, #7]
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	flds	s16, [r4, #48]
	mov	r1, #12
	ldr	r3, [r0, #0]
	mov	r6, r0
	ldr	r2, [r3, #-12]
	add	r2, r0, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r0, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
.L72:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #52]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r6, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
.L77:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #56]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r7, [r3, #-12]
	add	r7, r6, r7
	ldrb	r3, [r7, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L82:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r7, #116]
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L112
	mov	r2, #1
	mov	r6, r0
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r6, #0]
	flds	s16, [r4, #60]
	mov	r1, #12
	ldr	r2, [r3, #-12]
	add	r2, r6, r2
	str	r1, [r2, #8]
	ldr	r4, [r3, #-12]
	add	r4, r6, r4
	ldrb	r3, [r4, #117]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
.L87:
	fcvtds	d16, s16
	mov	r1, #95
	mov	r0, r6
	strb	r1, [r4, #116]
	mov	r4, #10
	fmrrd	r2, r3, d16
	bl	_ZNSo9_M_insertIdEERSoT_
	mov	r1, r5
	mov	r2, #1
	strb	r4, [sp, #7]
	bl	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i
	ldr	r3, [r0, #0]
	mov	r5, r0
	ldr	r3, [r3, #-12]
	add	r3, r0, r3
	ldr	r6, [r3, #124]
	cmp	r6, #0
	beq	.L95
	ldrb	r2, [r6, #28]	@ zero_extendqisi2
	cmp	r2, #0
	ldrneb	r1, [r6, #39]	@ zero_extendqisi2
	bne	.L93
	mov	r0, r6
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r3, [r6, #0]
	mov	r1, r4
	mov	r0, r6
	ldr	ip, [r3, #24]
	blx	ip
	mov	r1, r0
.L93:
	mov	r0, r5
	bl	_ZNSo3putEc
	bl	_ZNSo5flushEv
	add	sp, sp, #8
	fldmfdd	sp!, {d8}
	ldmfd	sp!, {r4, r5, r6, r7, r8, pc}
.L96:
	ldr	r7, [r6, #124]
	cmp	r7, #0
	beq	.L95
	ldrb	lr, [r7, #28]	@ zero_extendqisi2
	cmp	lr, #0
	ldrneb	r0, [r7, #61]	@ zero_extendqisi2
	bne	.L15
	mov	r0, r7
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r2, [r7, #0]
	mov	r0, r7
	mov	r1, #32
	ldr	r3, [r2, #24]
	blx	r3
.L15:
	strb	r0, [r6, #116]
	mov	r0, #1
	strb	r0, [r6, #117]
	b	.L12
.L97:
	ldr	r7, [r6, #124]
	cmp	r7, #0
	beq	.L95
	ldrb	r1, [r7, #28]	@ zero_extendqisi2
	cmp	r1, #0
	ldrneb	r0, [r7, #61]	@ zero_extendqisi2
	bne	.L20
	mov	r0, r7
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	ip, [r7, #0]
	mov	r0, r7
	mov	r1, #32
	ldr	r7, [ip, #24]
	blx	r7
.L20:
	mov	lr, #1
	strb	r0, [r6, #116]
	strb	lr, [r6, #117]
	b	.L17
.L98:
	ldr	r7, [r6, #124]
	cmp	r7, #0
	beq	.L95
	ldrb	r3, [r7, #28]	@ zero_extendqisi2
	cmp	r3, #0
	ldrneb	r0, [r7, #61]	@ zero_extendqisi2
	bne	.L25
	mov	r0, r7
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	ip, [r7, #0]
	mov	r0, r7
	mov	r1, #32
	ldr	r2, [ip, #24]
	blx	r2
.L25:
	strb	r0, [r6, #116]
	mov	r0, #1
	strb	r0, [r6, #117]
	b	.L22
.L99:
	ldr	r5, [r7, #124]
	cmp	r5, #0
	beq	.L95
	ldrb	r1, [r5, #28]	@ zero_extendqisi2
	cmp	r1, #0
	ldrneb	r0, [r5, #61]	@ zero_extendqisi2
	bne	.L30
	mov	r0, r5
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r3, [r5, #0]
	mov	r0, r5
	mov	r1, #32
	ldr	r5, [r3, #24]
	blx	r5
.L30:
	mov	lr, #1
	strb	r0, [r7, #116]
	strb	lr, [r7, #117]
	b	.L27
.L100:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	r2, [r8, #28]	@ zero_extendqisi2
	cmp	r2, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L35
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r3, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	ip, [r3, #24]
	blx	ip
.L35:
	strb	r0, [r7, #116]
	mov	r0, #1
	strb	r0, [r7, #117]
	b	.L32
.L101:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	r1, [r8, #28]	@ zero_extendqisi2
	cmp	r1, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L40
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	ip, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	r2, [ip, #24]
	blx	r2
.L40:
	mov	lr, #1
	strb	r0, [r7, #116]
	strb	lr, [r7, #117]
	b	.L37
.L103:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	r1, [r8, #28]	@ zero_extendqisi2
	cmp	r1, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L50
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r2, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	r3, [r2, #24]
	blx	r3
.L50:
	mov	lr, #1
	strb	r0, [r7, #116]
	strb	lr, [r7, #117]
	b	.L47
.L102:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	r3, [r8, #28]	@ zero_extendqisi2
	cmp	r3, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L45
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	ip, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	r2, [ip, #24]
	blx	r2
.L45:
	strb	r0, [r7, #116]
	mov	r0, #1
	strb	r0, [r7, #117]
	b	.L42
.L105:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	r1, [r8, #28]	@ zero_extendqisi2
	cmp	r1, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L60
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r3, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	ip, [r3, #24]
	blx	ip
.L60:
	mov	lr, #1
	strb	r0, [r7, #116]
	strb	lr, [r7, #117]
	b	.L57
.L104:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	ip, [r8, #28]	@ zero_extendqisi2
	cmp	ip, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L55
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r2, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	r3, [r2, #24]
	blx	r3
.L55:
	strb	r0, [r7, #116]
	mov	r0, #1
	strb	r0, [r7, #117]
	b	.L52
.L106:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	r2, [r8, #28]	@ zero_extendqisi2
	cmp	r2, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L65
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r3, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	ip, [r3, #24]
	blx	ip
.L65:
	strb	r0, [r7, #116]
	mov	r0, #1
	strb	r0, [r7, #117]
	b	.L62
.L107:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	r1, [r8, #28]	@ zero_extendqisi2
	cmp	r1, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L70
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	ip, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	r2, [ip, #24]
	blx	r2
.L70:
	mov	lr, #1
	strb	r0, [r7, #116]
	strb	lr, [r7, #117]
	b	.L67
.L108:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	r3, [r8, #28]	@ zero_extendqisi2
	cmp	r3, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L75
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	ip, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	r2, [ip, #24]
	blx	r2
.L75:
	strb	r0, [r7, #116]
	mov	r0, #1
	strb	r0, [r7, #117]
	b	.L72
.L109:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	r1, [r8, #28]	@ zero_extendqisi2
	cmp	r1, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L80
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r2, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	r3, [r2, #24]
	blx	r3
.L80:
	mov	lr, #1
	strb	r0, [r7, #116]
	strb	lr, [r7, #117]
	b	.L77
.L111:
	ldr	r7, [r4, #124]
	cmp	r7, #0
	beq	.L95
	ldrb	r1, [r7, #28]	@ zero_extendqisi2
	cmp	r1, #0
	ldrneb	r0, [r7, #61]	@ zero_extendqisi2
	bne	.L90
	mov	r0, r7
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r3, [r7, #0]
	mov	r0, r7
	mov	r1, #32
	ldr	ip, [r3, #24]
	blx	ip
.L90:
	mov	lr, #1
	strb	r0, [r4, #116]
	strb	lr, [r4, #117]
	b	.L87
.L110:
	ldr	r8, [r7, #124]
	cmp	r8, #0
	beq	.L95
	ldrb	ip, [r8, #28]	@ zero_extendqisi2
	cmp	ip, #0
	ldrneb	r0, [r8, #61]	@ zero_extendqisi2
	bne	.L85
	mov	r0, r8
	bl	_ZNKSt5ctypeIcE13_M_widen_initEv
	ldr	r2, [r8, #0]
	mov	r0, r8
	mov	r1, #32
	ldr	r3, [r2, #24]
	blx	r3
.L85:
	strb	r0, [r7, #116]
	mov	r0, #1
	strb	r0, [r7, #117]
	b	.L82
.L95:
	bl	_ZSt16__throw_bad_castv
.L113:
	.align	2
.L112:
	.word	.LC0
	.fnend
	.size	_ZlsRSoRK5matx4, .-_ZlsRSoRK5matx4
	.global	__aeabi_ul2d
	.section	.text.startup,"ax",%progbits
	.align	2
	.global	main
	.type	main, %function
main:
	.fnstart
.LFB1007:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 0, uses_anonymous_args = 0
	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
	.save {r4, r5, r6, r7, r8, r9, sl, fp, lr}
	fstmfdd	sp!, {d8, d9}
	.vsave {d8, d9}
	.pad #20
	sub	sp, sp, #20
	ldr	r1, .L118+8
	mov	r4, #34560
	ldr	r0, .L118+12
	movt	r4, 915
	bl	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	ldr	r1, .L118+16
	ldr	r0, .L118+20
	bl	_ZrsRSiR5matx4
	ldr	r1, .L118+24
	ldr	r0, .L118+12
	bl	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	ldr	r1, .L118+28
	ldr	r0, .L118+20
	bl	_ZrsRSiR5matx4
	ldr	r1, .L118+32
	ldr	r0, .L118+12
	bl	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	add	r1, sp, #12
	ldr	r0, .L118+20
	bl	_ZNSi10_M_extractIfEERSiRT_
	flds	s0, [sp, #12]
	ftouizs	s15, s0
	mov	r0, #1
	add	r1, sp, #4
	fmrs	r5, s15	@ int
	bl	clock_gettime
	ldr	sl, [sp, #4]
	mov	r3, #51712
	movt	r3, 15258
	ldr	r8, [sp, #8]
	ldr	r0, .L118+16
	sub	r5, r5, #1
	smull	sl, fp, sl, r3
	mov	r9, r8, asr #31
	add	r7, r0, #128
.L116:
	mov	r1, r5, asl #6
	add	r2, r5, #1
	add	r3, r0, r1
	subs	r4, r4, #1
	add	r2, r0, r2, asl #6
	vldr	d24, [r2, #16]
	vldr	d25, [r2, #24]
	ldr	r6, [r3, #20]	@ float
	vldmia	r2, {d22-d23}
	ldr	ip, [r3, #36]	@ float
	add	r1, r7, r1
	ldr	lr, [r3, #4]	@ float
	mov	r5, r5, asl #1
	vdup.32	q9, r6
	ldr	r6, [r3, #52]	@ float
	vdup.32	q8, ip
	ldr	ip, [r3, #16]	@ float
	vdup.32	q10, lr
	vmul.f32	q9, q9, q12
	vdup.32	q1, r6
	ldr	lr, [r3, #0]	@ float
	vmul.f32	q10, q12, q10
	vdup.32	q14, ip
	ldr	r6, [r3, #32]	@ float
	vmul.f32	q8, q8, q12
	ldr	ip, [r3, #48]	@ float
	vdup.32	q13, lr
	ldr	lr, [r3, #8]	@ float
	vmul.f32	q12, q1, q12
	vdup.32	q3, r6
	vdup.32	q2, ip
	ldr	r6, [r3, #24]	@ float
	vmla.f32	q10, q13, q11
	ldr	ip, [r3, #40]	@ float
	vdup.32	q15, lr
	ldr	lr, [r3, #28]	@ float
	vmla.f32	q9, q14, q11
	vdup.32	q1, r6
	ldr	r6, [r3, #56]	@ float
	vdup.32	q0, ip
	vmla.f32	q8, q3, q11
	vldr	d28, [r2, #32]
	vldr	d29, [r2, #40]
	ldr	ip, [r3, #44]	@ float
	vldr	d26, [r2, #48]
	vldr	d27, [r2, #56]
	vmla.f32	q12, q2, q11
	vdup.32	q4, r6
	ldr	r6, [r3, #12]	@ float
	ldr	r3, [r3, #60]	@ float
	vdup.32	q3, ip
	vmla.f32	q10, q14, q15
	vdup.32	q15, lr
	vdup.32	q2, r6
	vmla.f32	q9, q1, q14
	vdup.32	q11, r3
	vmla.f32	q8, q0, q14
	vmla.f32	q12, q4, q14
	vmla.f32	q10, q13, q2
	vstmia	r1, {d20-d21}
	vmla.f32	q9, q15, q13
	vstr	d18, [r1, #16]
	vstr	d19, [r1, #24]
	vmla.f32	q8, q3, q13
	vstr	d16, [r1, #32]
	vstr	d17, [r1, #40]
	vmla.f32	q12, q11, q13
	vstr	d24, [r1, #48]
	vstr	d25, [r1, #56]
	bne	.L116
	add	r1, sp, #4
	mov	r0, #1
	bl	clock_gettime
	ldr	r2, [sp, #4]
	mov	r3, #51712
	movt	r3, 15258
	ldr	ip, [sp, #8]
	smull	r2, r3, r2, r3
	subs	r2, r2, r8
	sbc	r3, r3, r9
	adds	r0, r2, ip
	adc	r1, r3, ip, asr #31
	subs	r0, r0, sl
	sbc	r1, r1, fp
	bl	__aeabi_ul2d
	fldd	d16, .L118
	fmdrr	d17, r0, r1
	fmuld	d8, d17, d16
	ldr	r1, .L118+36
	ldr	r0, .L118+12
	bl	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	fmrrd	r2, r3, d8
	bl	_ZNSo9_M_insertIdEERSoT_
	ldr	r1, .L118+40
	bl	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	bl	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	ldr	r1, .L118+44
	ldr	r0, .L118+12
	bl	_ZlsRSoRK5matx4
	mov	r0, r4
	add	sp, sp, #20
	fldmfdd	sp!, {d8, d9}
	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
.L119:
	.align	3
.L118:
	.word	-400107883
	.word	1041313291
	.word	.LC1
	.word	_ZSt4cout
	.word	.LANCHOR0
	.word	_ZSt3cin
	.word	.LC2
	.word	.LANCHOR0+64
	.word	.LC3
	.word	.LC4
	.word	.LC5
	.word	.LANCHOR0+128
	.fnend
	.size	main, .-main
	.align	2
	.type	_GLOBAL__sub_I__ZrsRSiR5matx4, %function
_GLOBAL__sub_I__ZrsRSiR5matx4:
	.fnstart
.LFB1026:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	stmfd	sp!, {r4, lr}
	ldr	r4, .L121
	mov	r0, r4
	bl	_ZNSt8ios_base4InitC1Ev
	mov	r0, r4
	movw	r1, #:lower16:_ZNSt8ios_base4InitD1Ev
	movw	r2, #:lower16:__dso_handle
	movt	r1, #:upper16:_ZNSt8ios_base4InitD1Ev
	movt	r2, #:upper16:__dso_handle
	ldmfd	sp!, {r4, lr}
	b	__aeabi_atexit
.L122:
	.align	2
.L121:
	.word	.LANCHOR0+192
	.cantunwind
	.fnend
	.size	_GLOBAL__sub_I__ZrsRSiR5matx4, .-_GLOBAL__sub_I__ZrsRSiR5matx4
	.section	.init_array,"aw",%init_array
	.align	2
	.word	_GLOBAL__sub_I__ZrsRSiR5matx4(target1)
	.global	ra
	.global	ma
	.weakref	_ZL20__gthrw_pthread_oncePiPFvvE,pthread_once
	.weakref	_ZL27__gthrw_pthread_getspecificj,pthread_getspecific
	.weakref	_ZL27__gthrw_pthread_setspecificjPKv,pthread_setspecific
	.weakref	_ZL22__gthrw_pthread_createPmPK14pthread_attr_tPFPvS3_ES3_,pthread_create
	.weakref	_ZL20__gthrw_pthread_joinmPPv,pthread_join
	.weakref	_ZL21__gthrw_pthread_equalmm,pthread_equal
	.weakref	_ZL20__gthrw_pthread_selfv,pthread_self
	.weakref	_ZL22__gthrw_pthread_detachm,pthread_detach
	.weakref	_ZL22__gthrw_pthread_cancelm,pthread_cancel
	.weakref	_ZL19__gthrw_sched_yieldv,sched_yield
	.weakref	_ZL26__gthrw_pthread_mutex_lockP15pthread_mutex_t,pthread_mutex_lock
	.weakref	_ZL29__gthrw_pthread_mutex_trylockP15pthread_mutex_t,pthread_mutex_trylock
	.weakref	_ZL31__gthrw_pthread_mutex_timedlockP15pthread_mutex_tPK8timespec,pthread_mutex_timedlock
	.weakref	_ZL28__gthrw_pthread_mutex_unlockP15pthread_mutex_t,pthread_mutex_unlock
	.weakref	_ZL26__gthrw_pthread_mutex_initP15pthread_mutex_tPK19pthread_mutexattr_t,pthread_mutex_init
	.weakref	_ZL29__gthrw_pthread_mutex_destroyP15pthread_mutex_t,pthread_mutex_destroy
	.weakref	_ZL30__gthrw_pthread_cond_broadcastP14pthread_cond_t,pthread_cond_broadcast
	.weakref	_ZL27__gthrw_pthread_cond_signalP14pthread_cond_t,pthread_cond_signal
	.weakref	_ZL25__gthrw_pthread_cond_waitP14pthread_cond_tP15pthread_mutex_t,pthread_cond_wait
	.weakref	_ZL30__gthrw_pthread_cond_timedwaitP14pthread_cond_tP15pthread_mutex_tPK8timespec,pthread_cond_timedwait
	.weakref	_ZL28__gthrw_pthread_cond_destroyP14pthread_cond_t,pthread_cond_destroy
	.weakref	_ZL26__gthrw_pthread_key_createPjPFvPvE,pthread_key_create
	.weakref	_ZL26__gthrw_pthread_key_deletej,pthread_key_delete
	.weakref	_ZL30__gthrw_pthread_mutexattr_initP19pthread_mutexattr_t,pthread_mutexattr_init
	.weakref	_ZL33__gthrw_pthread_mutexattr_settypeP19pthread_mutexattr_ti,pthread_mutexattr_settype
	.weakref	_ZL33__gthrw_pthread_mutexattr_destroyP19pthread_mutexattr_t,pthread_mutexattr_destroy
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	" \000"
	.space	2
.LC1:
	.ascii	"enter ma0: \000"
.LC2:
	.ascii	"enter ma1: \000"
.LC3:
	.ascii	"enter 1.0: \000"
.LC4:
	.ascii	"elapsed time: \000"
	.space	1
.LC5:
	.ascii	" s\000"
	.bss
	.align	4
.LANCHOR0 = . + 0
	.type	ma, %object
	.size	ma, 128
ma:
	.space	128
	.type	ra, %object
	.size	ra, 64
ra:
	.space	64
	.type	_ZStL8__ioinit, %object
	.size	_ZStL8__ioinit, 1
_ZStL8__ioinit:
	.space	1
	.ident	"GCC: (GNU) 4.6.3"
	.section	.note.GNU-stack,"",%progbits