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-- Company:
-- Engineer: Jonas Otto
--
-- Create Date:    17:16:08 06/01/2015
-- Design Name:
-- Module Name:    transmitter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity transmitter is
    port( CLK : in std_logic;
            RST : in std_logic;
            DIN : in std_logic_vector(7 downto 0);
            SEND : in std_logic;
            TXD : out std_logic;
            LED  : out std_logic_vector (7 downto 0)
    );
end entity;

architecture Behavioral of transmitter is
    type STATE is (STATE_WAIT, STATE_START, STATE_SEND, STATE_STOP);
    signal current_state : STATE;
    signal current_data_bit : integer range 0 to 8;
    signal tickin : std_logic;

    component baud_gen is
        port( CLK : in std_logic;
                RST : in std_logic;
                TICK : out std_logic);
    end component;

begin

ticker: baud_gen
    port map(CLK=>CLK, RST=>RST, TICK=>tickin);

transmit : process(tickin, RST) is
begin


    if (tickin'event and tickin = '1') then
        if RST = '1' then
            current_state <= STATE_WAIT;
            current_data_bit <= 0;
        end if;

        case current_state is
            when STATE_WAIT =>
                TXD <= '1';
                if SEND = '1' then
                    current_state <= STATE_START;
                end if;

            when STATE_START =>
                TXD <= '0'; -- Startbit
                current_state <= STATE_SEND;

            when STATE_SEND =>
                TXD <= din(current_data_bit);
                current_data_bit <= current_data_bit + 1;
                if(current_data_bit > 7) then
                    current_data_bit <= 0;
                    current_state <= STATE_STOP;
                end if;

            when STATE_STOP =>
                TXD <= '1'; --Stopbit
                current_state <= STATE_WAIT;

        end case;

        LED <= DIN;
    end if;

end process;
end architecture;