FSK Generator

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.frame_lib.all;

entity fsk is
    port ( clk : in std_logic;
           rst : in std_logic;
           sine_out : out std_logic_vector(7 downto 0);
           leds : out std_logic_vector(7 downto 0);
           rx : in std_logic);
end fsk;

architecture behave of fsk is

    signal new_frame, last_new_frame : std_logic;
    signal frame : frame_t;
    COMPONENT uart_comms_generic
        GENERIC(
            clk_rate : natural;
            baud_rate: natural
        );
        PORT(
            clk : IN std_logic;
            rst : IN std_logic;
            rx : IN std_logic;
            frame : OUT frame_t;
            new_frame : OUT std_logic
        );
    END COMPONENT;

    type freq_input_type is array(0 to 1) of std_logic_vector(15 downto 0);
    signal pincs : freq_input_type;

    type sine_buffer_type is array(0 to 1) of std_logic_vector(sine_out'range);
    signal sine_buffers : sine_buffer_type;
    COMPONENT fsk_dds
        PORT (
                clk : IN STD_LOGIC;
                pinc_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
                sine : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
        );
    END COMPONENT;

    signal lfsr : std_logic_vector(19 downto 0) := (others => '1');
    signal lfsr_divider : unsigned(31 downto 0) := (others => '0');
    signal symbol : integer range 0 to 1;

begin
    symbol <= 1 when lfsr(0) = '1' else 0;
    sine_out <= std_logic_vector((unsigned(sine_buffers(symbol)) + 127) / 2);
    leds <= lfsr(7 downto 0);

    process(clk, rst)
    begin
        if(rst = '1') then
            lfsr <= (others => '1');
            lfsr_divider <= (others => '0');
        elsif(rising_edge(clk)) then
            if(lfsr_divider = 100_000_000 / 25) then
                lfsr_divider <= (others => '1');
                lfsr <= lfsr(18 downto 0) & ( lfsr(16) xor lfsr(19) );
            else
                lfsr_divider <= lfsr_divider + 1;
            end if;
        end if;
    end process;

    process(clk, rst)
    begin
        if(rst = '1') then
            last_new_frame <= '0';
            pincs(0) <= (others => '0');
            pincs(1) <= (others => '0');
        elsif(rising_edge(clk)) then
            if(new_frame = '1' and last_new_frame = '0') then
                case frame(3) is
                    when x"03" =>
                        pincs(1) <= frame(4) & frame(5);
                    when x"04" =>
                        pincs(0) <= frame(4) & frame(5);
                    when others =>
                        null;
                end case;
            end if;

            last_new_frame <= new_frame;
        end if;
    end process;

    mark_dds : fsk_dds
    PORT MAP (
            clk => clk,
        pinc_in => pincs(1),
        sine => sine_buffers(1)
    );

    space_dds : fsk_dds
    PORT MAP (
            clk => clk,
            pinc_in => pincs(0),
            sine => sine_buffers(0)
    );


    uart_comms_generic_inst : uart_comms_generic
    GENERIC MAP (
        clk_rate  => 100_000_000,
        baud_rate => 500_000)
    PORT MAP(
        clk => clk,
        rst => rst,
        rx => rx,
        frame => frame,
        new_frame => new_frame
    );

end behave;