comp

entity comparator_pe_1_bit is
    port(A,B: in BIT;
    X,Y,Z: out BIT);
end comparator_pe_1_bit;

architecture flux_de_date of comparator_pe_1_bit is
begin
    Y<=A xnor B;           -- A = B
    X<=(not (A))and B;     -- A < B
    Z<=(not(B))and A;      -- A > B
end flux_de_date;

entity modul_comp is
end modul_comp;
architecture arh_mod of modul_comp is
component comparator_pe_1_bit
    port(A,B: in BIT;
    X,Y,Z: out BIT);
end component comparator_pe_1_bit;
signal A,B,X,Y,Z: BIT;
begin
    UST: comparator_pe_1_bit port map(A,B,X,Y,Z);
    A<='0', '1' after 20 ns;
    B<='0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
end arh_mod;