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  1. diff --git a/arch/arm/mach-msm/acpuclock-scorpion.c b/arch/arm/mach-msm/acpuclock-scorpion.c
  2. index 6d79cd7..44e9b60 100644
  3. --- a/arch/arm/mach-msm/acpuclock-scorpion.c
  4. +++ b/arch/arm/mach-msm/acpuclock-scorpion.c
  5. @@ -28,6 +28,7 @@
  6.  
  7. #include "acpuclock.h"
  8. #include "proc_comm.h"
  9. +#include "clock.h"
  10.  
  11. #if 0
  12. #define DEBUG(x...) pr_info(x)
  13. @@ -55,6 +56,7 @@ struct clkctl_acpu_speed {
  14. unsigned sc_l_value;
  15. unsigned lpj;
  16. int vdd;
  17. + unsigned axiclk_khz;
  18. };
  19.  
  20. /* clock sources */
  21. @@ -71,27 +73,28 @@ struct clkctl_acpu_speed {
  22. #define SRC_PLL1 3 /* 768 MHz */
  23.  
  24. struct clkctl_acpu_speed acpu_freq_tbl[] = {
  25. - { 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 1050 },
  26. - { 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 1050 },
  27. - { 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 1050 },
  28. - { 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 1050 },
  29. - { 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 1050 },
  30. - { 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 1050 },
  31. - { 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1050 },
  32. - { 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1075 },
  33. - { 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1100 },
  34. - { 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1100 },
  35. - { 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1125 },
  36. - { 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1150 },
  37. - { 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1175 },
  38. - { 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1200 },
  39. - { 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1200 },
  40. - { 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1225 },
  41. - { 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1250 },
  42. - { 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1275 },
  43. - { 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1275 },
  44. - { 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1275 },
  45. - { 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1275 },
  46. + { 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 1050, 14000},
  47. + { 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 1050, 14000 },
  48. + { 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 1050, 29000 },
  49. + /* Work arround for acpu resume hung, GPLL is turn off by arm9 */
  50. + /*{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 1050, 29000 },*/
  51. + { 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 1050, 58000 },
  52. + { 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 1050, 117000 },
  53. + { 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1050, 117000 },
  54. + { 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1075, 117000 },
  55. + { 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1100, 117000 },
  56. + { 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1100, 117000 },
  57. + { 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1125, 117000 },
  58. + { 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1150, 117000 },
  59. + { 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1175, 117000 },
  60. + { 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1200, 117000 },
  61. + { 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1200, 128000 },
  62. + { 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1225, 128000 },
  63. + { 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1250, 128000 },
  64. + { 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1275, 128000 },
  65. + { 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1300, 128000 },
  66. + { 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1300, 128000 },
  67. + { 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1300, 128000 },
  68. { 0 },
  69. };
  70.  
  71. @@ -152,11 +155,17 @@ struct clock_state {
  72. uint32_t vdd_switch_time_us;
  73. unsigned long power_collapse_khz;
  74. unsigned long wait_for_irq_khz;
  75. + struct clk* clk_ebi1;
  76. struct regulator *regulator;
  77. };
  78.  
  79. static struct clock_state drv_state = { 0 };
  80.  
  81. +
  82. +struct clk *clk_get(struct device *dev, const char *id);
  83. +unsigned long clk_get_rate(struct clk *clk);
  84. +int clk_set_rate(struct clk *clk, unsigned long rate);
  85. +
  86. static DEFINE_SPINLOCK(acpu_lock);
  87.  
  88. #define PLLMODE_POWERDOWN 0
  89. @@ -288,7 +297,7 @@ static int acpuclk_set_vdd_level(int vdd)
  90. return regulator_set_voltage(drv_state.regulator, vdd, vdd);
  91. }
  92.  
  93. -int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
  94. +int acpuclk_set_rate(unsigned long rate, enum setrate_reason reason)
  95. {
  96. struct clkctl_acpu_speed *cur, *next;
  97. unsigned long flags;
  98. @@ -298,9 +307,9 @@ int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
  99. /* convert to KHz */
  100. rate /= 1000;
  101.  
  102. - DEBUG("acpuclk_set_rate(%d,%d)\n", (int) rate, for_power_collapse);
  103. + DEBUG("acpuclk_set_rate(%d,%d)\n", (int) rate, reason);
  104.  
  105. - if (rate == 0 || rate == cur->acpu_khz)
  106. + if (rate == cur->acpu_khz || rate == 0)
  107. return 0;
  108.  
  109. next = acpu_freq_tbl;
  110. @@ -312,7 +321,7 @@ int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
  111. next++;
  112. }
  113.  
  114. - if (!for_power_collapse) {
  115. + if (reason == SETRATE_CPUFREQ) {
  116. mutex_lock(&drv_state.lock);
  117. /* Increase VDD if needed. */
  118. if (next->vdd > cur->vdd) {
  119. @@ -331,6 +340,7 @@ int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
  120. next->clk_sel, next->clk_cfg, next->sc_l_value);
  121.  
  122. if (next->clk_sel == SRC_SCPLL) {
  123. + /* curr -> standby(MPLL speed) -> target */
  124. if (!IS_ACPU_STANDBY(cur))
  125. select_clock(acpu_stby->clk_sel, acpu_stby->clk_cfg);
  126. loops_per_jiffy = next->lpj;
  127. @@ -350,7 +360,16 @@ int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
  128. drv_state.current_speed = next;
  129.  
  130. spin_unlock_irqrestore(&acpu_lock, flags);
  131. - if (!for_power_collapse) {
  132. +
  133. +#ifndef CONFIG_AXI_SCREEN_POLICY
  134. + if (reason == SETRATE_CPUFREQ || reason == SETRATE_PC) {
  135. + if (cur->axiclk_khz != next->axiclk_khz)
  136. + clk_set_rate(drv_state.clk_ebi1, next->axiclk_khz * 1000);
  137. + DEBUG("acpuclk_set_rate switch axi to %d\n",
  138. + clk_get_rate(drv_state.clk_ebi1));
  139. + }
  140. +#endif
  141. + if (reason == SETRATE_CPUFREQ) {
  142. /* Drop VDD level if we can. */
  143. if (next->vdd < cur->vdd) {
  144. if (acpuclk_set_vdd_level(next->vdd))
  145. @@ -384,12 +403,59 @@ static unsigned __init acpuclk_find_speed(void)
  146. #define PCOM_MODEM_PLL 0
  147. static int pll_request(unsigned id, unsigned on)
  148. {
  149. -#if !defined(CONFIG_MSM_AMSS_VERSION_WINCE)
  150. on = !!on;
  151. return msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
  152. -#else
  153. - return 0;
  154. -#endif
  155. +}
  156. +
  157. +/* Spare register populated with efuse data on max ACPU freq. */
  158. +#define CT_CSR_PHYS 0xA8700000
  159. +#define TCSR_SPARE2_ADDR (ct_csr_base + 0x60)
  160. +
  161. +void __init acpu_freq_tbl_fixup(void)
  162. +{
  163. + void __iomem *ct_csr_base;
  164. + uint32_t tcsr_spare2;
  165. + unsigned int max_acpu_khz;
  166. + unsigned int i;
  167. +
  168. + ct_csr_base = ioremap(CT_CSR_PHYS, PAGE_SIZE);
  169. + BUG_ON(ct_csr_base == NULL);
  170. +
  171. + tcsr_spare2 = readl(TCSR_SPARE2_ADDR);
  172. +
  173. + /* Check if the register is supported and meaningful. */
  174. + if ((tcsr_spare2 & 0xF000) != 0xA000) {
  175. + pr_info("Efuse data on Max ACPU freq not present.\n");
  176. + goto skip_efuse_fixup;
  177. + }
  178. +
  179. + switch (tcsr_spare2 & 0xF0) {
  180. + case 0x70:
  181. + max_acpu_khz = 768000;
  182. + break;
  183. + case 0x30:
  184. + case 0x00:
  185. + max_acpu_khz = 998400;
  186. + break;
  187. + case 0x10:
  188. + max_acpu_khz = 1267200;
  189. + break;
  190. + default:
  191. + pr_warning("Invalid efuse data (%x) on Max ACPU freq!\n",
  192. + tcsr_spare2);
  193. + goto skip_efuse_fixup;
  194. + }
  195. +
  196. + pr_info("Max ACPU freq from efuse data is %d KHz\n", max_acpu_khz);
  197. +
  198. + for (i = 0; acpu_freq_tbl[i].acpu_khz != 0; i++) {
  199. + if (acpu_freq_tbl[i].acpu_khz > max_acpu_khz) {
  200. + acpu_freq_tbl[i].acpu_khz = 0;
  201. + break;
  202. + }
  203. + }
  204. +skip_efuse_fixup:
  205. + iounmap(ct_csr_base);
  206. }
  207.  
  208. static void __init acpuclk_init(void)
  209. @@ -458,11 +524,12 @@ uint32_t acpuclk_get_switch_time(void)
  210. return drv_state.acpu_switch_time_us;
  211. }
  212.  
  213. -unsigned long acpuclk_power_collapse(void)
  214. +unsigned long acpuclk_power_collapse(int from_idle)
  215. {
  216. int ret = acpuclk_get_rate();
  217. + enum setrate_reason reason = (from_idle) ? SETRATE_PC_IDLE : SETRATE_PC;
  218. if (ret > drv_state.power_collapse_khz)
  219. - acpuclk_set_rate(drv_state.power_collapse_khz * 1000, 1);
  220. + acpuclk_set_rate(drv_state.power_collapse_khz * 1000, reason);
  221. return ret * 1000;
  222. }
  223.  
  224. @@ -475,7 +542,7 @@ unsigned long acpuclk_wait_for_irq(void)
  225. {
  226. int ret = acpuclk_get_rate();
  227. if (ret > drv_state.wait_for_irq_khz)
  228. - acpuclk_set_rate(drv_state.wait_for_irq_khz * 1000, 1);
  229. + acpuclk_set_rate(drv_state.wait_for_irq_khz * 1000, SETRATE_SWFI);
  230. return ret * 1000;
  231. }
  232.  
  233. @@ -493,6 +560,11 @@ void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
  234. if (clkdata->mpll_khz)
  235. acpu_mpll->acpu_khz = clkdata->mpll_khz;
  236.  
  237. + acpu_freq_tbl_fixup();
  238. acpuclk_init();
  239. acpuclk_init_cpufreq_table();
  240. + drv_state.clk_ebi1 = clk_get(NULL,"ebi1_clk");
  241. +#ifndef CONFIG_AXI_SCREEN_POLICY
  242. + clk_set_rate(drv_state.clk_ebi1, drv_state.current_speed->axiclk_khz * 1000);
  243. +#endif
  244. }
  245. diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h
  246. index 415de2e..97fcb4f 100644
  247. --- a/arch/arm/mach-msm/acpuclock.h
  248. +++ b/arch/arm/mach-msm/acpuclock.h
  249. @@ -20,11 +20,23 @@
  250. #ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
  251. #define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
  252.  
  253. -int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
  254. +enum setrate_reason {
  255. + SETRATE_CPUFREQ = 0,
  256. + SETRATE_SWFI,
  257. + SETRATE_PC,
  258. + SETRATE_PC_IDLE,
  259. +};
  260. +
  261. +#if defined(CONFIG_ARCH_MSM_SCORPION)
  262. +int acpuclk_set_rate(unsigned long rate, enum setrate_reason reason);
  263. +unsigned long acpuclk_power_collapse(int from_idle);
  264. +#else
  265. +int acpuclk_set_rate(unsigned long rate, enum setrate_reason reason);
  266. +unsigned long acpuclk_power_collapse(int from_idle);
  267. +#endif
  268. unsigned long acpuclk_get_rate(void);
  269. uint32_t acpuclk_get_switch_time(void);
  270. unsigned long acpuclk_wait_for_irq(void);
  271. -unsigned long acpuclk_power_collapse(void);
  272. unsigned long acpuclk_get_wfi_rate(void);
  273.  
  274.  
  275. diff --git a/arch/arm/mach-msm/include/mach/msm_smd.h b/arch/arm/mach-msm/include/mach/msm_smd.h
  276. index 2e56b82..d9418ba 100644
  277. --- a/arch/arm/mach-msm/include/mach/msm_smd.h
  278. +++ b/arch/arm/mach-msm/include/mach/msm_smd.h
  279. @@ -54,7 +54,6 @@ int smd_cur_packet_size(smd_channel_t *ch);
  280. */
  281. void smd_kick(smd_channel_t *ch);
  282.  
  283. -
  284. #if 0
  285. /* these are interruptable waits which will block you until the specified
  286. ** number of bytes are readable or writable.
  287. @@ -62,6 +61,7 @@ void smd_kick(smd_channel_t *ch);
  288. int smd_wait_until_readable(smd_channel_t *ch, int bytes);
  289. int smd_wait_until_writable(smd_channel_t *ch, int bytes);
  290. #endif
  291. +int smd_wait_until_opened(smd_channel_t *ch, int timeout_us);
  292.  
  293. typedef enum
  294. {
  295. @@ -105,11 +105,18 @@ typedef enum
  296. SMD_NUM_PORTS,
  297. } smd_port_id_type;
  298.  
  299. -struct smd_tty_channel_desc {
  300. - int id;
  301. - const char *name;
  302. +#if defined(CONFIG_MSM_N_WAY_SMD)
  303. +enum
  304. +{
  305. + SMD_APPS_MODEM = 0,
  306. + SMD_APPS_QDSP,
  307. + SMD_MODEM_QDSP
  308. };
  309. -
  310. -int smd_set_channel_list(const struct smd_tty_channel_desc *, int len);
  311. +#else
  312. +enum
  313. +{
  314. + SMD_APPS_MODEM = 0
  315. +};
  316. +#endif
  317.  
  318. #endif
  319. diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
  320. index 57de269..4b4a044 100644
  321. --- a/arch/arm/mach-msm/irq.c
  322. +++ b/arch/arm/mach-msm/irq.c
  323. @@ -43,19 +43,38 @@ static int msm_irq_debug_mask;
  324. module_param_named(debug_mask, msm_irq_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
  325.  
  326. #define VIC_REG(off) (MSM_VIC_BASE + (off))
  327. +#if defined(CONFIG_ARCH_MSM7X30)
  328. +#define VIC_INT_TO_REG_ADDR(base, irq) (base + (irq / 32) * 4)
  329. +#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 3)
  330. +#else
  331. +#define VIC_INT_TO_REG_ADDR(base, irq) (base + ((irq & 32) ? 4 : 0))
  332. +#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 1)
  333. +#endif
  334.  
  335. #define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
  336. #define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
  337. +#define VIC_INT_SELECT2 VIC_REG(0x0008) /* 1: FIQ, 0: IRQ */
  338. +#define VIC_INT_SELECT3 VIC_REG(0x000C) /* 1: FIQ, 0: IRQ */
  339. #define VIC_INT_EN0 VIC_REG(0x0010)
  340. #define VIC_INT_EN1 VIC_REG(0x0014)
  341. +#define VIC_INT_EN2 VIC_REG(0x0018)
  342. +#define VIC_INT_EN3 VIC_REG(0x001C)
  343. #define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
  344. #define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
  345. +#define VIC_INT_ENCLEAR2 VIC_REG(0x0028)
  346. +#define VIC_INT_ENCLEAR3 VIC_REG(0x002C)
  347. #define VIC_INT_ENSET0 VIC_REG(0x0030)
  348. #define VIC_INT_ENSET1 VIC_REG(0x0034)
  349. +#define VIC_INT_ENSET2 VIC_REG(0x0038)
  350. +#define VIC_INT_ENSET3 VIC_REG(0x003C)
  351. #define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
  352. #define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
  353. +#define VIC_INT_TYPE2 VIC_REG(0x0048) /* 1: EDGE, 0: LEVEL */
  354. +#define VIC_INT_TYPE3 VIC_REG(0x004C) /* 1: EDGE, 0: LEVEL */
  355. #define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
  356. #define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
  357. +#define VIC_INT_POLARITY2 VIC_REG(0x0058) /* 1: NEG, 0: POS */
  358. +#define VIC_INT_POLARITY3 VIC_REG(0x005C) /* 1: NEG, 0: POS */
  359. #define VIC_NO_PEND_VAL VIC_REG(0x0060)
  360.  
  361. #if defined(CONFIG_ARCH_MSM_SCORPION)
  362. @@ -69,14 +88,24 @@ module_param_named(debug_mask, msm_irq_debug_mask, int, S_IRUGO | S_IWUSR | S_IW
  363. #endif
  364. #define VIC_IRQ_STATUS0 VIC_REG(0x0080)
  365. #define VIC_IRQ_STATUS1 VIC_REG(0x0084)
  366. +#define VIC_IRQ_STATUS2 VIC_REG(0x0088)
  367. +#define VIC_IRQ_STATUS3 VIC_REG(0x008C)
  368. #define VIC_FIQ_STATUS0 VIC_REG(0x0090)
  369. #define VIC_FIQ_STATUS1 VIC_REG(0x0094)
  370. +#define VIC_FIQ_STATUS2 VIC_REG(0x0098)
  371. +#define VIC_FIQ_STATUS3 VIC_REG(0x009C)
  372. #define VIC_RAW_STATUS0 VIC_REG(0x00A0)
  373. #define VIC_RAW_STATUS1 VIC_REG(0x00A4)
  374. +#define VIC_RAW_STATUS2 VIC_REG(0x00A8)
  375. +#define VIC_RAW_STATUS3 VIC_REG(0x00AC)
  376. #define VIC_INT_CLEAR0 VIC_REG(0x00B0)
  377. #define VIC_INT_CLEAR1 VIC_REG(0x00B4)
  378. +#define VIC_INT_CLEAR2 VIC_REG(0x00B8)
  379. +#define VIC_INT_CLEAR3 VIC_REG(0x00BC)
  380. #define VIC_SOFTINT0 VIC_REG(0x00C0)
  381. #define VIC_SOFTINT1 VIC_REG(0x00C4)
  382. +#define VIC_SOFTINT2 VIC_REG(0x00C8)
  383. +#define VIC_SOFTINT3 VIC_REG(0x00CC)
  384. #define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
  385. #define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
  386. #define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
  387. @@ -100,21 +129,47 @@ module_param_named(debug_mask, msm_irq_debug_mask, int, S_IRUGO | S_IWUSR | S_IW
  388. #define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
  389. #define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
  390.  
  391. +#if defined(CONFIG_ARCH_MSM7X30)
  392. +#define VIC_NUM_REGS 4
  393. +#else
  394. +#define VIC_NUM_REGS 2
  395. +#endif
  396. +
  397. +#if VIC_NUM_REGS == 2
  398. +#define DPRINT_REGS(base_reg, format, ...) \
  399. + printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
  400. + readl(base_reg ## 0), readl(base_reg ## 1))
  401. +#define DPRINT_ARRAY(array, format, ...) \
  402. + printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
  403. + array[0], array[1])
  404. +#elif VIC_NUM_REGS == 4
  405. +#define DPRINT_REGS(base_reg, format, ...) \
  406. + printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
  407. + readl(base_reg ## 0), readl(base_reg ## 1), \
  408. + readl(base_reg ## 2), readl(base_reg ## 3))
  409. +#define DPRINT_ARRAY(array, format, ...) \
  410. + printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
  411. + array[0], array[1], \
  412. + array[2], array[3])
  413. +#else
  414. +#error "VIC_NUM_REGS set to illegal value"
  415. +#endif
  416. +
  417. static uint32_t msm_irq_smsm_wake_enable[2];
  418. static struct {
  419. uint32_t int_en[2];
  420. uint32_t int_type;
  421. uint32_t int_polarity;
  422. uint32_t int_select;
  423. -} msm_irq_shadow_reg[2];
  424. -static uint32_t msm_irq_idle_disable[2];
  425. +} msm_irq_shadow_reg[VIC_NUM_REGS];
  426. +static uint32_t msm_irq_idle_disable[VIC_NUM_REGS];
  427.  
  428. -#ifndef CONFIG_ARCH_MSM_SCORPION
  429. -#define INT_INFO_SMSM_ID SMEM_SMSM_INT_INFO
  430. -struct smsm_interrupt_info *smsm_int_info;
  431. -#else
  432. +#if defined(CONFIG_MSM_N_WAY_SMD)
  433. #define INT_INFO_SMSM_ID SMEM_APPS_DEM_SLAVE_DATA
  434. struct msm_dem_slave_data *smsm_int_info;
  435. +#else
  436. +#define INT_INFO_SMSM_ID SMEM_SMSM_INT_INFO
  437. +struct smsm_interrupt_info *smsm_int_info;
  438. #endif
  439.  
  440.  
  441. @@ -143,7 +198,9 @@ static uint8_t msm_irq_to_smsm[NR_MSM_IRQS + NR_SIRC_IRQS] = {
  442. [INT_UART1DM_IRQ] = 17,
  443. [INT_UART1DM_RX] = 18,
  444. [INT_KEYSENSE] = 19,
  445. +#if !defined(CONFIG_ARCH_MSM7X30)
  446. [INT_AD_HSSD] = 20,
  447. +#endif
  448.  
  449. [INT_NAND_WR_ER_DONE] = 21,
  450. [INT_NAND_OP_DONE] = 22,
  451. @@ -168,25 +225,32 @@ static uint8_t msm_irq_to_smsm[NR_MSM_IRQS + NR_SIRC_IRQS] = {
  452. [INT_A9_M2A_5] = SMSM_FAKE_IRQ,
  453. [INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ,
  454. [INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ,
  455. - [INT_AD6_EXT_VFR] = SMSM_FAKE_IRQ,
  456. [INT_ADSP_A11] = SMSM_FAKE_IRQ,
  457. -#ifdef CONFIG_ARCH_MSM_SCORPION
  458. +#ifdef CONFIG_ARCH_QSD8X50
  459. [INT_SIRC_0] = SMSM_FAKE_IRQ,
  460. [INT_SIRC_1] = SMSM_FAKE_IRQ,
  461. #endif
  462. };
  463.  
  464. +static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
  465. +{
  466. + int i;
  467. + /* the address must be continue */
  468. + for (i = 0; i < VIC_NUM_REGS; i++)
  469. + writel(val, base + (i * 4));
  470. +}
  471. +
  472. static void msm_irq_ack(unsigned int irq)
  473. {
  474. - void __iomem *reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0);
  475. + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq);
  476. irq = 1 << (irq & 31);
  477. writel(irq, reg);
  478. }
  479.  
  480. static void msm_irq_mask(unsigned int irq)
  481. {
  482. - void __iomem *reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0);
  483. - unsigned index = (irq >> 5) & 1;
  484. + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq);
  485. + unsigned index = VIC_INT_TO_REG_INDEX(irq);
  486. uint32_t mask = 1UL << (irq & 31);
  487. int smsm_irq = msm_irq_to_smsm[irq];
  488.  
  489. @@ -202,8 +266,8 @@ static void msm_irq_mask(unsigned int irq)
  490.  
  491. static void msm_irq_unmask(unsigned int irq)
  492. {
  493. - void __iomem *reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0);
  494. - unsigned index = (irq >> 5) & 1;
  495. + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq);
  496. + unsigned index = VIC_INT_TO_REG_INDEX(irq);
  497. uint32_t mask = 1UL << (irq & 31);
  498. int smsm_irq = msm_irq_to_smsm[irq];
  499.  
  500. @@ -220,7 +284,7 @@ static void msm_irq_unmask(unsigned int irq)
  501.  
  502. static int msm_irq_set_wake(unsigned int irq, unsigned int on)
  503. {
  504. - unsigned index = (irq >> 5) & 1;
  505. + unsigned index = VIC_INT_TO_REG_INDEX(irq);
  506. uint32_t mask = 1UL << (irq & 31);
  507. int smsm_irq = msm_irq_to_smsm[irq];
  508.  
  509. @@ -246,9 +310,9 @@ static int msm_irq_set_wake(unsigned int irq, unsigned int on)
  510.  
  511. static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
  512. {
  513. - void __iomem *treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0);
  514. - void __iomem *preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0);
  515. - unsigned index = (irq >> 5) & 1;
  516. + void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq);
  517. + void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq);
  518. + unsigned index = VIC_INT_TO_REG_INDEX(irq);
  519. int b = 1 << (irq & 31);
  520. uint32_t polarity;
  521. uint32_t type;
  522. @@ -277,16 +341,24 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
  523.  
  524. int msm_irq_pending(void)
  525. {
  526. - return readl(VIC_IRQ_STATUS0) || readl(VIC_IRQ_STATUS1);
  527. + int i, pending = 0;
  528. + /* the address must be continue */
  529. + for (i = 0; (i < VIC_NUM_REGS) && !pending; i++)
  530. + pending |= readl(VIC_IRQ_STATUS0 + (i * 4));
  531. +
  532. + return pending;
  533. }
  534.  
  535. int msm_irq_idle_sleep_allowed(void)
  536. {
  537. + int i, disable = 0;
  538. +
  539. if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_REQUEST)
  540. - printk(KERN_INFO "msm_irq_idle_sleep_allowed: disable %x %x\n",
  541. - msm_irq_idle_disable[0], msm_irq_idle_disable[1]);
  542. - return !(msm_irq_idle_disable[0] || msm_irq_idle_disable[1] ||
  543. - !smsm_int_info);
  544. + DPRINT_ARRAY(msm_irq_idle_disable,
  545. + "msm_irq_idle_sleep_allowed: disable");
  546. + for (i = 0; i < VIC_NUM_REGS; i++)
  547. + disable |= msm_irq_idle_disable[i];
  548. + return !(disable || !smsm_int_info);
  549. }
  550.  
  551. /* If arm9_wake is set: pass control to the other core.
  552. @@ -302,8 +374,8 @@ void msm_irq_enter_sleep1(bool arm9_wake, int from_idle)
  553.  
  554. int msm_irq_enter_sleep2(bool arm9_wake, int from_idle)
  555. {
  556. - int limit = 10;
  557. - uint32_t pending0, pending1;
  558. + int i, limit = 10;
  559. + uint32_t pending[VIC_NUM_REGS];
  560.  
  561. if (from_idle && !arm9_wake)
  562. return 0;
  563. @@ -312,23 +384,25 @@ int msm_irq_enter_sleep2(bool arm9_wake, int from_idle)
  564. WARN_ON_ONCE(!arm9_wake && !from_idle);
  565.  
  566. if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
  567. - printk(KERN_INFO "msm_irq_enter_sleep change irq, pend %x %x\n",
  568. - readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
  569. - pending0 = readl(VIC_IRQ_STATUS0);
  570. - pending1 = readl(VIC_IRQ_STATUS1);
  571. - pending0 &= msm_irq_shadow_reg[0].int_en[!from_idle];
  572. + DPRINT_REGS(VIC_IRQ_STATUS, "%s change irq, pend", __func__);
  573. +
  574. + for (i = 0; i < VIC_NUM_REGS; i++) {
  575. + pending[i] = readl(VIC_IRQ_STATUS0 + (i * 4));
  576. + pending[i] &= msm_irq_shadow_reg[i].int_en[!from_idle];
  577. + }
  578. /* Clear INT_A9_M2A_5 since requesting sleep triggers it */
  579. - pending0 &= ~(1U << INT_A9_M2A_5);
  580. - pending1 &= msm_irq_shadow_reg[1].int_en[!from_idle];
  581. - if (pending0 || pending1) {
  582. - if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT)
  583. - printk(KERN_INFO "msm_irq_enter_sleep2 abort %x %x\n",
  584. - pending0, pending1);
  585. - return -EAGAIN;
  586. + pending[0] &= ~(1U << INT_A9_M2A_5);
  587. +
  588. + for (i = 0; i < VIC_NUM_REGS; i++) {
  589. + if (pending[i]) {
  590. + if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT)
  591. + DPRINT_ARRAY(pending, "%s abort",
  592. + __func__);
  593. + return -EAGAIN;
  594. + }
  595. }
  596.  
  597. - writel(0, VIC_INT_EN0);
  598. - writel(0, VIC_INT_EN1);
  599. + msm_irq_write_all_regs(VIC_INT_EN0, 0);
  600.  
  601. while (limit-- > 0) {
  602. int pend_irq;
  603. @@ -346,8 +420,9 @@ int msm_irq_enter_sleep2(bool arm9_wake, int from_idle)
  604. msm_irq_ack(INT_A9_M2A_6);
  605. writel(1U << INT_A9_M2A_6, VIC_INT_ENSET0);
  606. } else {
  607. - writel(msm_irq_shadow_reg[0].int_en[1], VIC_INT_ENSET0);
  608. - writel(msm_irq_shadow_reg[1].int_en[1], VIC_INT_ENSET1);
  609. + for (i = 0; i < VIC_NUM_REGS; i++)
  610. + writel(msm_irq_shadow_reg[i].int_en[1],
  611. + VIC_INT_ENSET0 + (i * 4));
  612. }
  613. return 0;
  614. }
  615. @@ -358,7 +433,7 @@ void msm_irq_exit_sleep1(void)
  616.  
  617. msm_irq_ack(INT_A9_M2A_6);
  618. msm_irq_ack(INT_PWB_I2C);
  619. - for (i = 0; i < 2; i++) {
  620. + for (i = 0; i < VIC_NUM_REGS; i++) {
  621. writel(msm_irq_shadow_reg[i].int_type, VIC_INT_TYPE0 + i * 4);
  622. writel(msm_irq_shadow_reg[i].int_polarity, VIC_INT_POLARITY0 + i * 4);
  623. writel(msm_irq_shadow_reg[i].int_en[0], VIC_INT_EN0 + i * 4);
  624. @@ -452,20 +527,16 @@ void __init msm_init_irq(void)
  625. unsigned n;
  626.  
  627. /* select level interrupts */
  628. - writel(0, VIC_INT_TYPE0);
  629. - writel(0, VIC_INT_TYPE1);
  630. + msm_irq_write_all_regs(VIC_INT_TYPE0, 0);
  631.  
  632. /* select highlevel interrupts */
  633. - writel(0, VIC_INT_POLARITY0);
  634. - writel(0, VIC_INT_POLARITY1);
  635. + msm_irq_write_all_regs(VIC_INT_POLARITY0, 0);
  636.  
  637. /* select IRQ for all INTs */
  638. - writel(0, VIC_INT_SELECT0);
  639. - writel(0, VIC_INT_SELECT1);
  640. + msm_irq_write_all_regs(VIC_INT_SELECT0, 0);
  641.  
  642. /* disable all INTs */
  643. - writel(0, VIC_INT_EN0);
  644. - writel(0, VIC_INT_EN1);
  645. + msm_irq_write_all_regs(VIC_INT_EN0, 0);
  646.  
  647. /* don't use 1136 vic */
  648. writel(0, VIC_CONFIG);
  649. @@ -494,7 +565,7 @@ late_initcall(msm_init_irq_late);
  650. #if defined(CONFIG_MSM_FIQ_SUPPORT)
  651. void msm_trigger_irq(int irq)
  652. {
  653. - void __iomem *reg = VIC_SOFTINT0 + ((irq & 32) ? 4 : 0);
  654. + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_SOFTINT0, irq);
  655. uint32_t mask = 1UL << (irq & 31);
  656. writel(mask, reg);
  657. }
  658. @@ -517,8 +588,8 @@ void msm_fiq_disable(int irq)
  659.  
  660. static void _msm_fiq_select(int irq)
  661. {
  662. - void __iomem *reg = VIC_INT_SELECT0 + ((irq & 32) ? 4 : 0);
  663. - unsigned index = (irq >> 5) & 1;
  664. + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_SELECT0, irq);
  665. + unsigned index = VIC_INT_TO_REG_INDEX(irq);
  666. uint32_t mask = 1UL << (irq & 31);
  667. unsigned long flags;
  668.  
  669. @@ -530,8 +601,8 @@ static void _msm_fiq_select(int irq)
  670.  
  671. static void _msm_fiq_unselect(int irq)
  672. {
  673. - void __iomem *reg = VIC_INT_SELECT0 + ((irq & 32) ? 4 : 0);
  674. - unsigned index = (irq >> 5) & 1;
  675. + void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_SELECT0, irq);
  676. + unsigned index = VIC_INT_TO_REG_INDEX(irq);
  677. uint32_t mask = 1UL << (irq & 31);
  678. unsigned long flags;
  679.  
  680. diff --git a/arch/arm/mach-msm/pm.c b/arch/arm/mach-msm/pm.c
  681. index 6f1614d..bfcf7b5 100644
  682. --- a/arch/arm/mach-msm/pm.c
  683. +++ b/arch/arm/mach-msm/pm.c
  684. @@ -29,26 +29,24 @@
  685. #include <mach/msm_iomap.h>
  686. #include <mach/system.h>
  687. #include <asm/io.h>
  688. +#ifdef CONFIG_VFP
  689. +#include <asm/vfp.h>
  690. +#endif
  691. +
  692. +#ifdef CONFIG_CACHE_L2X0
  693. +#include <asm/hardware/cache-l2x0.h>
  694. +#endif
  695.  
  696. #include "smd_private.h"
  697. +#include "smd_rpcrouter.h"
  698. #include "acpuclock.h"
  699. -
  700. +#include "proc_comm.h"
  701. #include "clock.h"
  702. +#include "spm.h"
  703. #ifdef CONFIG_HAS_WAKELOCK
  704. #include <linux/wakelock.h>
  705. #endif
  706.  
  707. -#include "dex_comm.h"
  708. -
  709. -/*
  710. -#if defined(CONFIG_MSM_AMSS_VERSION_WINCE)
  711. -
  712. -#else
  713. -#include "proc_comm.h"
  714. -#endif
  715. -*/
  716. -
  717. -
  718. enum {
  719. MSM_PM_DEBUG_SUSPEND = 1U << 0,
  720. MSM_PM_DEBUG_POWER_COLLAPSE = 1U << 1,
  721. @@ -57,9 +55,10 @@ enum {
  722. MSM_PM_DEBUG_RESET_VECTOR = 1U << 4,
  723. MSM_PM_DEBUG_SMSM_STATE = 1U << 5,
  724. MSM_PM_DEBUG_IDLE = 1U << 6,
  725. - MSM_PM_DEBUG_CLOCK_VOTE = 1U << 7
  726. + MSM_PM_DEBUG_SLEEP_LIMIT = 1U << 7,
  727. + MSM_PM_DEBUG_WAKEUP_REASON = 1U << 8,
  728. };
  729. -static int msm_pm_debug_mask = MSM_PM_DEBUG_CLOCK_VOTE;
  730. +static int msm_pm_debug_mask = MSM_PM_DEBUG_SLEEP_LIMIT | MSM_PM_DEBUG_WAKEUP_REASON;
  731. module_param_named(debug_mask, msm_pm_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
  732.  
  733. enum {
  734. @@ -78,12 +77,18 @@ module_param_named(idle_sleep_min_time, msm_pm_idle_sleep_min_time, int, S_IRUGO
  735. static int msm_pm_idle_spin_time = CONFIG_MSM7X00A_IDLE_SPIN_TIME;
  736. module_param_named(idle_spin_time, msm_pm_idle_spin_time, int, S_IRUGO | S_IWUSR | S_IWGRP);
  737.  
  738. +#if defined (CONFIG_ARCH_MSM7X30)
  739. +#define A11S_CLK_SLEEP_EN (MSM_GCC_BASE + 0x020)
  740. +#define A11S_PWRDOWN (MSM_ACC_BASE + 0x01C)
  741. +#define A11S_SECOP (MSM_TCSR_BASE + 0x38)
  742. +#else
  743. #define A11S_CLK_SLEEP_EN (MSM_CSR_BASE + 0x11c)
  744. #define A11S_PWRDOWN (MSM_CSR_BASE + 0x440)
  745. #define A11S_STANDBY_CTL (MSM_CSR_BASE + 0x108)
  746. +#endif
  747. #define A11RAMBACKBIAS (MSM_CSR_BASE + 0x508)
  748.  
  749. -
  750. +#if defined(CONFIG_MSM_N_WAY_SMD)
  751. #define DEM_MASTER_BITS_PER_CPU 6
  752.  
  753. /* Power Master State Bits - Per CPU */
  754. @@ -112,18 +117,17 @@ module_param_named(idle_spin_time, msm_pm_idle_spin_time, int, S_IRUGO | S_IWUSR
  755. #define DEM_SLAVE_SMSM_RESET (0x0100)
  756. #define DEM_SLAVE_SMSM_PWRC_SUSPEND (0x0200)
  757.  
  758. -#ifndef CONFIG_ARCH_MSM_SCORPION
  759. -#define PM_SMSM_WRITE_STATE SMSM_STATE_APPS
  760. -#define PM_SMSM_READ_STATE SMSM_STATE_MODEM
  761. -
  762. -#define PM_SMSM_WRITE_RUN SMSM_RUN
  763. -#define PM_SMSM_READ_RUN SMSM_RUN
  764. -#else
  765. #define PM_SMSM_WRITE_STATE SMSM_STATE_APPS_DEM
  766. #define PM_SMSM_READ_STATE SMSM_STATE_POWER_MASTER_DEM
  767.  
  768. #define PM_SMSM_WRITE_RUN DEM_SLAVE_SMSM_RUN
  769. #define PM_SMSM_READ_RUN DEM_MASTER_SMSM_RUN
  770. +#else
  771. +#define PM_SMSM_WRITE_STATE SMSM_STATE_APPS
  772. +#define PM_SMSM_READ_STATE SMSM_STATE_MODEM
  773. +
  774. +#define PM_SMSM_WRITE_RUN SMSM_RUN
  775. +#define PM_SMSM_READ_RUN SMSM_RUN
  776. #endif
  777.  
  778. int msm_pm_collapse(void);
  779. @@ -134,7 +138,11 @@ int64_t msm_timer_enter_idle(void);
  780. void msm_timer_exit_idle(int low_power);
  781. int msm_irq_idle_sleep_allowed(void);
  782. int msm_irq_pending(void);
  783. -int clks_print_running(void);
  784. +int clks_allow_tcxo_locked_debug(void);
  785. +extern int board_mfg_mode(void);
  786. +extern char * board_get_mfg_sleep_gpio_table(void);
  787. +extern void gpio_set_diag_gpio_table(unsigned long * dwMFG_gpio_table);
  788. +extern void wait_rmt_final_call_back(int timeout);
  789.  
  790. static int axi_rate;
  791. static int sleep_axi_rate;
  792. @@ -212,12 +220,32 @@ msm_pm_wait_state(uint32_t wait_all_set, uint32_t wait_all_clear,
  793. return -ETIMEDOUT;
  794. }
  795.  
  796. +/*
  797. + * For speeding up boot time:
  798. + * During booting up, disable entering arch_idle() by disable_hlt()
  799. + * Enable it after booting up BOOT_LOCK_TIMEOUT sec.
  800. + */
  801. +#define BOOT_LOCK_TIMEOUT (60 * HZ)
  802. +static void do_expire_boot_lock(struct work_struct *work)
  803. +{
  804. + enable_hlt();
  805. + pr_info("Release 'boot-time' halt_lock\n");
  806. +}
  807. +static DECLARE_DELAYED_WORK(work_expire_boot_lock, do_expire_boot_lock);
  808. +
  809. #ifdef CONFIG_MSM_FIQ_SUPPORT
  810. void msm_fiq_exit_sleep(void);
  811. #else
  812. static inline void msm_fiq_exit_sleep(void) { }
  813. #endif
  814.  
  815. +#ifdef CONFIG_HTC_POWER_COLLAPSE_MAGIC
  816. +/* Set magic number in SMEM for power collapse state */
  817. +#define HTC_POWER_COLLAPSE_ADD (MSM_SHARED_RAM_BASE + 0x000F8000 + 0x000007F8)
  818. +#define HTC_POWER_COLLAPSE_MAGIC_NUM (HTC_POWER_COLLAPSE_ADD - 0x04)
  819. +unsigned int magic_num;
  820. +#endif
  821. +
  822. static int msm_sleep(int sleep_mode, uint32_t sleep_delay, int from_idle)
  823. {
  824. uint32_t saved_vector[2];
  825. @@ -241,34 +269,13 @@ static int msm_sleep(int sleep_mode, uint32_t sleep_delay, int from_idle)
  826. int rv = -EINTR;
  827. bool invalid_inital_state = false;
  828.  
  829. + if (board_mfg_mode() == 4) /*power test mode*/
  830. + gpio_set_diag_gpio_table(board_get_mfg_sleep_gpio_table());
  831. +
  832. if (msm_pm_debug_mask & MSM_PM_DEBUG_SUSPEND)
  833. printk(KERN_INFO "msm_sleep(): mode %d delay %u idle %d\n",
  834. sleep_mode, sleep_delay, from_idle);
  835. -
  836. -#ifndef CONFIG_ARCH_MSM_SCORPION
  837. - switch (sleep_mode) {
  838. - case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
  839. - enter_state = SMSM_PWRC;
  840. - enter_wait_set = SMSM_RSA;
  841. - exit_state = SMSM_WFPI;
  842. - exit_wait_clear = SMSM_RSA;
  843. - break;
  844. - case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_SUSPEND:
  845. - enter_state = SMSM_PWRC_SUSPEND;
  846. - enter_wait_set = SMSM_RSA;
  847. - exit_state = SMSM_WFPI;
  848. - exit_wait_clear = SMSM_RSA;
  849. - break;
  850. - case MSM_PM_SLEEP_MODE_APPS_SLEEP:
  851. - enter_state = SMSM_SLEEP;
  852. - exit_state = SMSM_SLEEPEXIT;
  853. - exit_wait_any_set = SMSM_SLEEPEXIT;
  854. - break;
  855. - default:
  856. - enter_state = 0;
  857. - exit_state = 0;
  858. - }
  859. -#else
  860. +#if defined(CONFIG_MSM_N_WAY_SMD)
  861. switch (sleep_mode) {
  862. case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
  863. enter_state = DEM_SLAVE_SMSM_PWRC;
  864. @@ -294,8 +301,30 @@ static int msm_sleep(int sleep_mode, uint32_t sleep_delay, int from_idle)
  865. enter_state = 0;
  866. exit_state = 0;
  867. }
  868. +#else
  869. + switch (sleep_mode) {
  870. + case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
  871. + enter_state = SMSM_PWRC;
  872. + enter_wait_set = SMSM_RSA;
  873. + exit_state = SMSM_WFPI;
  874. + exit_wait_clear = SMSM_RSA;
  875. + break;
  876. + case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_SUSPEND:
  877. + enter_state = SMSM_PWRC_SUSPEND;
  878. + enter_wait_set = SMSM_RSA;
  879. + exit_state = SMSM_WFPI;
  880. + exit_wait_clear = SMSM_RSA;
  881. + break;
  882. + case MSM_PM_SLEEP_MODE_APPS_SLEEP:
  883. + enter_state = SMSM_SLEEP;
  884. + exit_state = SMSM_SLEEPEXIT;
  885. + exit_wait_any_set = SMSM_SLEEPEXIT;
  886. + break;
  887. + default:
  888. + enter_state = 0;
  889. + exit_state = 0;
  890. + }
  891. #endif
  892. -
  893. clk_enter_sleep(from_idle);
  894. msm_irq_enter_sleep1(!!enter_state, from_idle);
  895. msm_gpio_enter_sleep(from_idle);
  896. @@ -316,9 +345,9 @@ static int msm_sleep(int sleep_mode, uint32_t sleep_delay, int from_idle)
  897. enter_state = 0;
  898. exit_state = 0;
  899. }
  900. - if ((!from_idle && (msm_pm_debug_mask & MSM_PM_DEBUG_CLOCK_VOTE)) ||
  901. - (from_idle && (msm_pm_debug_mask & MSM_PM_DEBUG_IDLE)))
  902. - clks_print_running();
  903. + if ((!from_idle && msm_pm_debug_mask & MSM_PM_DEBUG_SLEEP_LIMIT) ||
  904. + (from_idle && msm_pm_debug_mask & MSM_PM_DEBUG_IDLE))
  905. + clks_allow_tcxo_locked_debug();
  906.  
  907. ret = smsm_change_state(PM_SMSM_WRITE_STATE, PM_SMSM_WRITE_RUN, enter_state);
  908. if (ret) {
  909. @@ -336,15 +365,16 @@ static int msm_sleep(int sleep_mode, uint32_t sleep_delay, int from_idle)
  910. goto enter_failed;
  911.  
  912. if (enter_state) {
  913. -#ifdef CONFIG_ARCH_MSM_SCORPION
  914. - writel(0x1b, A11S_CLK_SLEEP_EN);
  915. +#if defined (CONFIG_ARCH_MSM7X30)
  916. + writel(1, A11S_PWRDOWN);
  917. + writel(4, A11S_SECOP);
  918. #else
  919. writel(0x1f, A11S_CLK_SLEEP_EN);
  920. -#endif
  921. writel(1, A11S_PWRDOWN);
  922.  
  923. writel(0, A11S_STANDBY_CTL);
  924. -#ifndef CONFIG_ARCH_MSM_SCORPION
  925. +#endif
  926. +#if !defined(CONFIG_MSM_N_WAY_SMD)
  927. writel(0, A11RAMBACKBIAS);
  928. #endif
  929.  
  930. @@ -356,20 +386,26 @@ static int msm_sleep(int sleep_mode, uint32_t sleep_delay, int from_idle)
  931. }
  932.  
  933. if (sleep_mode <= MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT) {
  934. - pm_saved_acpu_clk_rate = acpuclk_power_collapse();
  935. + pm_saved_acpu_clk_rate = acpuclk_power_collapse(from_idle);
  936. if (msm_pm_debug_mask & MSM_PM_DEBUG_CLOCK)
  937. printk(KERN_INFO "msm_sleep(): %ld enter power collapse"
  938. "\n", pm_saved_acpu_clk_rate);
  939. if (pm_saved_acpu_clk_rate == 0)
  940. goto ramp_down_failed;
  941.  
  942. +#ifdef CONFIG_AXI_SCREEN_POLICY
  943. /* Drop AXI request when the screen is on */
  944. if (axi_rate)
  945. clk_set_rate(axi_clk, sleep_axi_rate);
  946. +#endif
  947. }
  948. +#ifdef CONFIG_HTC_POWER_COLLAPSE_MAGIC
  949. + magic_num = 0xAAAA1111;
  950. + writel(magic_num, HTC_POWER_COLLAPSE_MAGIC_NUM);
  951. +#endif
  952. if (sleep_mode < MSM_PM_SLEEP_MODE_APPS_SLEEP) {
  953. if (msm_pm_debug_mask & MSM_PM_DEBUG_SMSM_STATE)
  954. - smsm_print_sleep_info();
  955. + smsm_print_sleep_info(0);
  956. saved_vector[0] = msm_pm_reset_vector[0];
  957. saved_vector[1] = msm_pm_reset_vector[1];
  958. msm_pm_reset_vector[0] = 0xE51FF004; /* ldr pc, 4 */
  959. @@ -378,10 +414,29 @@ static int msm_sleep(int sleep_mode, uint32_t sleep_delay, int from_idle)
  960. printk(KERN_INFO "msm_sleep(): vector %x %x -> "
  961. "%x %x\n", saved_vector[0], saved_vector[1],
  962. msm_pm_reset_vector[0], msm_pm_reset_vector[1]);
  963. +#ifdef CONFIG_VFP
  964. + if (from_idle)
  965. + vfp_flush_context();
  966. +#endif
  967. +
  968. +#ifdef CONFIG_CACHE_L2X0
  969. + l2x0_suspend();
  970. +#endif
  971. + if (!from_idle) printk(KERN_INFO "[R] suspend end\n");
  972. + /* reset idle sleep mode when suspend. */
  973. + if (!from_idle) msm_pm_idle_sleep_mode = CONFIG_MSM7X00A_IDLE_SLEEP_MODE;
  974. collapsed = msm_pm_collapse();
  975. + if (!from_idle) printk(KERN_INFO "[R] resume start\n");
  976. +#ifdef CONFIG_CACHE_L2X0
  977. + l2x0_resume(collapsed);
  978. +#endif
  979. msm_pm_reset_vector[0] = saved_vector[0];
  980. msm_pm_reset_vector[1] = saved_vector[1];
  981. if (collapsed) {
  982. +#ifdef CONFIG_VFP
  983. + if (from_idle)
  984. + vfp_reinit();
  985. +#endif
  986. cpu_init();
  987. __asm__("cpsie a");
  988. msm_fiq_exit_sleep();
  989. @@ -392,23 +447,33 @@ static int msm_sleep(int sleep_mode, uint32_t sleep_delay, int from_idle)
  990. printk(KERN_INFO "msm_pm_collapse(): returned %d\n",
  991. collapsed);
  992. if (msm_pm_debug_mask & MSM_PM_DEBUG_SMSM_STATE)
  993. - smsm_print_sleep_info();
  994. + smsm_print_sleep_info(0);
  995. } else {
  996. msm_arch_idle();
  997. rv = 0;
  998. }
  999. -
  1000. +#ifdef CONFIG_HTC_POWER_COLLAPSE_MAGIC
  1001. + magic_num = 0xBBBB9999;
  1002. + writel(magic_num, HTC_POWER_COLLAPSE_MAGIC_NUM);
  1003. +#endif
  1004. if (sleep_mode <= MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT) {
  1005. if (msm_pm_debug_mask & MSM_PM_DEBUG_CLOCK)
  1006. printk(KERN_INFO "msm_sleep(): exit power collapse %ld"
  1007. "\n", pm_saved_acpu_clk_rate);
  1008. +#if defined(CONFIG_ARCH_QSD8X50)
  1009. if (acpuclk_set_rate(pm_saved_acpu_clk_rate, 1) < 0)
  1010. +#else
  1011. + if (acpuclk_set_rate(pm_saved_acpu_clk_rate,
  1012. + from_idle ? SETRATE_PC_IDLE : SETRATE_PC) < 0)
  1013. +#endif
  1014. printk(KERN_ERR "msm_sleep(): clk_set_rate %ld "
  1015. "failed\n", pm_saved_acpu_clk_rate);
  1016.  
  1017. +#ifdef CONFIG_AXI_SCREEN_POLICY
  1018. /* Restore axi rate if needed */
  1019. if (axi_rate)
  1020. clk_set_rate(axi_clk, axi_rate);
  1021. +#endif
  1022. }
  1023. if (msm_pm_debug_mask & MSM_PM_DEBUG_STATE)
  1024. printk(KERN_INFO "msm_sleep(): exit A11S_CLK_SLEEP_EN %x, "
  1025. @@ -419,8 +484,14 @@ ramp_down_failed:
  1026. msm_irq_exit_sleep1();
  1027. enter_failed:
  1028. if (enter_state) {
  1029. +#if defined (CONFIG_ARCH_MSM7X30)
  1030. + writel(0, A11S_SECOP);
  1031. + writel(0, A11S_PWRDOWN);
  1032. + msm_spm_reinit();
  1033. +#else
  1034. writel(0x00, A11S_CLK_SLEEP_EN);
  1035. writel(0, A11S_PWRDOWN);
  1036. +#endif
  1037. smsm_change_state(PM_SMSM_WRITE_STATE, enter_state, exit_state);
  1038. msm_pm_wait_state(0, exit_wait_clear, exit_wait_any_set, 0);
  1039. if (msm_pm_debug_mask & MSM_PM_DEBUG_STATE)
  1040. @@ -429,7 +500,9 @@ enter_failed:
  1041. "smsm_get_state %x\n", readl(A11S_CLK_SLEEP_EN),
  1042. readl(A11S_PWRDOWN), smsm_get_state(PM_SMSM_READ_STATE));
  1043. if (msm_pm_debug_mask & MSM_PM_DEBUG_SMSM_STATE)
  1044. - smsm_print_sleep_info();
  1045. + smsm_print_sleep_info(0);
  1046. + if (msm_pm_debug_mask & MSM_PM_DEBUG_WAKEUP_REASON && !from_idle)
  1047. + smsm_print_sleep_info(1);
  1048. }
  1049. msm_irq_exit_sleep2();
  1050. if (enter_state) {
  1051. @@ -463,7 +536,6 @@ static int msm_pm_idle_spin(void)
  1052.  
  1053. void arch_idle(void)
  1054. {
  1055. -#if 1
  1056. int ret;
  1057. int64_t sleep_time;
  1058. int low_power = 0;
  1059. @@ -492,6 +564,7 @@ void arch_idle(void)
  1060. sleep_time, allow_sleep);
  1061. if (sleep_time < msm_pm_idle_sleep_min_time || !allow_sleep) {
  1062. unsigned long saved_rate;
  1063. + /* only spin while trying wfi ramp down */
  1064. if (acpuclk_get_wfi_rate() && msm_pm_idle_spin() < 0) {
  1065. #ifdef CONFIG_MSM_IDLE_STATS
  1066. exit_stat = MSM_PM_STAT_IDLE_SPIN;
  1067. @@ -518,13 +591,18 @@ void arch_idle(void)
  1068. if (msm_pm_debug_mask & MSM_PM_DEBUG_CLOCK)
  1069. printk(KERN_DEBUG "msm_sleep: clk swfi -> %ld\n",
  1070. saved_rate);
  1071. - if (acpuclk_set_rate(saved_rate, 1) < 0)
  1072. +#if defined(CONFIG_ARCH_QSD8X50)
  1073. + if (saved_rate && acpuclk_set_rate(saved_rate, 1) < 0)
  1074. +#else
  1075. + if (saved_rate
  1076. + && acpuclk_set_rate(saved_rate, SETRATE_SWFI) < 0)
  1077. +#endif
  1078. printk(KERN_ERR "msm_sleep(): clk_set_rate %ld "
  1079. "failed\n", saved_rate);
  1080. #ifdef CONFIG_MSM_IDLE_STATS
  1081. exit_stat = MSM_PM_STAT_IDLE_WFI;
  1082. #endif
  1083. - } else {
  1084. + } else {
  1085. if (msm_pm_idle_spin() < 0) {
  1086. #ifdef CONFIG_MSM_IDLE_STATS
  1087. exit_stat = MSM_PM_STAT_IDLE_SPIN;
  1088. @@ -552,8 +630,6 @@ abort_idle:
  1089. t2 = ktime_to_ns(ktime_get());
  1090. msm_pm_add_stat(exit_stat, t2 - t1);
  1091. #endif
  1092. -
  1093. -#endif
  1094. }
  1095.  
  1096. static int msm_pm_enter(suspend_state_t state)
  1097. @@ -567,16 +643,44 @@ static struct platform_suspend_ops msm_pm_ops = {
  1098. .valid = suspend_valid_only_mem,
  1099. };
  1100.  
  1101. -#if defined(CONFIG_ARCH_MSM7X00A)
  1102. static uint32_t restart_reason = 0x776655AA;
  1103. -#else
  1104. -static uint32_t restart_reason = 0;
  1105. -#endif
  1106. +
  1107. +static int msm_wakeup_after; /* default, no wakeup by alarm */
  1108. +static int msm_power_wakeup_after(const char *val, struct kernel_param *kp)
  1109. +{
  1110. + int ret;
  1111. + struct uart_port *port;
  1112. + struct msm_port *msm_port;
  1113. +
  1114. + ret = param_set_int(val, kp);
  1115. + printk(KERN_INFO "+msm_power_wakeup_after, ret=%d\r\n", ret);
  1116. +
  1117. + if (!ret) {
  1118. + printk(KERN_INFO "msm_wakeup_after=%d\r\n", msm_wakeup_after);
  1119. + if (msm_wakeup_after < 0)
  1120. + msm_wakeup_after = 0; /* invalid, no wakeup */
  1121. + }
  1122. + printk(KERN_INFO "-msm_power_wakeup_after, msm_wakeup_after=%d\r\n", msm_wakeup_after);
  1123. + return ret;
  1124. +}
  1125. +
  1126. +module_param_call(wakeup_after, msm_power_wakeup_after, param_get_int,
  1127. + &msm_wakeup_after, S_IWUSR | S_IRUGO);
  1128.  
  1129. static void msm_pm_power_off(void)
  1130. {
  1131. -// msm_proc_comm(PCOM_POWER_DOWN, 0, 0);
  1132. - dex_comm(DEX_POWER_DOWN, 0, 0);
  1133. + printk(KERN_INFO "msm_pm_power_off:wakeup after %d\r\n", msm_wakeup_after);
  1134. +
  1135. + if (msm_wakeup_after)
  1136. + msm_proc_comm(PCOM_SET_RTC_ALARM, &msm_wakeup_after, 0);
  1137. +
  1138. + msm_proc_comm(PCOM_POWER_DOWN, 0, 0);
  1139. +
  1140. +#if CONFIG_MSM_RMT_STORAGE_SERVER
  1141. + printk(KERN_INFO "from %s\r\n", __func__);
  1142. + wait_rmt_final_call_back(10);
  1143. + printk(KERN_INFO "back %s\r\n", __func__);
  1144. +#endif
  1145. for (;;) ;
  1146. }
  1147.  
  1148. @@ -609,22 +713,29 @@ static void msm_pm_restart(char str)
  1149. {
  1150. msm_pm_flush_console();
  1151.  
  1152. - /* If there's a hard reset hook and the restart_reason
  1153. - * is the default, prefer that to the (slower) proc_comm
  1154. - * reset command.
  1155. - */
  1156. -#ifdef CONFIG_MSM_AMSS_VERSION_WINCE
  1157. - if (msm_hw_reset_hook)
  1158. - msm_hw_reset_hook();
  1159. + /* always reboot device through proc comm */
  1160. + if (restart_reason == 0x6f656d99)
  1161. + msm_proc_comm(PCOM_RESET_CHIP_IMM, &restart_reason, 0);
  1162. else
  1163. - printk(KERN_ERR "No msm_hw_reset_hook() available! System halted.\n");
  1164. + msm_proc_comm(PCOM_RESET_CHIP, &restart_reason, 0);
  1165. +
  1166. +#if CONFIG_MSM_RMT_STORAGE_SERVER
  1167. + printk(KERN_INFO "from %s\r\n", __func__);
  1168. + wait_rmt_final_call_back(10);
  1169. + printk(KERN_INFO "back %s\r\n", __func__);
  1170. + /* wait 2 seconds to let radio reset device after the final EFS sync*/
  1171. + mdelay(2000);
  1172. #else
  1173. - if ((restart_reason == 0x776655AA) && msm_hw_reset_hook) {
  1174. + /* In case Radio is dead, reset device after notify Radio 5 seconds */
  1175. + mdelay(5000);
  1176. +#endif
  1177. +
  1178. + /* hard reboot if possible */
  1179. + if (msm_hw_reset_hook) {
  1180. + printk(KERN_INFO "%s : Do HW_RESET by APP not by RADIO\r\n", __func__);
  1181. msm_hw_reset_hook();
  1182. - } else {
  1183. - msm_proc_comm(PCOM_RESET_CHIP, &restart_reason, 0);
  1184. }
  1185. -#endif
  1186. +
  1187. for (;;) ;
  1188. }
  1189.  
  1190. @@ -723,16 +834,18 @@ void msm_pm_set_max_sleep_time(int64_t max_sleep_time_ns)
  1191. }
  1192. EXPORT_SYMBOL(msm_pm_set_max_sleep_time);
  1193.  
  1194. -#if defined(CONFIG_EARLYSUSPEND) && defined(CONFIG_ARCH_MSM_SCORPION)
  1195. +#ifdef CONFIG_EARLYSUSPEND
  1196. /* axi 128 screen on, 61mhz screen off */
  1197. -static void axi_early_suspend(struct early_suspend *handler) {
  1198. +static void axi_early_suspend(struct early_suspend *handler)
  1199. +{
  1200. axi_rate = 0;
  1201. clk_set_rate(axi_clk, axi_rate);
  1202. }
  1203.  
  1204. -static void axi_late_resume(struct early_suspend *handler) {
  1205. +static void axi_late_resume(struct early_suspend *handler)
  1206. +{
  1207. axi_rate = 128000000;
  1208. - sleep_axi_rate = 120000000;
  1209. + sleep_axi_rate = 117000000;
  1210. clk_set_rate(axi_clk, axi_rate);
  1211. }
  1212.  
  1213. @@ -744,7 +857,7 @@ static struct early_suspend axi_screen_suspend = {
  1214.  
  1215. static void __init msm_pm_axi_init(void)
  1216. {
  1217. -#if defined(CONFIG_EARLYSUSPEND) && defined(CONFIG_ARCH_MSM_SCORPION)
  1218. +#ifdef CONFIG_EARLYSUSPEND
  1219. axi_clk = clk_get(NULL, "ebi1_clk");
  1220. if (IS_ERR(axi_clk)) {
  1221. int result = PTR_ERR(axi_clk);
  1222. @@ -752,7 +865,7 @@ static void __init msm_pm_axi_init(void)
  1223. return;
  1224. }
  1225. axi_rate = 128000000;
  1226. - sleep_axi_rate = 120000000;
  1227. + sleep_axi_rate = 117000000;
  1228. clk_set_rate(axi_clk, axi_rate);
  1229. register_early_suspend(&axi_screen_suspend);
  1230. #else
  1231. @@ -765,11 +878,15 @@ static int __init msm_pm_init(void)
  1232. pm_power_off = msm_pm_power_off;
  1233. arm_pm_restart = msm_pm_restart;
  1234. msm_pm_max_sleep_time = 0;
  1235. +#if defined(CONFIG_ARCH_MSM_SCORPION)
  1236. +#ifdef CONFIG_AXI_SCREEN_POLICY
  1237. msm_pm_axi_init();
  1238. +#endif
  1239. +#endif
  1240.  
  1241. register_reboot_notifier(&msm_reboot_notifier);
  1242. + msm_pm_reset_vector = ioremap(0x0, PAGE_SIZE);
  1243.  
  1244. - msm_pm_reset_vector = ioremap(0, PAGE_SIZE);
  1245. if (msm_pm_reset_vector == NULL) {
  1246. printk(KERN_ERR "msm_pm_init: failed to map reset vector\n");
  1247. return -ENODEV;
  1248. @@ -781,6 +898,12 @@ static int __init msm_pm_init(void)
  1249. create_proc_read_entry("msm_pm_stats", S_IRUGO,
  1250. NULL, msm_pm_read_proc, NULL);
  1251. #endif
  1252. +
  1253. + if ((board_mfg_mode() == 0) || (board_mfg_mode() == 1)) {
  1254. + disable_hlt();
  1255. + schedule_delayed_work(&work_expire_boot_lock, BOOT_LOCK_TIMEOUT);
  1256. + pr_info("Acquire 'boot-time' halt_lock\n");
  1257. + }
  1258. return 0;
  1259. }
  1260.  
  1261. diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
  1262. index 861b7b9..4df7c09 100644
  1263. --- a/arch/arm/mach-msm/smd.c
  1264. +++ b/arch/arm/mach-msm/smd.c
  1265. @@ -61,6 +61,11 @@ static struct shared_info smd_info = {
  1266. .state = (unsigned) &dummy_state,
  1267. };
  1268.  
  1269. +#ifdef CONFIG_BUILD_CIQ
  1270. +static int msm_smd_ciq_info;
  1271. +module_param_named(ciq_info, msm_smd_ciq_info,
  1272. + int, S_IRUGO | S_IWUSR | S_IWGRP);
  1273. +#endif
  1274. module_param_named(debug_mask, msm_smd_debug_mask,
  1275. int, S_IRUGO | S_IWUSR | S_IWGRP);
  1276.  
  1277. @@ -71,9 +76,18 @@ static unsigned last_heap_free = 0xffffffff;
  1278.  
  1279. #define MSM_A2M_INT(n) (MSM_CSR_BASE + 0x400 + (n) * 4)
  1280.  
  1281. +#if defined(CONFIG_ARCH_MSM7X30)
  1282. +#define MSM_TRIG_A2M_INT(n) (writel(1 << n, MSM_GCC_BASE + 0x8))
  1283. +#endif
  1284. +
  1285. static inline void notify_other_smsm(void)
  1286. {
  1287. +#if defined(CONFIG_ARCH_MSM7X30)
  1288. + MSM_TRIG_A2M_INT(5);
  1289. +#else
  1290. writel(1, MSM_A2M_INT(5));
  1291. +#endif
  1292. +
  1293. #ifdef CONFIG_QDSP6
  1294. writel(1, MSM_A2M_INT(8));
  1295. #endif
  1296. @@ -81,12 +95,20 @@ static inline void notify_other_smsm(void)
  1297.  
  1298. static inline void notify_modem_smd(void)
  1299. {
  1300. +#if defined(CONFIG_ARCH_MSM7X30)
  1301. + MSM_TRIG_A2M_INT(0);
  1302. +#else
  1303. writel(1, MSM_A2M_INT(0));
  1304. +#endif
  1305. }
  1306.  
  1307. static inline void notify_dsp_smd(void)
  1308. {
  1309. +#if defined(CONFIG_ARCH_MSM7X30)
  1310. + MSM_TRIG_A2M_INT(8);
  1311. +#else
  1312. writel(1, MSM_A2M_INT(8));
  1313. +#endif
  1314. }
  1315.  
  1316. static void smd_diag(void)
  1317. @@ -100,17 +122,15 @@ static void smd_diag(void)
  1318. }
  1319. }
  1320.  
  1321. -#if defined(CONFIG_PM)
  1322. void msm_pm_flush_console(void);
  1323. -#endif
  1324. +
  1325. /* call when SMSM_RESET flag is set in the A9's smsm_state */
  1326. static void handle_modem_crash(void)
  1327. {
  1328. pr_err("ARM9 has CRASHED\n");
  1329. smd_diag();
  1330. -#if defined(CONFIG_PM)
  1331. msm_pm_flush_console();
  1332. -#endif
  1333. +
  1334. /* hard reboot if possible */
  1335. if (msm_hw_reset_hook)
  1336. msm_hw_reset_hook();
  1337. @@ -151,6 +171,69 @@ static DEFINE_MUTEX(smd_creation_mutex);
  1338.  
  1339. static int smd_initialized;
  1340.  
  1341. +struct smd_alloc_elm {
  1342. + char name[20];
  1343. + uint32_t cid;
  1344. + uint32_t ctype;
  1345. + uint32_t ref_count;
  1346. +};
  1347. +
  1348. +struct smd_half_channel {
  1349. + unsigned state;
  1350. + unsigned char fDSR;
  1351. + unsigned char fCTS;
  1352. + unsigned char fCD;
  1353. + unsigned char fRI;
  1354. + unsigned char fHEAD;
  1355. + unsigned char fTAIL;
  1356. + unsigned char fSTATE;
  1357. + unsigned char fUNUSED;
  1358. + unsigned tail;
  1359. + unsigned head;
  1360. +};
  1361. +
  1362. +struct smd_shared_v1 {
  1363. + struct smd_half_channel ch0;
  1364. + unsigned char data0[SMD_BUF_SIZE];
  1365. + struct smd_half_channel ch1;
  1366. + unsigned char data1[SMD_BUF_SIZE];
  1367. +};
  1368. +
  1369. +struct smd_shared_v2 {
  1370. + struct smd_half_channel ch0;
  1371. + struct smd_half_channel ch1;
  1372. +};
  1373. +
  1374. +struct smd_channel {
  1375. + volatile struct smd_half_channel *send;
  1376. + volatile struct smd_half_channel *recv;
  1377. + unsigned char *send_data;
  1378. + unsigned char *recv_data;
  1379. +
  1380. + unsigned fifo_mask;
  1381. + unsigned fifo_size;
  1382. + unsigned current_packet;
  1383. + unsigned n;
  1384. +
  1385. + struct list_head ch_list;
  1386. +
  1387. + void *priv;
  1388. + void (*notify)(void *priv, unsigned flags);
  1389. +
  1390. + int (*read)(struct smd_channel *ch, void *data, int len);
  1391. + int (*write)(struct smd_channel *ch, const void *data, int len);
  1392. + int (*read_avail)(struct smd_channel *ch);
  1393. + int (*write_avail)(struct smd_channel *ch);
  1394. +
  1395. + void (*update_state)(struct smd_channel *ch);
  1396. + unsigned last_state;
  1397. + void (*notify_other_cpu)(void);
  1398. + unsigned type;
  1399. +
  1400. + char name[32];
  1401. + struct platform_device pdev;
  1402. +};
  1403. +
  1404. LIST_HEAD(smd_ch_closed_list);
  1405. LIST_HEAD(smd_ch_list_modem);
  1406. LIST_HEAD(smd_ch_list_dsp);
  1407. @@ -158,7 +241,7 @@ LIST_HEAD(smd_ch_list_dsp);
  1408. static unsigned char smd_ch_allocated[64];
  1409. static struct work_struct probe_work;
  1410.  
  1411. -static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type);
  1412. +static unsigned smd_alloc_channel(const char *name, uint32_t cid, uint32_t type);
  1413.  
  1414. static void smd_channel_probe_worker(struct work_struct *work)
  1415. {
  1416. @@ -166,6 +249,7 @@ static void smd_channel_probe_worker(struct work_struct *work)
  1417. unsigned ctype;
  1418. unsigned type;
  1419. unsigned n;
  1420. + unsigned ret = -EAGAIN;
  1421.  
  1422. shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
  1423. if (!shared) {
  1424. @@ -191,8 +275,9 @@ static void smd_channel_probe_worker(struct work_struct *work)
  1425. type = shared[n].ctype & SMD_TYPE_MASK;
  1426. if ((type == SMD_TYPE_APPS_MODEM) ||
  1427. (type == SMD_TYPE_APPS_DSP))
  1428. - if (!smd_alloc_channel(shared[n].name, shared[n].cid, ctype))
  1429. - smd_ch_allocated[n] = 1;
  1430. + ret = smd_alloc_channel(shared[n].name, shared[n].cid, ctype);
  1431. + if (!ret)
  1432. + smd_ch_allocated[n] = 1;
  1433. }
  1434. }
  1435.  
  1436. @@ -229,8 +314,9 @@ static int smd_packet_write_avail(struct smd_channel *ch)
  1437.  
  1438. static int ch_is_open(struct smd_channel *ch)
  1439. {
  1440. - return (ch->recv->state == SMD_SS_OPENED) &&
  1441. - (ch->send->state == SMD_SS_OPENED);
  1442. + return (ch->recv->state == SMD_SS_OPENED ||
  1443. + ch->recv->state == SMD_SS_FLUSHING)
  1444. + && (ch->send->state == SMD_SS_OPENED);
  1445. }
  1446.  
  1447. /* provide a pointer and length to readable data in the fifo */
  1448. @@ -272,6 +358,7 @@ static int ch_read(struct smd_channel *ch, void *_data, int len)
  1449.  
  1450. if (n > len)
  1451. n = len;
  1452. +
  1453. if (_data)
  1454. memcpy(data, ptr, n);
  1455.  
  1456. @@ -368,20 +455,31 @@ static void smd_state_change(struct smd_channel *ch,
  1457.  
  1458. switch (next) {
  1459. case SMD_SS_OPENING:
  1460. - ch->recv->tail = 0;
  1461. + if (ch->send->state == SMD_SS_CLOSING ||
  1462. + ch->send->state == SMD_SS_CLOSED) {
  1463. + ch->recv->tail = 0;
  1464. + ch->send->head = 0;
  1465. + ch_set_state(ch, SMD_SS_OPENING);
  1466. + }
  1467. + break;
  1468. case SMD_SS_OPENED:
  1469. - if (ch->send->state != SMD_SS_OPENED)
  1470. + if (ch->send->state == SMD_SS_OPENING) {
  1471. ch_set_state(ch, SMD_SS_OPENED);
  1472. - ch->notify(ch->priv, SMD_EVENT_OPEN);
  1473. + ch->notify(ch->priv, SMD_EVENT_OPEN);
  1474. + }
  1475. break;
  1476. case SMD_SS_FLUSHING:
  1477. case SMD_SS_RESET:
  1478. /* we should force them to close? */
  1479. - default:
  1480. - ch->notify(ch->priv, SMD_EVENT_CLOSE);
  1481. + break;
  1482. + case SMD_SS_CLOSED:
  1483. + if (ch->send->state == SMD_SS_OPENED) {
  1484. + ch_set_state(ch, SMD_SS_CLOSING);
  1485. + ch->notify(ch->priv, SMD_EVENT_CLOSE);
  1486. + }
  1487. + break;
  1488. }
  1489. }
  1490. -
  1491. static void handle_smd_irq(struct list_head *list, void (*notify)(void))
  1492. {
  1493. unsigned long flags;
  1494. @@ -389,7 +487,11 @@ static void handle_smd_irq(struct list_head *list, void (*notify)(void))
  1495. int do_notify = 0;
  1496. unsigned ch_flags;
  1497. unsigned tmp;
  1498. -
  1499. +#ifdef CONFIG_BUILD_CIQ
  1500. + /* put here to make sure we got the disable/enable index */
  1501. + if (!msm_smd_ciq_info)
  1502. + msm_smd_ciq_info = (*(volatile uint32_t *)(MSM_SHARED_RAM_BASE + 0xFC11C));
  1503. +#endif
  1504. spin_lock_irqsave(&smd_lock, flags);
  1505. list_for_each_entry(ch, list, ch_list) {
  1506. ch_flags = 0;
  1507. @@ -430,11 +532,13 @@ static irqreturn_t smd_modem_irq_handler(int irq, void *data)
  1508. return IRQ_HANDLED;
  1509. }
  1510.  
  1511. +#if defined(CONFIG_QDSP6)
  1512. static irqreturn_t smd_dsp_irq_handler(int irq, void *data)
  1513. {
  1514. handle_smd_irq(&smd_ch_list_dsp, notify_dsp_smd);
  1515. return IRQ_HANDLED;
  1516. }
  1517. +#endif
  1518.  
  1519. static void smd_fake_irq_handler(unsigned long arg)
  1520. {
  1521. @@ -514,6 +618,14 @@ static int smd_is_packet(int chn, unsigned type)
  1522. return 0;
  1523.  
  1524. /* older AMSS reports SMD_KIND_UNKNOWN always */
  1525. +#if defined(CONFIG_ARCH_MSM7225)
  1526. + if (chn == 1)
  1527. + return 0;
  1528. +#endif
  1529. +#ifdef CONFIG_BUILD_CIQ
  1530. + if (chn == 26)
  1531. + return 0;
  1532. +#endif
  1533. if ((chn > 4) || (chn == 1))
  1534. return 1;
  1535. else
  1536. @@ -552,7 +664,7 @@ static int smd_packet_write(smd_channel_t *ch, const void *_data, int len)
  1537. {
  1538. unsigned hdr[5];
  1539.  
  1540. - if (len < 0)
  1541. + if (len <= 0)
  1542. return -EINVAL;
  1543.  
  1544. if (smd_stream_write_avail(ch) < (len + SMD_HEADER_SIZE))
  1545. @@ -611,10 +723,16 @@ static int smd_alloc_v2(struct smd_channel *ch)
  1546. unsigned buffer_sz;
  1547.  
  1548. shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n, sizeof(*shared2));
  1549. + if (!shared2) {
  1550. + pr_err("smd_alloc_v2: cid %d does not exist\n", ch->n);
  1551. + return -1;
  1552. + }
  1553. buffer = smem_item(SMEM_SMD_FIFO_BASE_ID + ch->n, &buffer_sz);
  1554.  
  1555. - if (!buffer)
  1556. + if (!buffer) {
  1557. + pr_err("smd_alloc_v2: ch%d buffer allocate fail\n", ch->n);
  1558. return -1;
  1559. + }
  1560.  
  1561. /* buffer must be a power-of-two size */
  1562. if (buffer_sz & (buffer_sz - 1))
  1563. @@ -634,7 +752,7 @@ static int smd_alloc_v1(struct smd_channel *ch)
  1564. struct smd_shared_v1 *shared1;
  1565. shared1 = smem_alloc(ID_SMD_CHANNELS + ch->n, sizeof(*shared1));
  1566. if (!shared1) {
  1567. - pr_err("smd_alloc_channel() cid %d does not exist\n", ch->n);
  1568. + pr_err("smd_alloc_v1: cid %d does not exist\n", ch->n);
  1569. return -1;
  1570. }
  1571. ch->send = &shared1->ch0;
  1572. @@ -646,26 +764,26 @@ static int smd_alloc_v1(struct smd_channel *ch)
  1573. }
  1574.  
  1575.  
  1576. -static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type)
  1577. +static unsigned smd_alloc_channel(const char *name, uint32_t cid, uint32_t type)
  1578. {
  1579. struct smd_channel *ch;
  1580.  
  1581. ch = kzalloc(sizeof(struct smd_channel), GFP_KERNEL);
  1582. if (ch == 0) {
  1583. pr_err("smd_alloc_channel() out of memory\n");
  1584. - return -1;
  1585. + return -EAGAIN;
  1586. }
  1587. ch->n = cid;
  1588.  
  1589. if (smd_alloc_v2(ch) && smd_alloc_v1(ch)) {
  1590. kfree(ch);
  1591. - return -1;
  1592. + return -EAGAIN;
  1593. }
  1594.  
  1595. ch->fifo_mask = ch->fifo_size - 1;
  1596. - ch->type = type;
  1597. + ch->type = type & SMD_TYPE_MASK;
  1598.  
  1599. - if ((type & SMD_TYPE_MASK) == SMD_TYPE_APPS_MODEM)
  1600. + if (ch->type == SMD_TYPE_APPS_MODEM)
  1601. ch->notify_other_cpu = notify_modem_smd;
  1602. else
  1603. ch->notify_other_cpu = notify_dsp_smd;
  1604. @@ -684,14 +802,16 @@ static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type)
  1605. ch->update_state = update_stream_state;
  1606. }
  1607.  
  1608. - if ((type & 0xff) == 0)
  1609. + if (ch->type == SMD_TYPE_APPS_MODEM)
  1610. memcpy(ch->name, "SMD_", 4);
  1611. else
  1612. memcpy(ch->name, "DSP_", 4);
  1613. +
  1614. memcpy(ch->name + 4, name, 20);
  1615. ch->name[23] = 0;
  1616. +
  1617. ch->pdev.name = ch->name;
  1618. - ch->pdev.id = -1;
  1619. + ch->pdev.id = ch->type;
  1620.  
  1621. pr_info("smd_alloc_channel() cid=%02d size=%05d '%s'\n",
  1622. ch->n, ch->fifo_size, ch->name);
  1623. @@ -737,8 +857,10 @@ int smd_open(const char *name, smd_channel_t **_ch,
  1624. }
  1625.  
  1626. ch = smd_get_channel(name);
  1627. - if (!ch)
  1628. + if (!ch){
  1629. + pr_info("smd_open() fail, because radio no open %s smd chnnel\n",name);
  1630. return -ENODEV;
  1631. + }
  1632.  
  1633. if (notify == 0)
  1634. notify = do_nothing_notify;
  1635. @@ -752,27 +874,14 @@ int smd_open(const char *name, smd_channel_t **_ch,
  1636.  
  1637. spin_lock_irqsave(&smd_lock, flags);
  1638.  
  1639. - if ((ch->type & SMD_TYPE_MASK) == SMD_TYPE_APPS_MODEM)
  1640. + if (ch->type == SMD_APPS_MODEM)
  1641. list_add(&ch->ch_list, &smd_ch_list_modem);
  1642. else
  1643. list_add(&ch->ch_list, &smd_ch_list_dsp);
  1644.  
  1645. - /* If the remote side is CLOSING, we need to get it to
  1646. - * move to OPENING (which we'll do by moving from CLOSED to
  1647. - * OPENING) and then get it to move from OPENING to
  1648. - * OPENED (by doing the same state change ourselves).
  1649. - *
  1650. - * Otherwise, it should be OPENING and we can move directly
  1651. - * to OPENED so that it will follow.
  1652. - */
  1653. - if (ch->recv->state == SMD_SS_CLOSING) {
  1654. - ch->send->head = 0;
  1655. - ch_set_state(ch, SMD_SS_OPENING);
  1656. - } else {
  1657. - ch_set_state(ch, SMD_SS_OPENED);
  1658. - }
  1659. + smd_state_change(ch, ch->last_state, SMD_SS_OPENING);
  1660. +
  1661. spin_unlock_irqrestore(&smd_lock, flags);
  1662. - smd_kick(ch);
  1663.  
  1664. return 0;
  1665. }
  1666. @@ -786,6 +895,9 @@ int smd_close(smd_channel_t *ch)
  1667. if (ch == 0)
  1668. return -1;
  1669.  
  1670. + ch->recv->head = 0;
  1671. + ch->recv->tail = 0;
  1672. +
  1673. spin_lock_irqsave(&smd_lock, flags);
  1674. ch->notify = do_nothing_notify;
  1675. list_del(&ch->ch_list);
  1676. @@ -839,6 +951,26 @@ int smd_wait_until_writable(smd_channel_t *ch, int bytes)
  1677. return -1;
  1678. }
  1679.  
  1680. +int smd_wait_until_opened(smd_channel_t *ch, int timeout_us)
  1681. +{
  1682. +#define POLL_INTERVAL_USEC 200
  1683. + int count = 0;
  1684. +
  1685. + if (timeout_us)
  1686. + count = timeout_us / (POLL_INTERVAL_USEC + 1) + 1;
  1687. +
  1688. + do {
  1689. + if (ch_is_open(ch))
  1690. + return 0;
  1691. + if (count--)
  1692. + udelay(POLL_INTERVAL_USEC);
  1693. + else
  1694. + break;
  1695. + } while (1);
  1696. +
  1697. + return -1;
  1698. +}
  1699. +
  1700. int smd_cur_packet_size(smd_channel_t *ch)
  1701. {
  1702. return ch->current_packet;
  1703. @@ -954,8 +1086,7 @@ uint32_t smsm_get_state(enum smsm_state_item item)
  1704. return rv;
  1705. }
  1706.  
  1707. -#ifdef CONFIG_ARCH_MSM_SCORPION
  1708. -
  1709. +#if defined(CONFIG_MSM_N_WAY_SMD)
  1710. int smsm_set_sleep_duration(uint32_t delay)
  1711. {
  1712. struct msm_dem_slave_data *ptr;
  1713. @@ -972,8 +1103,23 @@ int smsm_set_sleep_duration(uint32_t delay)
  1714. return 0;
  1715. }
  1716.  
  1717. -#else
  1718. +int smsm_set_sleep_limit(uint32_t sleep_limit)
  1719. +{
  1720. + struct msm_dem_slave_data *ptr;
  1721. +
  1722. + ptr = smem_find(SMEM_APPS_DEM_SLAVE_DATA, sizeof(*ptr));
  1723. + if (ptr == NULL) {
  1724. + pr_err("smsm_set_sleep_limit <SM NO APPS_DEM_SLAVE_DATA>\n");
  1725. + return -EIO;
  1726. + }
  1727. + if (msm_smd_debug_mask & MSM_SMSM_DEBUG)
  1728. + pr_info("smsm_set_sleep_limit %d -> %d\n",
  1729. + ptr->resources_used, sleep_limit);
  1730. + ptr->resources_used = sleep_limit;
  1731. + return 0;
  1732. +}
  1733.  
  1734. +#else
  1735. int smsm_set_sleep_duration(uint32_t delay)
  1736. {
  1737. uint32_t *ptr;
  1738. @@ -990,6 +1136,10 @@ int smsm_set_sleep_duration(uint32_t delay)
  1739. return 0;
  1740. }
  1741.  
  1742. +inline int smsm_set_sleep_limit(uint32_t sleep_limit)
  1743. +{
  1744. + return 0;
  1745. +}
  1746. #endif
  1747.  
  1748. int smd_core_init(void)
  1749. @@ -1030,12 +1180,16 @@ int smd_core_init(void)
  1750.  
  1751. #if defined(CONFIG_QDSP6)
  1752. r = request_irq(INT_ADSP_A11, smd_dsp_irq_handler,
  1753. - IRQF_TRIGGER_RISING, "smd_dsp", 0);
  1754. + IRQF_TRIGGER_RISING | IRQF_SHARED, "smd_dev", smd_dsp_irq_handler);
  1755. if (r < 0) {
  1756. free_irq(INT_A9_M2A_0, 0);
  1757. free_irq(INT_A9_M2A_5, 0);
  1758. return r;
  1759. }
  1760. + r = enable_irq_wake(INT_ADSP_A11);
  1761. + if (r < 0)
  1762. + printk(KERN_ERR "smd_core_init: "
  1763. + "enable_irq_wake failed for INT_ADSP_A11\n");
  1764. #endif
  1765.  
  1766. /* check for any SMD channels that may already exist */
  1767. @@ -1044,7 +1198,7 @@ int smd_core_init(void)
  1768. /* indicate that we're up and running */
  1769. smsm_change_state(SMSM_STATE_APPS,
  1770. ~0, SMSM_INIT | SMSM_SMDINIT | SMSM_RPCINIT | SMSM_RUN);
  1771. -#ifdef CONFIG_ARCH_MSM_SCORPION
  1772. +#if defined(CONFIG_MSM_N_WAY_SMD)
  1773. smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0);
  1774. #endif
  1775.  
  1776. diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c
  1777. index e2bfa7e..9246a45 100644
  1778. --- a/arch/arm/mach-msm/smd_debug.c
  1779. +++ b/arch/arm/mach-msm/smd_debug.c
  1780. @@ -16,10 +16,105 @@
  1781.  
  1782. #include <linux/debugfs.h>
  1783. #include <linux/list.h>
  1784. +#include <linux/io.h>
  1785. +#include <linux/earlysuspend.h>
  1786. +#include <linux/rtc.h>
  1787. +#include <linux/suspend.h>
  1788.  
  1789. #include <mach/msm_iomap.h>
  1790.  
  1791. #include "smd_private.h"
  1792. +#include "smd_debug.h"
  1793. +
  1794. +
  1795. +#if CONFIG_SMD_OFFSET_TCXO_STAT
  1796. +enum {
  1797. + F_SCREEN_OFF = 0,
  1798. + F_SUSPEND,
  1799. + F_RESUME,
  1800. + F_SCREEN_ON,
  1801. +};
  1802. +
  1803. +struct smem_sleep_stat {
  1804. + uint32_t tcxo_time;
  1805. + uint32_t tcxo_cnt;
  1806. + uint32_t suspend_tcxo_time;
  1807. + uint32_t suspend_tcxo_cnt;
  1808. + uint32_t garbage_pkt_cnt;
  1809. + uint32_t zone_based_reg_cnt;
  1810. + uint32_t idle_hand_off_cnt;
  1811. + uint32_t mo_2g_probe_cnt;
  1812. + uint32_t mo_3g_probe_cnt;
  1813. + uint32_t reserved[5];
  1814. +};
  1815. +static struct smem_sleep_stat *sleep_stat;
  1816. +static struct smem_sleep_stat *get_smem_sleep_stat(void)
  1817. +{
  1818. + return (struct smem_sleep_stat *)
  1819. + (MSM_SHARED_RAM_BASE + CONFIG_SMD_OFFSET_TCXO_STAT);
  1820. +}
  1821. +
  1822. +static void print_sleep_stat(int flag)
  1823. +{
  1824. + struct timespec ts;
  1825. + struct rtc_time tm;
  1826. + getnstimeofday(&ts);
  1827. + rtc_time_to_tm(ts.tv_sec, &tm);
  1828. +
  1829. + if (!sleep_stat)
  1830. + return;
  1831. +
  1832. + pr_info("sleep_stat.%d: %ds %d %ds %d - "
  1833. + "%d %d %d - %d %d - %d %d %d %d %d"
  1834. + "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n",
  1835. + flag, sleep_stat->tcxo_time, sleep_stat->tcxo_cnt,
  1836. + sleep_stat->suspend_tcxo_time, sleep_stat->suspend_tcxo_cnt,
  1837. + sleep_stat->garbage_pkt_cnt, sleep_stat->zone_based_reg_cnt,
  1838. + sleep_stat->idle_hand_off_cnt, sleep_stat->mo_2g_probe_cnt,
  1839. + sleep_stat->mo_3g_probe_cnt, sleep_stat->reserved[0],
  1840. + sleep_stat->reserved[1], sleep_stat->reserved[2],
  1841. + sleep_stat->reserved[3], sleep_stat->reserved[4],
  1842. + tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
  1843. + tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
  1844. +
  1845. +}
  1846. +
  1847. +static int sleep_stat_suspend_notifier(struct notifier_block *nb,
  1848. + unsigned long event, void *dummy)
  1849. +{
  1850. + switch (event) {
  1851. + /* enter suspend */
  1852. + case PM_SUSPEND_PREPARE:
  1853. + print_sleep_stat(F_SUSPEND);
  1854. + return NOTIFY_OK;
  1855. + /* exit suspend */
  1856. + case PM_POST_SUSPEND:
  1857. + print_sleep_stat(F_RESUME);
  1858. + return NOTIFY_OK;
  1859. + default:
  1860. + return NOTIFY_DONE;
  1861. + }
  1862. +}
  1863. +
  1864. +static struct notifier_block sleep_stat_notif_block = {
  1865. + .notifier_call = sleep_stat_suspend_notifier,
  1866. +};
  1867. +
  1868. +static void sleep_stat_early_suspend(struct early_suspend *handler)
  1869. +{
  1870. + print_sleep_stat(F_SCREEN_OFF);
  1871. +}
  1872. +
  1873. +static void sleep_stat_late_resume(struct early_suspend *handler)
  1874. +{
  1875. + print_sleep_stat(F_SCREEN_ON);
  1876. +}
  1877. +
  1878. +static struct early_suspend sleep_stat_screen_hdl = {
  1879. + .suspend = sleep_stat_early_suspend,
  1880. + .resume = sleep_stat_late_resume,
  1881. +};
  1882. +#endif
  1883.  
  1884. #if defined(CONFIG_DEBUG_FS)
  1885.  
  1886. @@ -103,6 +198,29 @@ static int debug_read_stat(char *buf, int max)
  1887. msg[SZ_DIAG_ERR_MSG - 1] = 0;
  1888. i += scnprintf(buf + i, max - i, "diag: '%s'\n", msg);
  1889. }
  1890. +
  1891. +#if CONFIG_SMD_OFFSET_TCXO_STAT
  1892. + if (sleep_stat) {
  1893. + i += scnprintf(buf + i, max - i,
  1894. + "tcxo_time: 0x%x (%ds) tcxo_cnt: %d\n"
  1895. + "suspend_tcxo_time: 0x%x (%ds) suspend_tcxo_cnt: %d\n"
  1896. + "garbage_pkt_cnt: %d "
  1897. + "zone_based_reg_cnt: %d "
  1898. + "idle_hand_off_cnt: %d "
  1899. + "mo_2g_probe_cnt: %d "
  1900. + "mo_3g_probe_cnt: %d\n",
  1901. + sleep_stat->tcxo_time, sleep_stat->tcxo_time >> 15,
  1902. + sleep_stat->tcxo_cnt, sleep_stat->suspend_tcxo_time,
  1903. + sleep_stat->suspend_tcxo_time >> 15,
  1904. + sleep_stat->suspend_tcxo_cnt,
  1905. + sleep_stat->garbage_pkt_cnt,
  1906. + sleep_stat->zone_based_reg_cnt,
  1907. + sleep_stat->idle_hand_off_cnt,
  1908. + sleep_stat->mo_2g_probe_cnt,
  1909. + sleep_stat->mo_3g_probe_cnt);
  1910. + }
  1911. +#endif
  1912. +
  1913. return i;
  1914. }
  1915.  
  1916. @@ -176,6 +294,10 @@ static int debug_read_alloc_tbl(char *buf, int max)
  1917. int n, i = 0;
  1918.  
  1919. shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
  1920. + if (!shared) {
  1921. + pr_err("smd: cannot find allocation table\n");
  1922. + return 0;
  1923. + }
  1924.  
  1925. for (n = 0; n < 64; n++) {
  1926. if (shared[n].ref_count == 0)
  1927. @@ -221,13 +343,13 @@ static void debug_create(const char *name, mode_t mode,
  1928. debugfs_create_file(name, mode, dent, fill, &debug_ops);
  1929. }
  1930.  
  1931. -static int smd_debugfs_init(void)
  1932. +static int __init smd_debugfs_init(void)
  1933. {
  1934. struct dentry *dent;
  1935.  
  1936. dent = debugfs_create_dir("smd", 0);
  1937. if (IS_ERR(dent))
  1938. - return PTR_ERR(dent);
  1939. + return -1;
  1940.  
  1941. debug_create("ch", 0444, dent, debug_read_ch);
  1942. debug_create("stat", 0444, dent, debug_read_stat);
  1943. @@ -235,7 +357,13 @@ static int smd_debugfs_init(void)
  1944. debug_create("version", 0444, dent, debug_read_version);
  1945. debug_create("tbl", 0444, dent, debug_read_alloc_tbl);
  1946. debug_create("build", 0444, dent, debug_read_build_id);
  1947. -
  1948. +#if CONFIG_SMD_OFFSET_TCXO_STAT
  1949. + sleep_stat = get_smem_sleep_stat();
  1950. + register_early_suspend(&sleep_stat_screen_hdl);
  1951. + register_pm_notifier(&sleep_stat_notif_block);
  1952. +#else
  1953. + pr_info("No sleep statistics\n");
  1954. +#endif
  1955. return 0;
  1956. }
  1957.  
  1958. @@ -265,30 +393,33 @@ struct tramp_gpio_smem {
  1959. };
  1960.  
  1961.  
  1962. -void smsm_print_sleep_info(void)
  1963. +void smsm_print_sleep_info(unsigned wakeup_reason_only)
  1964. {
  1965. unsigned long flags;
  1966. uint32_t *ptr;
  1967. -#ifndef CONFIG_ARCH_MSM_SCORPION
  1968. +#if defined(CONFIG_MSM_N_WAY_SMD)
  1969. + struct msm_dem_slave_data *smd_int_info;
  1970. +#else
  1971. struct tramp_gpio_smem *gpio;
  1972. struct smsm_interrupt_info *int_info;
  1973. #endif
  1974.  
  1975. spin_lock_irqsave(&smem_lock, flags);
  1976.  
  1977. - ptr = smem_alloc(SMEM_SMSM_SLEEP_DELAY, sizeof(*ptr));
  1978. - if (ptr)
  1979. - pr_info("SMEM_SMSM_SLEEP_DELAY: %x\n", *ptr);
  1980. -
  1981. - ptr = smem_alloc(SMEM_SMSM_LIMIT_SLEEP, sizeof(*ptr));
  1982. - if (ptr)
  1983. - pr_info("SMEM_SMSM_LIMIT_SLEEP: %x\n", *ptr);
  1984. + if (!wakeup_reason_only) {
  1985. + ptr = smem_alloc(SMEM_SMSM_SLEEP_DELAY, sizeof(*ptr));
  1986. + if (ptr)
  1987. + pr_info("SMEM_SMSM_SLEEP_DELAY: %x\n", *ptr);
  1988.  
  1989. - ptr = smem_alloc(SMEM_SLEEP_POWER_COLLAPSE_DISABLED, sizeof(*ptr));
  1990. - if (ptr)
  1991. - pr_info("SMEM_SLEEP_POWER_COLLAPSE_DISABLED: %x\n", *ptr);
  1992. + ptr = smem_alloc(SMEM_SMSM_LIMIT_SLEEP, sizeof(*ptr));
  1993. + if (ptr)
  1994. + pr_info("SMEM_SMSM_LIMIT_SLEEP: %x\n", *ptr);
  1995.  
  1996. -#ifndef CONFIG_ARCH_MSM_SCORPION
  1997. + ptr = smem_alloc(SMEM_SLEEP_POWER_COLLAPSE_DISABLED, sizeof(*ptr));
  1998. + if (ptr)
  1999. + pr_info("SMEM_SLEEP_POWER_COLLAPSE_DISABLED: %x\n", *ptr);
  2000. + }
  2001. +#if !defined(CONFIG_MSM_N_WAY_SMD)
  2002. int_info = smem_alloc(SMEM_SMSM_INT_INFO, sizeof(*int_info));
  2003. if (int_info)
  2004. pr_info("SMEM_SMSM_INT_INFO %x %x %x\n",
  2005. @@ -299,17 +430,32 @@ void smsm_print_sleep_info(void)
  2006. gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*gpio));
  2007. if (gpio) {
  2008. int i;
  2009. - for (i = 0; i < NUM_GPIO_INT_REGISTERS; i++)
  2010. - pr_info("SMEM_GPIO_INT: %d: e %x d %x p %x\n",
  2011. - i, gpio->enabled[i], gpio->detection[i],
  2012. - gpio->polarity[i]);
  2013. -
  2014. + if (!wakeup_reason_only) {
  2015. + for (i = 0; i < NUM_GPIO_INT_REGISTERS; i++)
  2016. + pr_info("SMEM_GPIO_INT: %d: e %x d %x p %x\n",
  2017. + i, gpio->enabled[i], gpio->detection[i],
  2018. + gpio->polarity[i]);
  2019. + }
  2020. for (i = 0; i < GPIO_SMEM_NUM_GROUPS; i++)
  2021. pr_info("SMEM_GPIO_INT: %d: f %d: %d %d...\n",
  2022. i, gpio->num_fired[i], gpio->fired[i][0],
  2023. gpio->fired[i][1]);
  2024. }
  2025. #else
  2026. + smd_int_info = smem_find(SMEM_APPS_DEM_SLAVE_DATA, sizeof(*smd_int_info));
  2027. + if (smd_int_info) {
  2028. + pr_info("SMEM_APPS_DEM_SLAVE_DATA: %ds %x %x %x %x %x %x %x %s %x\n",
  2029. + smd_int_info->sleep_time / 32768,
  2030. + smd_int_info->interrupt_mask,
  2031. + smd_int_info->resources_used,
  2032. + smd_int_info->reserved1,
  2033. + smd_int_info->wakeup_reason,
  2034. + smd_int_info->pending_interrupts,
  2035. + smd_int_info->rpc_prog,
  2036. + smd_int_info->rpc_proc,
  2037. + smd_int_info->smd_port_name,
  2038. + smd_int_info->reserved2);
  2039. + }
  2040. #endif
  2041. spin_unlock_irqrestore(&smem_lock, flags);
  2042. }
  2043. diff --git a/arch/arm/mach-msm/smd_private.h b/arch/arm/mach-msm/smd_private.h
  2044. index 2da758e..7094783 100644
  2045. --- a/arch/arm/mach-msm/smd_private.h
  2046. +++ b/arch/arm/mach-msm/smd_private.h
  2047. @@ -16,28 +16,21 @@
  2048. #ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
  2049. #define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
  2050.  
  2051. -#include <linux/platform_device.h>
  2052. -#include <linux/spinlock.h>
  2053. -#include <linux/list.h>
  2054. -
  2055. -struct smem_heap_info
  2056. -{
  2057. +struct smem_heap_info {
  2058. unsigned initialized;
  2059. unsigned free_offset;
  2060. unsigned heap_remaining;
  2061. unsigned reserved;
  2062. };
  2063.  
  2064. -struct smem_heap_entry
  2065. -{
  2066. +struct smem_heap_entry {
  2067. unsigned allocated;
  2068. unsigned offset;
  2069. unsigned size;
  2070. unsigned reserved;
  2071. };
  2072.  
  2073. -struct smem_proc_comm
  2074. -{
  2075. +struct smem_proc_comm {
  2076. unsigned command;
  2077. unsigned status;
  2078. unsigned data1;
  2079. @@ -54,8 +47,7 @@ struct smem_proc_comm
  2080. #define VERSION_APPS 8
  2081. #define VERSION_MODEM 9
  2082.  
  2083. -struct smem_shared
  2084. -{
  2085. +struct smem_shared {
  2086. struct smem_proc_comm proc_comm[4];
  2087. unsigned version[32];
  2088. struct smem_heap_info heap_info;
  2089. @@ -65,14 +57,7 @@ struct smem_shared
  2090. #define SMSM_V1_SIZE (sizeof(unsigned) * 8)
  2091. #define SMSM_V2_SIZE (sizeof(unsigned) * 4)
  2092.  
  2093. -#ifndef CONFIG_ARCH_MSM_SCORPION
  2094. -struct smsm_interrupt_info
  2095. -{
  2096. - uint32_t interrupt_mask;
  2097. - uint32_t pending_interrupts;
  2098. - uint32_t wakeup_reason;
  2099. -};
  2100. -#else
  2101. +#if defined(CONFIG_MSM_N_WAY_SMD)
  2102. #define DEM_MAX_PORT_NAME_LEN (20)
  2103. struct msm_dem_slave_data {
  2104. uint32_t sleep_time;
  2105. @@ -87,6 +72,21 @@ struct msm_dem_slave_data {
  2106. char smd_port_name[DEM_MAX_PORT_NAME_LEN];
  2107. uint32_t reserved2;
  2108. };
  2109. +#else
  2110. +#define SMSM_MAX_PORT_NAME_LEN 20
  2111. +struct smsm_interrupt_info {
  2112. + uint32_t interrupt_mask;
  2113. + uint32_t pending_interrupts;
  2114. + uint32_t wakeup_reason;
  2115. + uint32_t aArm_rpc_prog;
  2116. + uint32_t aArm_rpc_proc;
  2117. + char aArm_smd_port_name[SMSM_MAX_PORT_NAME_LEN];
  2118. + /* If the wakeup reason is GPIO then send the gpio info */
  2119. + uint32_t aArm_gpio_info;
  2120. + /*uint32_t interrupt_mask;
  2121. + uint32_t pending_interrupts;
  2122. + uint32_t wakeup_reason;*/
  2123. +};
  2124. #endif
  2125.  
  2126. #define SZ_DIAG_ERR_MSG 0xC8
  2127. @@ -96,7 +96,10 @@ struct msm_dem_slave_data {
  2128. #define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
  2129.  
  2130. #define SMSM_INIT 0x00000001
  2131. +#define SMSM_OSENTERED 0x00000002
  2132. +#define SMSM_SMDWAIT 0x00000004
  2133. #define SMSM_SMDINIT 0x00000008
  2134. +#define SMSM_RPCWAIT 0x00000010
  2135. #define SMSM_RPCINIT 0x00000020
  2136. #define SMSM_RESET 0x00000040
  2137. #define SMSM_RSA 0x00000080
  2138. @@ -108,6 +111,7 @@ struct msm_dem_slave_data {
  2139. #define SMSM_WFPI 0x00002000
  2140. #define SMSM_SLEEP 0x00004000
  2141. #define SMSM_SLEEPEXIT 0x00008000
  2142. +#define SMSM_OEMSBL_RELEASE 0x00010000
  2143. #define SMSM_APPS_REBOOT 0x00020000
  2144. #define SMSM_SYSTEM_POWER_DOWN 0x00040000
  2145. #define SMSM_SYSTEM_REBOOT 0x00080000
  2146. @@ -128,13 +132,7 @@ struct msm_dem_slave_data {
  2147. #define SMSM_WKUP_REASON_ALARM 0x00000010
  2148. #define SMSM_WKUP_REASON_RESET 0x00000020
  2149.  
  2150. -#ifndef CONFIG_ARCH_MSM_SCORPION
  2151. -enum smsm_state_item {
  2152. - SMSM_STATE_APPS = 1,
  2153. - SMSM_STATE_MODEM = 3,
  2154. - SMSM_STATE_COUNT,
  2155. -};
  2156. -#else
  2157. +//#if defined(CONFIG_MSM_N_WAY_SMD)
  2158. enum smsm_state_item {
  2159. SMSM_STATE_APPS,
  2160. SMSM_STATE_MODEM,
  2161. @@ -146,18 +144,24 @@ enum smsm_state_item {
  2162. SMSM_STATE_TIME_MASTER_DEM,
  2163. SMSM_STATE_COUNT,
  2164. };
  2165. -#endif
  2166. +//#else
  2167. +//enum smsm_state_item {
  2168. +// SMSM_STATE_APPS = 1,
  2169. +// SMSM_STATE_MODEM = 3,
  2170. +// SMSM_STATE_COUNT,
  2171. +//};
  2172. +//#endif
  2173.  
  2174. void *smem_alloc(unsigned id, unsigned size);
  2175. int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask);
  2176. uint32_t smsm_get_state(enum smsm_state_item item);
  2177. int smsm_set_sleep_duration(uint32_t delay);
  2178. -void smsm_print_sleep_info(void);
  2179. +int smsm_set_sleep_limit(uint32_t sleep_limit);
  2180. +void smsm_print_sleep_info(unsigned wakeup_reason_only);
  2181.  
  2182. #define SMEM_NUM_SMD_CHANNELS 64
  2183.  
  2184. -typedef enum
  2185. -{
  2186. +typedef enum {
  2187. /* fixed items */
  2188. SMEM_PROC_COMM = 0,
  2189. SMEM_HEAP_INFO,
  2190. @@ -213,6 +217,7 @@ typedef enum
  2191. SMEM_ID_VENDOR1,
  2192. SMEM_ID_VENDOR2,
  2193. SMEM_HW_SW_BUILD_ID,
  2194. +//#if defined(CONFIG_MSM_N_WAY_SMD)
  2195. SMEM_SMD_BLOCK_PORT_BASE_ID,
  2196. SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
  2197. SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
  2198. @@ -232,7 +237,16 @@ typedef enum
  2199. SMEM_SMEM_LOG_POWER_WRAP,
  2200. SMEM_SMEM_LOG_POWER_EVENTS,
  2201. SMEM_ERR_CRASH_LOG,
  2202. - SMEM_ERR_F3_TRACE_LOG,
  2203. + SMEM_ERR_F3_TRACE_LOG,
  2204. + SMEM_SMD_BRIDGE_ALLOC_TABLE,
  2205. + SMEM_SMDLITE_TABLE,
  2206. + SMEM_SD_IMG_UPGRADE_STATUS,
  2207. + SMEM_SEFS_INFO,
  2208. +//#else
  2209. +// SMEM_SMD_FIFO_BASE_ID,
  2210. +// SMEM_SMEM_LAST = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
  2211. +//#endif
  2212. +
  2213. SMEM_NUM_ITEMS,
  2214. } smem_mem_type;
  2215.  
  2216. @@ -250,69 +264,6 @@ typedef enum
  2217.  
  2218. #define SMD_HEADER_SIZE 20
  2219.  
  2220. -struct smd_alloc_elm {
  2221. - char name[20];
  2222. - uint32_t cid;
  2223. - uint32_t ctype;
  2224. - uint32_t ref_count;
  2225. -};
  2226. -
  2227. -struct smd_half_channel {
  2228. - unsigned state;
  2229. - unsigned char fDSR;
  2230. - unsigned char fCTS;
  2231. - unsigned char fCD;
  2232. - unsigned char fRI;
  2233. - unsigned char fHEAD;
  2234. - unsigned char fTAIL;
  2235. - unsigned char fSTATE;
  2236. - unsigned char fUNUSED;
  2237. - unsigned tail;
  2238. - unsigned head;
  2239. -} __attribute__(( aligned(4), packed ));
  2240. -
  2241. -struct smd_shared_v1 {
  2242. - struct smd_half_channel ch0;
  2243. - unsigned char data0[SMD_BUF_SIZE];
  2244. - struct smd_half_channel ch1;
  2245. - unsigned char data1[SMD_BUF_SIZE];
  2246. -};
  2247. -
  2248. -struct smd_shared_v2 {
  2249. - struct smd_half_channel ch0;
  2250. - struct smd_half_channel ch1;
  2251. -};
  2252. -
  2253. -struct smd_channel {
  2254. - volatile struct smd_half_channel *send;
  2255. - volatile struct smd_half_channel *recv;
  2256. - unsigned char *send_data;
  2257. - unsigned char *recv_data;
  2258. -
  2259. - unsigned fifo_mask;
  2260. - unsigned fifo_size;
  2261. - unsigned current_packet;
  2262. - unsigned n;
  2263. -
  2264. - struct list_head ch_list;
  2265. -
  2266. - void *priv;
  2267. - void (*notify)(void *priv, unsigned flags);
  2268. -
  2269. - int (*read)(struct smd_channel *ch, void *data, int len);
  2270. - int (*write)(struct smd_channel *ch, const void *data, int len);
  2271. - int (*read_avail)(struct smd_channel *ch);
  2272. - int (*write_avail)(struct smd_channel *ch);
  2273. -
  2274. - void (*update_state)(struct smd_channel *ch);
  2275. - unsigned last_state;
  2276. - void (*notify_other_cpu)(void);
  2277. - unsigned type;
  2278. -
  2279. - char name[32];
  2280. - struct platform_device pdev;
  2281. -};
  2282. -
  2283. #define SMD_TYPE_MASK 0x0FF
  2284. #define SMD_TYPE_APPS_MODEM 0x000
  2285. #define SMD_TYPE_APPS_DSP 0x001
  2286. @@ -323,13 +274,6 @@ struct smd_channel {
  2287. #define SMD_KIND_STREAM 0x100
  2288. #define SMD_KIND_PACKET 0x200
  2289.  
  2290. -extern struct list_head smd_ch_closed_list;
  2291. -extern struct list_head smd_ch_list_modem;
  2292. -extern struct list_head smd_ch_list_dsp;
  2293. -
  2294. -extern spinlock_t smd_lock;
  2295. -extern spinlock_t smem_lock;
  2296. -
  2297. void *smem_find(unsigned id, unsigned size);
  2298. void *smem_item(unsigned id, unsigned *size);
  2299. uint32_t raw_smsm_get_state(enum smsm_state_item item);
  2300. diff --git a/arch/arm/mach-msm/smd_qmi.c b/arch/arm/mach-msm/smd_qmi.c
  2301. index 50411df..3d47fbc 100644
  2302. --- a/arch/arm/mach-msm/smd_qmi.c
  2303. +++ b/arch/arm/mach-msm/smd_qmi.c
  2304. @@ -324,6 +324,18 @@ static void qmi_process_unicast_wds_msg(struct qmi_ctxt *ctxt,
  2305. if (qmi_get_status(msg, &err)) {
  2306. printk(KERN_ERR
  2307. "qmi: wds: network start failed (%04x)\n", err);
  2308. + if (msg->size == 0x000c && (msg->tlv)[10] == 0x0b) {
  2309. + printk(KERN_ERR
  2310. + "qmi: wds: pdp activation collided with CCFC\n");
  2311. + ctxt->state = STATE_OFFLINE;
  2312. + ctxt->state_dirty = 1;
  2313. + }
  2314. + if (msg->size == 0x000c && (msg->tlv)[10] == 0x0c) {
  2315. + printk(KERN_ERR
  2316. + "qmi: wds: pdp activation failed. Cause: Operator-determined barring\n");
  2317. + ctxt->state = STATE_OFFLINE;
  2318. + ctxt->state_dirty = 1;
  2319. + }
  2320. } else if (qmi_get_tlv(msg, 0x01, sizeof(ctxt->wds_handle), &ctxt->wds_handle)) {
  2321. printk(KERN_INFO
  2322. "qmi: wds no handle?\n");
  2323. @@ -648,7 +660,7 @@ static int qmi_print_state(struct qmi_ctxt *ctxt, char *buf, int max)
  2324. }
  2325.  
  2326. i = scnprintf(buf, max, "STATE=%s\n", statename);
  2327. - i += scnprintf(buf + i, max - i, "CID=%d\n",ctxt->wds_client_id);
  2328. + i += scnprintf(buf + i, max - i, "CID=%d\n",ctxt->misc.minor);
  2329.  
  2330. if (ctxt->state != STATE_ONLINE){
  2331. return i;
  2332. diff --git a/arch/arm/mach-msm/smd_rpcrouter.c b/arch/arm/mach-msm/smd_rpcrouter.c
  2333. index d2f66c1..ba180dc 100644
  2334. --- a/arch/arm/mach-msm/smd_rpcrouter.c
  2335. +++ b/arch/arm/mach-msm/smd_rpcrouter.c
  2336. @@ -137,13 +137,7 @@ static int rpcrouter_send_control_msg(union rr_control_msg *msg)
  2337. unsigned long flags;
  2338. int need;
  2339.  
  2340. - RR("send control message cmd=%d srv.cmd=%d prog=%08x:%x id=%d:%08x\n", msg->cmd, msg->srv.cmd, msg->srv.prog, msg->srv.vers, msg->srv.pid, msg->srv.cid);
  2341. -
  2342. - if (!(msg->cmd == RPCROUTER_CTRL_CMD_HELLO
  2343. -#if defined(CONFIG_MSM_AMSS_VERSION_WINCE)
  2344. - || msg->cmd == RPCROUTER_CTRL_CMD_BYE
  2345. -#endif
  2346. - ) && !initialized) {
  2347. + if (!(msg->cmd == RPCROUTER_CTRL_CMD_HELLO) && !initialized) {
  2348. printk(KERN_ERR "rpcrouter_send_control_msg(): Warning, "
  2349. "router not initialized\n");
  2350. return -EINVAL;
  2351. @@ -400,10 +394,9 @@ static int process_control_msg(union rr_control_msg *msg, int len)
  2352.  
  2353. RR("x HELLO\n");
  2354. memset(&ctl, 0, sizeof(ctl));
  2355. -#if !defined(CONFIG_MSM_AMSS_VERSION_WINCE)
  2356. ctl.cmd = RPCROUTER_CTRL_CMD_HELLO;
  2357. rpcrouter_send_control_msg(&ctl);
  2358. -#endif
  2359. +
  2360. initialized = 1;
  2361.  
  2362. /* Send list of servers one at a time */
  2363. @@ -1248,12 +1241,15 @@ int msm_rpc_unregister_server(struct msm_rpc_endpoint *ept,
  2364. return 0;
  2365. }
  2366.  
  2367. +int msm_rpcrouter_close(void)
  2368. +{
  2369. + return smd_close(smd_channel);
  2370. +}
  2371. +
  2372. static int msm_rpcrouter_probe(struct platform_device *pdev)
  2373. {
  2374. int rc;
  2375. - union rr_control_msg msg = { 0 };
  2376. - pr_info("RPC Probe\n");
  2377. -
  2378. +
  2379. /* Initialize what we need to start processing */
  2380. INIT_LIST_HEAD(&local_endpoints);
  2381. INIT_LIST_HEAD(&remote_endpoints);
  2382. @@ -1270,8 +1266,6 @@ static int msm_rpcrouter_probe(struct platform_device *pdev)
  2383. if (rc < 0)
  2384. goto fail_destroy_workqueue;
  2385.  
  2386. - pr_info("RPC Init done\n");
  2387. -
  2388. /* Open up SMD channel 2 */
  2389. initialized = 0;
  2390. rc = smd_open("SMD_RPCCALL", &smd_channel, NULL, rpcrouter_smdnotify);
  2391. @@ -1279,22 +1273,6 @@ static int msm_rpcrouter_probe(struct platform_device *pdev)
  2392. goto fail_remove_devices;
  2393.  
  2394. queue_work(rpcrouter_workqueue, &work_read_data);
  2395. -
  2396. -#if defined(CONFIG_MSM_AMSS_VERSION_WINCE)
  2397. - msg.cmd = RPCROUTER_CTRL_CMD_BYE;
  2398. - rpcrouter_send_control_msg(&msg);
  2399. - msleep(50);
  2400. -
  2401. - /* wince rpc init */
  2402. - msg.cmd = RPCROUTER_CTRL_CMD_HELLO;
  2403. - rpcrouter_send_control_msg(&msg);
  2404. - msleep(50);
  2405. -
  2406. -
  2407. - process_control_msg(&msg, sizeof(msg));
  2408. - msleep(100);
  2409. -#endif
  2410. -
  2411. return 0;
  2412.  
  2413. fail_remove_devices:
  2414. diff --git a/arch/arm/mach-msm/smd_rpcrouter.h b/arch/arm/mach-msm/smd_rpcrouter.h
  2415. index a7416a2..aaf49f7 100644
  2416. --- a/arch/arm/mach-msm/smd_rpcrouter.h
  2417. +++ b/arch/arm/mach-msm/smd_rpcrouter.h
  2418. @@ -32,6 +32,9 @@
  2419. #define RPCROUTER_VERSION 1
  2420. #define RPCROUTER_PROCESSORS_MAX 4
  2421. #define RPCROUTER_MSGSIZE_MAX 512
  2422. +#if defined(CONFIG_ARCH_MSM7X30)
  2423. +#define RPCROUTER_PEND_REPLIES_MAX 32
  2424. +#endif
  2425.  
  2426. #define RPCROUTER_CLIENT_BCAST_ID 0xffffffff
  2427. #define RPCROUTER_ROUTER_ADDRESS 0xfffffffe
  2428. @@ -129,12 +132,26 @@ struct rr_remote_endpoint {
  2429. uint32_t cid;
  2430.  
  2431. int tx_quota_cntr;
  2432. +#if defined(CONFIG_ARCH_MSM7X30)
  2433. + int quota_restart_state;
  2434. +#endif
  2435. spinlock_t quota_lock;
  2436. wait_queue_head_t quota_wait;
  2437.  
  2438. struct list_head list;
  2439. };
  2440.  
  2441. +#if defined(CONFIG_ARCH_MSM7X30)
  2442. +struct msm_rpc_reply {
  2443. + struct list_head list;
  2444. + uint32_t pid;
  2445. + uint32_t cid;
  2446. + uint32_t prog; /* be32 */
  2447. + uint32_t vers; /* be32 */
  2448. + uint32_t xid; /* be32 */
  2449. +};
  2450. +#endif
  2451. +
  2452. struct msm_rpc_endpoint {
  2453. struct list_head list;
  2454.  
  2455. @@ -147,7 +164,12 @@ struct msm_rpc_endpoint {
  2456. struct wake_lock read_q_wake_lock;
  2457. wait_queue_head_t wait_q;
  2458. unsigned flags;
  2459. -
  2460. +#if defined(CONFIG_ARCH_MSM7X30)
  2461. + /* restart handling */
  2462. + int restart_state;
  2463. + spinlock_t restart_lock;
  2464. + wait_queue_head_t restart_wait;
  2465. +#endif
  2466. /* endpoint address */
  2467. uint32_t pid;
  2468. uint32_t cid;
  2469. @@ -171,6 +193,14 @@ struct msm_rpc_endpoint {
  2470. uint32_t reply_xid; /* be32 */
  2471. uint32_t next_pm; /* Pacmark sequence */
  2472.  
  2473. +#if defined(CONFIG_ARCH_MSM7X30)
  2474. + /* reply queue for inbound messages */
  2475. + struct list_head reply_pend_q;
  2476. + struct list_head reply_avail_q;
  2477. + spinlock_t reply_q_lock;
  2478. + uint32_t reply_cnt;
  2479. + struct wake_lock reply_q_wake_lock;
  2480. +#endif
  2481. /* device node if this endpoint is accessed via userspace */
  2482. dev_t dev;
  2483. };
  2484. @@ -181,6 +211,7 @@ int __msm_rpc_read(struct msm_rpc_endpoint *ept,
  2485. struct rr_fragment **frag,
  2486. unsigned len, long timeout);
  2487.  
  2488. +int msm_rpcrouter_close(void);
  2489. struct msm_rpc_endpoint *msm_rpcrouter_create_local_endpoint(dev_t dev);
  2490. int msm_rpcrouter_destroy_local_endpoint(struct msm_rpc_endpoint *ept);
  2491.  
  2492. @@ -190,6 +221,18 @@ int msm_rpcrouter_create_server_pdev(struct rr_server *server);
  2493. int msm_rpcrouter_init_devices(void);
  2494. void msm_rpcrouter_exit_devices(void);
  2495.  
  2496. +#if defined(CONFIG_ARCH_MSM7X30)
  2497. +void get_requesting_client(struct msm_rpc_endpoint *ept, uint32_t xid,
  2498. + struct msm_rpc_client_info *clnt_info);
  2499. +#endif
  2500. +
  2501. extern dev_t msm_rpcrouter_devno;
  2502. extern struct class *msm_rpcrouter_class;
  2503. +
  2504. +void xdr_init(struct msm_rpc_xdr *xdr);
  2505. +void xdr_init_input(struct msm_rpc_xdr *xdr, void *buf, uint32_t size);
  2506. +void xdr_init_output(struct msm_rpc_xdr *xdr, void *buf, uint32_t size);
  2507. +void xdr_clean_input(struct msm_rpc_xdr *xdr);
  2508. +void xdr_clean_output(struct msm_rpc_xdr *xdr);
  2509. +uint32_t xdr_read_avail(struct msm_rpc_xdr *xdr);
  2510. #endif
  2511. diff --git a/arch/arm/mach-msm/smd_rpcrouter_device.c b/arch/arm/mach-msm/smd_rpcrouter_device.c
  2512. index 16604ba..bdea3d0 100644
  2513. --- a/arch/arm/mach-msm/smd_rpcrouter_device.c
  2514. +++ b/arch/arm/mach-msm/smd_rpcrouter_device.c
  2515. @@ -246,7 +246,7 @@ int msm_rpcrouter_create_server_cdev(struct rr_server *server)
  2516. return -ENOBUFS;
  2517. }
  2518.  
  2519. -#if CONFIG_MSM_AMSS_VERSION >= 6350 || defined(CONFIG_ARCH_QSD8X50)
  2520. +#if CONFIG_MSM_AMSS_VERSION >= 6350 || defined(CONFIG_ARCH_QSD8X50) || defined(CONFIG_ARCH_MSM7X30)
  2521. /* Servers with bit 31 set are remote msm servers with hashkey version.
  2522. * Servers with bit 31 not set are remote msm servers with
  2523. * backwards compatible version type in which case the minor number
  2524. @@ -296,7 +296,7 @@ int msm_rpcrouter_create_server_pdev(struct rr_server *server)
  2525. {
  2526. sprintf(server->pdev_name, "rs%.8x:%.8x",
  2527. server->prog,
  2528. -#if CONFIG_MSM_AMSS_VERSION >= 6350 || defined(CONFIG_ARCH_QSD8X50)
  2529. +#if CONFIG_MSM_AMSS_VERSION >= 6350 || defined(CONFIG_ARCH_QSD8X50) || defined(CONFIG_ARCH_MSM7X30)
  2530. (server->vers & RPC_VERSION_MODE_MASK) ? server->vers :
  2531. (server->vers & RPC_VERSION_MAJOR_MASK));
  2532. #else
  2533. diff --git a/arch/arm/mach-msm/smd_tty.c b/arch/arm/mach-msm/smd_tty.c
  2534. index ef12bca..33af0d4 100644
  2535. --- a/arch/arm/mach-msm/smd_tty.c
  2536. +++ b/arch/arm/mach-msm/smd_tty.c
  2537. @@ -36,81 +36,111 @@ struct smd_tty_info {
  2538. struct tty_struct *tty;
  2539. struct wake_lock wake_lock;
  2540. int open_count;
  2541. + struct work_struct tty_work;
  2542. };
  2543.  
  2544. static struct smd_tty_info smd_tty[MAX_SMD_TTYS];
  2545. +static struct workqueue_struct *smd_tty_wq;
  2546.  
  2547. -static const struct smd_tty_channel_desc smd_default_tty_channels[] = {
  2548. - { .id = 0, .name = "SMD_DS" },
  2549. -#if defined(CONFIG_MSM_AMSS_VERSION_WINCE)
  2550. - { .id = 1, .name = "SMD_DATA1" },
  2551. -#endif
  2552. - { .id = 27, .name = "SMD_GPSNMEA" },
  2553. -};
  2554. -
  2555. -static const struct smd_tty_channel_desc *smd_tty_channels =
  2556. - smd_default_tty_channels;
  2557. -static int smd_tty_channels_len = ARRAY_SIZE(smd_default_tty_channels);
  2558. -
  2559. -int smd_set_channel_list(const struct smd_tty_channel_desc *channels, int len)
  2560. -{
  2561. - smd_tty_channels = channels;
  2562. - smd_tty_channels_len = len;
  2563. - return 0;
  2564. -}
  2565. -
  2566. -static void smd_tty_notify(void *priv, unsigned event)
  2567. +static void smd_tty_work_func(struct work_struct *work)
  2568. {
  2569. unsigned char *ptr;
  2570. int avail;
  2571. - struct smd_tty_info *info = priv;
  2572. +
  2573. + struct smd_tty_info *info = container_of(work,
  2574. + struct smd_tty_info,
  2575. + tty_work);
  2576. struct tty_struct *tty = info->tty;
  2577.  
  2578. if (!tty)
  2579. return;
  2580.  
  2581. - if (event != SMD_EVENT_DATA)
  2582. - return;
  2583. +
  2584. + mutex_lock(&smd_tty_lock);
  2585.  
  2586. for (;;) {
  2587. - if (test_bit(TTY_THROTTLED, &tty->flags)) break;
  2588. - avail = smd_read_avail(info->ch);
  2589. - if (avail == 0) break;
  2590. + if (test_bit(TTY_THROTTLED, &tty->flags))
  2591. + break;
  2592.  
  2593. - avail = tty_prepare_flip_string(tty, &ptr, avail);
  2594. + if (info->ch == 0) {
  2595. + printk(KERN_ERR "smd_tty_work_func: info->ch null\n");
  2596. + break;
  2597. + }
  2598.  
  2599. - if (smd_read(info->ch, ptr, avail) != avail) {
  2600. - /* shouldn't be possible since we're in interrupt
  2601. - ** context here and nobody else could 'steal' our
  2602. - ** characters.
  2603. - */
  2604. - printk(KERN_ERR "OOPS - smd_tty_buffer mismatch?!");
  2605. + avail = smd_read_avail(info->ch);
  2606. + if (avail == 0) {
  2607. + tty->low_latency = 0;
  2608. + tty_flip_buffer_push(tty);
  2609. + break;
  2610. }
  2611.  
  2612. - wake_lock_timeout(&info->wake_lock, HZ / 2);
  2613. - tty_flip_buffer_push(tty);
  2614. + ptr = NULL;
  2615. + avail = tty_prepare_flip_string(tty, &ptr, avail);
  2616. +
  2617. + if (avail && ptr) {
  2618. + if (smd_read(info->ch, ptr, avail) != avail) {
  2619. + /* shouldn't be possible since we're in interrupt
  2620. + * context here and nobody else could 'steal' our
  2621. + * characters.
  2622. + */
  2623. + printk(KERN_ERR "OOPS - smd_tty_buffer mismatch?!");
  2624. + }
  2625. + wake_lock_timeout(&info->wake_lock, HZ / 2);
  2626. + tty->low_latency = 1;
  2627. + tty_flip_buffer_push(tty);
  2628. + } else
  2629. + printk(KERN_ERR "smd_tty_work_func: tty_prepare_flip_string fail\n");
  2630. }
  2631.  
  2632. + mutex_unlock(&smd_tty_lock);
  2633. +
  2634. /* XXX only when writable and necessary */
  2635. tty_wakeup(tty);
  2636. }
  2637.  
  2638. +static void smd_tty_notify(void *priv, unsigned event)
  2639. +{
  2640. + struct smd_tty_info *info = priv;
  2641. +
  2642. + if (event != SMD_EVENT_DATA)
  2643. + return;
  2644. +
  2645. + queue_work(smd_tty_wq, &info->tty_work);
  2646. +}
  2647. +
  2648. static int smd_tty_open(struct tty_struct *tty, struct file *f)
  2649. {
  2650. int res = 0;
  2651. int n = tty->index;
  2652. struct smd_tty_info *info;
  2653. - const char *name = NULL;
  2654. - int i;
  2655. + const char *name;
  2656. +
  2657. + if (n == 0) {
  2658. + name = "SMD_DS";
  2659. + } else if (n == 1) {
  2660. + name = "SMD_DIAG";
  2661. + } else if (n == 9) {
  2662. +#if defined(CONFIG_MACH_DESIREC) || defined(CONFIG_ARCH_MSM7X30)
  2663. + name = "SMD_DATA4";
  2664. +#else
  2665. + name = "SMD_DATA9";
  2666. +#endif
  2667.  
  2668. - for (i = 0; i < smd_tty_channels_len; i++) {
  2669. - if (smd_tty_channels[i].id == n) {
  2670. - name = smd_tty_channels[i].name;
  2671. - break;
  2672. - }
  2673. - }
  2674. - if (!name)
  2675. + } else if (n == 27) {
  2676. + name = "SMD_GPSNMEA";
  2677. +#ifdef CONFIG_BUILD_OMA_DM
  2678. + } else if (n == 19) {
  2679. + /* MASD requested OMA_DM AT-channel */
  2680. + name = "SMD_DATA3";
  2681. +#endif
  2682. +#ifdef CONFIG_BUILD_CIQ
  2683. + } else if (n == 26) {
  2684. + /* CIQ Master/Slaver Bridge */
  2685. + name = "SMD_DATA20";
  2686. +#endif
  2687. + } else {
  2688. return -ENODEV;
  2689. + }
  2690.  
  2691. info = smd_tty + n;
  2692.  
  2693. @@ -124,6 +154,12 @@ static int smd_tty_open(struct tty_struct *tty, struct file *f)
  2694. smd_kick(info->ch);
  2695. } else {
  2696. res = smd_open(name, &info->ch, info, smd_tty_notify);
  2697. +#ifdef CONFIG_ARCH_QSD8X50
  2698. + /* 8x50 smd bug: channel open is too late to handle
  2699. + * smd write request */
  2700. + if (n == 19)
  2701. + smd_wait_until_opened(info->ch, 200);
  2702. +#endif
  2703. }
  2704. }
  2705. mutex_unlock(&smd_tty_lock);
  2706. @@ -137,6 +173,8 @@ static void smd_tty_close(struct tty_struct *tty, struct file *f)
  2707.  
  2708. if (info == 0)
  2709. return;
  2710. + /* wait for the work in workqueue to complete */
  2711. + flush_work(&info->tty_work);
  2712.  
  2713. mutex_lock(&smd_tty_lock);
  2714. if (--info->open_count == 0) {
  2715. @@ -151,20 +189,25 @@ static void smd_tty_close(struct tty_struct *tty, struct file *f)
  2716. mutex_unlock(&smd_tty_lock);
  2717. }
  2718.  
  2719. -static int smd_tty_write(struct tty_struct *tty, const unsigned char *buf, int len)
  2720. +static int smd_tty_write(struct tty_struct *tty,
  2721. + const unsigned char *buf, int len)
  2722. {
  2723. struct smd_tty_info *info = tty->driver_data;
  2724. int avail;
  2725. + int ret;
  2726.  
  2727. /* if we're writing to a packet channel we will
  2728. ** never be able to write more data than there
  2729. ** is currently space for
  2730. */
  2731. + mutex_lock(&smd_tty_lock);
  2732. avail = smd_write_avail(info->ch);
  2733. if (len > avail)
  2734. len = avail;
  2735. + ret = smd_write(info->ch, buf, len);
  2736. + mutex_unlock(&smd_tty_lock);
  2737.  
  2738. - return smd_write(info->ch, buf, len);
  2739. + return ret;
  2740. }
  2741.  
  2742. static int smd_tty_write_room(struct tty_struct *tty)
  2743. @@ -182,7 +225,8 @@ static int smd_tty_chars_in_buffer(struct tty_struct *tty)
  2744. static void smd_tty_unthrottle(struct tty_struct *tty)
  2745. {
  2746. struct smd_tty_info *info = tty->driver_data;
  2747. - smd_kick(info->ch);
  2748. + queue_work(smd_tty_wq, &info->tty_work);
  2749. + return;
  2750. }
  2751.  
  2752. static struct tty_operations smd_tty_ops = {
  2753. @@ -198,11 +242,17 @@ static struct tty_driver *smd_tty_driver;
  2754.  
  2755. static int __init smd_tty_init(void)
  2756. {
  2757. - int ret, i;
  2758. + int ret;
  2759. +
  2760. + smd_tty_wq = create_singlethread_workqueue("smd_tty");
  2761. + if (smd_tty_wq == 0)
  2762. + return -ENOMEM;
  2763.  
  2764. smd_tty_driver = alloc_tty_driver(MAX_SMD_TTYS);
  2765. - if (smd_tty_driver == 0)
  2766. + if (smd_tty_driver == 0) {
  2767. + destroy_workqueue(smd_tty_wq);
  2768. return -ENOMEM;
  2769. + }
  2770.  
  2771. smd_tty_driver->owner = THIS_MODULE;
  2772. smd_tty_driver->driver_name = "smd_tty_driver";
  2773. @@ -214,17 +264,34 @@ static int __init smd_tty_init(void)
  2774. smd_tty_driver->init_termios = tty_std_termios;
  2775. smd_tty_driver->init_termios.c_iflag = 0;
  2776. smd_tty_driver->init_termios.c_oflag = 0;
  2777. - smd_tty_driver->init_termios.c_cflag = B38400 | CS8 | CREAD;
  2778. + smd_tty_driver->init_termios.c_cflag = B115200 | CS8 | CREAD;
  2779. smd_tty_driver->init_termios.c_lflag = 0;
  2780. smd_tty_driver->flags = TTY_DRIVER_RESET_TERMIOS |
  2781. TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
  2782. tty_set_operations(smd_tty_driver, &smd_tty_ops);
  2783.  
  2784. ret = tty_register_driver(smd_tty_driver);
  2785. - if (ret) return ret;
  2786. -
  2787. - for (i = 0; i < smd_tty_channels_len; i++)
  2788. - tty_register_device(smd_tty_driver, smd_tty_channels[i].id, 0);
  2789. + if (ret)
  2790. + return ret;
  2791. +
  2792. + /* this should be dynamic */
  2793. + tty_register_device(smd_tty_driver, 0, 0);
  2794. + INIT_WORK(&smd_tty[0].tty_work, smd_tty_work_func);
  2795. + tty_register_device(smd_tty_driver, 1, 0);
  2796. + INIT_WORK(&smd_tty[1].tty_work, smd_tty_work_func);
  2797. + tty_register_device(smd_tty_driver, 9, 0);
  2798. + INIT_WORK(&smd_tty[9].tty_work, smd_tty_work_func);
  2799. + tty_register_device(smd_tty_driver, 27, 0);
  2800. + INIT_WORK(&smd_tty[27].tty_work, smd_tty_work_func);
  2801. +#ifdef CONFIG_BUILD_OMA_DM
  2802. + /* MASD requested OMA_DM AT-channel */
  2803. + tty_register_device(smd_tty_driver, 19, 0);
  2804. + INIT_WORK(&smd_tty[19].tty_work, smd_tty_work_func);
  2805. +#endif
  2806. +#ifdef CONFIG_BUILD_CIQ
  2807. + tty_register_device(smd_tty_driver, 26, 0);
  2808. + INIT_WORK(&smd_tty[26].tty_work, smd_tty_work_func);
  2809. +#endif
  2810.  
  2811. return 0;
  2812. }
  2813. diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
  2814. index 1523987..a1ed7a1 100644
  2815. --- a/arch/arm/mach-msm/timer.c
  2816. +++ b/arch/arm/mach-msm/timer.c
  2817. @@ -27,7 +27,6 @@
  2818.  
  2819. #include "smd_private.h"
  2820.  
  2821. -
  2822. enum {
  2823. MSM_TIMER_DEBUG_SYNC_STATE = 1U << 0,
  2824. MSM_TIMER_DEBUG_SYNC_UPDATE = 1U << 1,
  2825. @@ -36,7 +35,11 @@ enum {
  2826. static int msm_timer_debug_mask;
  2827. module_param_named(debug_mask, msm_timer_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
  2828.  
  2829. +#ifdef CONFIG_ARCH_MSM7X30
  2830. +#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
  2831. +#else
  2832. #define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
  2833. +#endif
  2834.  
  2835. #define TIMER_MATCH_VAL 0x0000
  2836. #define TIMER_COUNT_VAL 0x0004
  2837. @@ -50,7 +53,10 @@ module_param_named(debug_mask, msm_timer_debug_mask, int, S_IRUGO | S_IWUSR | S_
  2838.  
  2839. #define GPT_HZ 32768
  2840.  
  2841. -#ifdef CONFIG_ARCH_MSM_SCORPION
  2842. +#ifdef CONFIG_ARCH_MSM7X30
  2843. +#define DGT_HZ 6144000 /* Uses LPXO/4 (24.576 MHz / 4) */
  2844. +#define MSM_DGT_SHIFT (0)
  2845. +#elif CONFIG_ARCH_MSM_SCORPION
  2846. #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
  2847. #define MSM_DGT_SHIFT (0)
  2848. #else
  2849. @@ -215,7 +221,7 @@ static inline int check_timeout(struct msm_clock *clock, uint32_t timeout)
  2850. return (int32_t)(msm_read_timer_count(clock) - timeout) <= 0;
  2851. }
  2852.  
  2853. -#ifndef CONFIG_ARCH_MSM_SCORPION
  2854. +#ifndef CONFIG_MSM_N_WAY_SMD
  2855.  
  2856. static uint32_t msm_timer_sync_smem_clock(int exit_sleep)
  2857. {
  2858. @@ -457,23 +463,20 @@ int64_t msm_timer_enter_idle(void)
  2859. uint32_t count;
  2860. int32_t delta;
  2861.  
  2862. -// CotullaTODO: - disable idle...workaround for now?
  2863. - return 0;
  2864. -
  2865. if (clock != &msm_clocks[MSM_CLOCK_GPT] || msm_fast_timer_enabled)
  2866. return 0;
  2867.  
  2868. -// msm_timer_sync_smem_clock(0);
  2869. + msm_timer_sync_smem_clock(0);
  2870.  
  2871. count = msm_read_timer_count(clock);
  2872. if (clock->stopped++ == 0)
  2873. clock->stopped_tick = (count + clock->offset) >> clock->shift;
  2874. alarm = clock->alarm_vtime - clock->offset;
  2875. delta = alarm - count;
  2876. - if (delta <= -(int32_t)((clock->freq << clock->shift) >> 10))
  2877. - {
  2878. + if (delta <= -(int32_t)((clock->freq << clock->shift) >> 10)) {
  2879. /* timer should have triggered 1ms ago */
  2880. - printk(KERN_ERR "msm_timer_enter_idle: timer late %d, reprogram it\n", delta);
  2881. + printk(KERN_ERR "msm_timer_enter_idle: timer late %d, "
  2882. + "reprogram it\n", delta);
  2883. msm_timer_reactivate_alarm(clock);
  2884. }
  2885. if (delta <= 0)
  2886. @@ -487,16 +490,13 @@ void msm_timer_exit_idle(int low_power)
  2887. struct msm_clock *clock = msm_active_clock;
  2888. uint32_t smem_clock;
  2889.  
  2890. -// Cotulla - disable idle...workaround for now?
  2891. - return;
  2892. -
  2893. if (clock != &msm_clocks[MSM_CLOCK_GPT])
  2894. return;
  2895.  
  2896. if (low_power) {
  2897. if (!(readl(clock->regbase + TIMER_ENABLE) & TIMER_ENABLE_EN)) {
  2898. writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
  2899. -// smem_clock = msm_timer_sync_smem_clock(1);
  2900. + smem_clock = msm_timer_sync_smem_clock(1);
  2901. }
  2902. msm_timer_reactivate_alarm(clock);
  2903. }
  2904. @@ -543,19 +543,11 @@ unsigned long long sched_clock(void)
  2905. return result;
  2906. }
  2907.  
  2908. -/*
  2909. #ifdef CONFIG_MSM7X00A_USE_GP_TIMER
  2910. #define DG_TIMER_RATING 100
  2911. #else
  2912. #define DG_TIMER_RATING 300
  2913. #endif
  2914. -*/
  2915. -
  2916. -// for DGT timer
  2917. -#define DG_TIMER_RATING 300
  2918. -
  2919. -// for GPT timer
  2920. -//#define DG_TIMER_RATING 100
  2921.  
  2922. static struct msm_clock msm_clocks[] = {
  2923. [MSM_CLOCK_GPT] = {
  2924. @@ -583,15 +575,16 @@ static struct msm_clock msm_clocks[] = {
  2925. .dev_id = &msm_clocks[0].clockevent,
  2926. .irq = INT_GP_TIMER_EXP
  2927. },
  2928. +#if defined(CONFIG_ARCH_MSM7X30)
  2929. + .regbase = MSM_TMR_BASE + 4,
  2930. +#else
  2931. .regbase = MSM_GPT_BASE,
  2932. +#endif
  2933. .freq = GPT_HZ,
  2934. -
  2935. -
  2936. -/* .flags =
  2937. + .flags =
  2938. MSM_CLOCK_FLAGS_UNSTABLE_COUNT |
  2939. MSM_CLOCK_FLAGS_ODD_MATCH_WRITE |
  2940. MSM_CLOCK_FLAGS_DELAYED_WRITE_POST,
  2941. -*/
  2942. .write_delay = 9,
  2943. },
  2944. [MSM_CLOCK_DGT] = {
  2945. @@ -689,38 +682,35 @@ static void __init msm_timer_init(void)
  2946. {
  2947. int i;
  2948. int res;
  2949. -
  2950. - printk("msm_timer_init $$$\n");
  2951. -
  2952. - printk(" 1DIV = %08X\n", readl(MSM_GPT_BASE + 0x20));
  2953. - writel(3, MSM_GPT_BASE + 0x20);
  2954. - printk(" 2DIV = %08X\n", readl(MSM_GPT_BASE + 0x20));
  2955. -
  2956. - for (i = 0; i < ARRAY_SIZE(msm_clocks); i++)
  2957. - {
  2958. +
  2959. + for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
  2960. struct msm_clock *clock = &msm_clocks[i];
  2961. struct clock_event_device *ce = &clock->clockevent;
  2962. struct clocksource *cs = &clock->clocksource;
  2963. writel(0, clock->regbase + TIMER_ENABLE);
  2964. - writel(1, clock->regbase + TIMER_CLEAR);
  2965. + writel(0, clock->regbase + TIMER_CLEAR);
  2966. writel(~0, clock->regbase + TIMER_MATCH_VAL);
  2967. while (msm_read_timer_count(clock)) ; /* wait for clock to clear */
  2968.  
  2969. ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
  2970. /* allow at least 10 seconds to notice that the timer wrapped */
  2971. - ce->max_delta_ns = clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
  2972. + ce->max_delta_ns =
  2973. + clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
  2974. /* ticks gets rounded down by one */
  2975. - ce->min_delta_ns = clockevent_delta2ns(clock->write_delay + 4, ce);
  2976. + ce->min_delta_ns =
  2977. + clockevent_delta2ns(clock->write_delay + 4, ce);
  2978. ce->cpumask = cpumask_of(0);
  2979.  
  2980. cs->mult = clocksource_hz2mult(clock->freq, cs->shift);
  2981. res = clocksource_register(cs);
  2982. if (res)
  2983. - printk(KERN_ERR "msm_timer_init: clocksource_register failed for %s\n", cs->name);
  2984. + printk(KERN_ERR "msm_timer_init: clocksource_register "
  2985. + "failed for %s\n", cs->name);
  2986.  
  2987. res = setup_irq(clock->irq.irq, &clock->irq);
  2988. if (res)
  2989. - printk(KERN_ERR "msm_timer_init: setup_irq failed for %s\n", cs->name);
  2990. + printk(KERN_ERR "msm_timer_init: setup_irq "
  2991. + "failed for %s\n", cs->name);
  2992.  
  2993. clockevents_register_device(ce);
  2994. }
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