Automati: Žmigavac sa prelaskom stanja prilikom puštanje dug

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-- Company:
-- Engineer:
--
-- Create Date:    22:06:10 12/03/2014
-- Design Name:
-- Module Name:    MainModule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MainModule is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           inLEFT : in  STD_LOGIC;
           inRIGHT : in  STD_LOGIC;
           inHAZ : in  STD_LOGIC;
           oLEFT : out  STD_LOGIC_VECTOR (2 downto 0);
           oRIGHT : out  STD_LOGIC_VECTOR (2 downto 0)
    );
end MainModule;

architecture Behavioral of MainModule is
    type tSTATES is (IDLE, L1, L2, L3, R1, R2, R3, LR3);
    signal sSTATE: tSTATES;

    signal sDEVIDER: STD_LOGIC_VECTOR(23 downto 0);
    signal sENABLE_CS: STD_LOGIC;
    constant cDEVIDER_END: integer := 12;-- * 1000 * 1000 / 2;

    signal sFORCE_ENABLE_CS: STD_LOGIC; -- ButtonsFix

    signal sLEFT, sRIGHT, sHAZ, sLEFT_RIGHT: STD_LOGIC;
begin
    -- Proces u kome je realizovan automat, sa asihronim resetom
    Automat: process (iCLK, inRST) begin
        if (inRST = '0') then
            sSTATE <= IDLE;

        elsif (rising_edge(iCLK)) then
            if (sENABLE_CS = '1' or (sFORCE_ENABLE_CS = '1' and sSTATE = IDLE)) then
                case (sSTATE) is
                    when IDLE => if (sLEFT = '1') then
                                        sSTATE <= L1;
                                    elsif (sRIGHT = '1') then
                                        sSTATE <= R1;
                                    elsif (sHAZ = '1' or sLEFT_RIGHT = '1') then
                                        sSTATE <= LR3;
                                    else
                                        sSTATE <= IDLE;
                                    end if;

                    when L1 => sSTATE <= L2;
                    when L2 => sSTATE <= L3;
                    when L3 => sSTATE <= IDLE;

                    when R1 => sSTATE <= R2;
                    when R2 => sSTATE <= R3;
                    when R3 => sSTATE <= IDLE;

                    when LR3 => sSTATE <= IDLE;

                    --when others => sSTATE <= IDLE;
                end case;
            end if;
        end if;
    end process;

    -- Binarni djelitelj
    -- 12*10^6 = 2^x; log_2(12*10^6) = x; x = 24
    Divider: process (iCLK, inRST) begin
        if (inRST = '0') then
            sDEVIDER <= (others => '0');
            sENABLE_CS <= '0';
        elsif (rising_edge(iCLK)) then
            if (sDEVIDER = cDEVIDER_END) then
                sDEVIDER <= (others => '0');
                sENABLE_CS <= '1';
            elsif (sFORCE_ENABLE_CS = '1') then
                sDEVIDER <= (others => '0');
            else
                sENABLE_CS <= '0';
                sDEVIDER <= sDEVIDER + 1;
            end if;
        end if;
    end process;


    ButtonsFix: process (inRST, inLEFT, inRIGHT, inHAZ, sSTATE) begin
        if (inRST = '0') then
            sFORCE_ENABLE_CS <= '0';
            sLEFT <= '0';
            sRIGHT <= '0';
            sHAZ <= '0';
            sLEFT_RIGHT <= '0';

        elsif (sSTATE = IDLE) then
            if (rising_edge(inHAZ)) then
                sFORCE_ENABLE_CS <= '1';
                sHAZ <= '1';
            elsif (rising_edge(inLEFT)) then
                sFORCE_ENABLE_CS <= '1';
                sLEFT <= '1';
            elsif (rising_edge(inRIGHT)) then
                sFORCE_ENABLE_CS <= '1';
                sRIGHT <= '1';
            end if;
        else
            sFORCE_ENABLE_CS <= '0';
            sLEFT <= '0';
            sRIGHT <= '0';
            sHAZ <= '0';
            sLEFT_RIGHT <= '0';
        end if;
    end process;


    -- Dodjela ukljucivanje dioda zavisno od stanja
    oLEFT <= "000" when sSTATE = IDLE else
        "001" when sSTATE = L1 else
        "011" when sSTATE = L2 else
        "111" when sSTATE = L3 else
        "111" when sSTATE = LR3 else
        "000";  -- R1, R2, R3


    oRIGHT <= "000" when sSTATE = IDLE else
        "100" when sSTATE = R1 else
        "110" when sSTATE = R2 else
        "111" when sSTATE = R3 else
        "111" when sSTATE = LR3 else
        "000";  -- L1, L2, L3

end Behavioral;