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Sep 27th, 2016
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VHDL 0.82 KB | None | 0 0
  1. ----------------------------------------------------------------------
  2.     -- This process records the address translation simulation to file. --
  3.     -- Video RAM address is translated (row,column) -> (linear).        --
  4.     ----------------------------------------------------------------------
  5.     --process(addr_rec.ready)
  6.     process
  7.     variable line_var : line;
  8.     file     text_hnd : text;
  9.     variable filename : string(1 to 55):= "C:\_downloads\processors\_to_board\vga_addr_records.txt";
  10.     variable addr_var : integer;
  11.    
  12.     begin
  13.         file_open(text_hnd, filename, write_mode);
  14.         loop
  15.         exit when simulation_done = '1';           
  16.             addr_var := addr_rec.addr;
  17.             write(line_var, integer'image(addr_var));      
  18.             writeline(text_hnd, line_var);         
  19.         end loop;
  20.         file_close(text_hnd);
  21.         wait;
  22.     end process;
  23.  
  24.     simulation_done <= '1' after 64 us;
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