module trecizadatak (HEX0,SW);
    input [17:0]SW;
    output [0:6]HEX0;
    wire [17:0]ulaz;
    assign ulaz = SW[17:0];
    reg[3:0] broj;
    always @(*) begin
        broj <=  ( ulaz ^ ulaz ) % 7;
        end
    b2d_ssd (broj, HEX0);
endmodule

module b2d_ssd (X, SSD);
  input [3:0] X;
  output reg [0:6] SSD;

  always begin
    case(X)
      0:SSD=7'b0000001;
      1:SSD=7'b1001111;
      2:SSD=7'b0010010;
      3:SSD=7'b0000110;
      4:SSD=7'b1001100;
      5:SSD=7'b0100100;
      6:SSD=7'b0100000;
      7:SSD=7'b0001111;
      8:SSD=7'b0000000;
      9:SSD=7'b0001100;
    endcase
  end
endmodule