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Jul 17th, 2012
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  1. DefinitionBlock ("./dsdt.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00001000)
  2. {
  3. External (\_PR_.CPU7, DeviceObj)
  4. External (\_PR_.CPU6, DeviceObj)
  5. External (\_PR_.CPU5, DeviceObj)
  6. External (\_PR_.CPU4, DeviceObj)
  7. External (\_PR_.CPU3, DeviceObj)
  8. External (\_PR_.CPU2, DeviceObj)
  9. External (\_PR_.CPU1, DeviceObj)
  10. External (\_PR_.CPU0, DeviceObj)
  11.  
  12. Scope (\_PR.CPU0)
  13. {
  14. Name (VERS, "Core i7 3.9 GHz Maximum Clock SSDT based on Greggen\'s at tonymacx86.com 2012-05-16")
  15. Name (APSN, 0x04)
  16. Name (APSS, Package (0x18)
  17. {
  18. Package (0x06)
  19. {
  20. 0x0F3C,
  21. Zero,
  22. 0x0A,
  23. 0x0A,
  24. 0x2700,
  25. 0x2700
  26. },
  27.  
  28. Package (0x06)
  29. {
  30. 0x0ED8,
  31. Zero,
  32. 0x0A,
  33. 0x0A,
  34. 0x2600,
  35. 0x2600
  36. },
  37.  
  38. Package (0x06)
  39. {
  40. 0x0E74,
  41. Zero,
  42. 0x0A,
  43. 0x0A,
  44. 0x2500,
  45. 0x2500
  46. },
  47.  
  48. Package (0x06)
  49. {
  50. 0x0E10,
  51. Zero,
  52. 0x0A,
  53. 0x0A,
  54. 0x2400,
  55. 0x2400
  56. },
  57.  
  58. Package (0x06)
  59. {
  60. 0x0DAC,
  61. Zero,
  62. 0x0A,
  63. 0x0A,
  64. 0x2300,
  65. 0x2300
  66. },
  67.  
  68. Package (0x06)
  69. {
  70. 0x0D48,
  71. Zero,
  72. 0x0A,
  73. 0x0A,
  74. 0x2200,
  75. 0x2200
  76. },
  77.  
  78. Package (0x06)
  79. {
  80. 0x0CE4,
  81. Zero,
  82. 0x0A,
  83. 0x0A,
  84. 0x2100,
  85. 0x2100
  86. },
  87.  
  88. Package (0x06)
  89. {
  90. 0x0C80,
  91. Zero,
  92. 0x0A,
  93. 0x0A,
  94. 0x2000,
  95. 0x2000
  96. },
  97.  
  98. Package (0x06)
  99. {
  100. 0x0C1C,
  101. Zero,
  102. 0x0A,
  103. 0x0A,
  104. 0x1F00,
  105. 0x1F00
  106. },
  107.  
  108. Package (0x06)
  109. {
  110. 0x0BB8,
  111. Zero,
  112. 0x0A,
  113. 0x0A,
  114. 0x1E00,
  115. 0x1E00
  116. },
  117.  
  118. Package (0x06)
  119. {
  120. 0x0B54,
  121. Zero,
  122. 0x0A,
  123. 0x0A,
  124. 0x1D00,
  125. 0x1D00
  126. },
  127.  
  128. Package (0x06)
  129. {
  130. 0x0AF0,
  131. Zero,
  132. 0x0A,
  133. 0x0A,
  134. 0x1C00,
  135. 0x1C00
  136. },
  137.  
  138. Package (0x06)
  139. {
  140. 0x0A8C,
  141. Zero,
  142. 0x0A,
  143. 0x0A,
  144. 0x1B00,
  145. 0x1B00
  146. },
  147.  
  148. Package (0x06)
  149. {
  150. 0x0A28,
  151. Zero,
  152. 0x0A,
  153. 0x0A,
  154. 0x1A00,
  155. 0x1A00
  156. },
  157.  
  158. Package (0x06)
  159. {
  160. 0x09C4,
  161. Zero,
  162. 0x0A,
  163. 0x0A,
  164. 0x1900,
  165. 0x1900
  166. },
  167.  
  168. Package (0x06)
  169. {
  170. 0x0960,
  171. Zero,
  172. 0x0A,
  173. 0x0A,
  174. 0x1800,
  175. 0x1800
  176. },
  177.  
  178. Package (0x06)
  179. {
  180. 0x08FC,
  181. Zero,
  182. 0x0A,
  183. 0x0A,
  184. 0x1700,
  185. 0x1700
  186. },
  187.  
  188. Package (0x06)
  189. {
  190. 0x0898,
  191. Zero,
  192. 0x0A,
  193. 0x0A,
  194. 0x1600,
  195. 0x1600
  196. },
  197.  
  198. Package (0x06)
  199. {
  200. 0x0834,
  201. Zero,
  202. 0x0A,
  203. 0x0A,
  204. 0x1500,
  205. 0x1500
  206. },
  207.  
  208. Package (0x06)
  209. {
  210. 0x07D0,
  211. Zero,
  212. 0x0A,
  213. 0x0A,
  214. 0x1400,
  215. 0x1400
  216. },
  217.  
  218. Package (0x06)
  219. {
  220. 0x076C,
  221. Zero,
  222. 0x0A,
  223. 0x0A,
  224. 0x1300,
  225. 0x1300
  226. },
  227.  
  228. Package (0x06)
  229. {
  230. 0x0708,
  231. Zero,
  232. 0x0A,
  233. 0x0A,
  234. 0x1200,
  235. 0x1200
  236. },
  237.  
  238. Package (0x06)
  239. {
  240. 0x06A4,
  241. Zero,
  242. 0x0A,
  243. 0x0A,
  244. 0x1100,
  245. 0x1100
  246. },
  247.  
  248. Package (0x06)
  249. {
  250. 0x0640,
  251. Zero,
  252. 0x0A,
  253. 0x0A,
  254. 0x1000,
  255. 0x1000
  256. }
  257. })
  258. Method (ACST, 0, NotSerialized)
  259. {
  260. Return (Package (0x06)
  261. {
  262. One,
  263. 0x04,
  264. Package (0x04)
  265. {
  266. ResourceTemplate ()
  267. {
  268. Register (FFixedHW,
  269. 0x01, // Bit Width
  270. 0x02, // Bit Offset
  271. 0x0000000000000000, // Address
  272. 0x01, // Access Size
  273. )
  274. },
  275.  
  276. One,
  277. 0x03,
  278. 0x03E8
  279. },
  280.  
  281. Package (0x04)
  282. {
  283. ResourceTemplate ()
  284. {
  285. Register (FFixedHW,
  286. 0x01, // Bit Width
  287. 0x02, // Bit Offset
  288. 0x0000000000000010, // Address
  289. 0x03, // Access Size
  290. )
  291. },
  292.  
  293. 0x03,
  294. 0xCD,
  295. 0x01F4
  296. },
  297.  
  298. Package (0x04)
  299. {
  300. ResourceTemplate ()
  301. {
  302. Register (FFixedHW,
  303. 0x01, // Bit Width
  304. 0x02, // Bit Offset
  305. 0x0000000000000020, // Address
  306. 0x03, // Access Size
  307. )
  308. },
  309.  
  310. 0x06,
  311. 0xF5,
  312. 0x015E
  313. },
  314.  
  315. Package (0x04)
  316. {
  317. ResourceTemplate ()
  318. {
  319. Register (FFixedHW,
  320. 0x01, // Bit Width
  321. 0x02, // Bit Offset
  322. 0x0000000000000030, // Address
  323. 0x03, // Access Size
  324. )
  325. },
  326.  
  327. 0x07,
  328. 0xF5,
  329. 0xC8
  330. }
  331. })
  332. }
  333. }
  334.  
  335. Scope (\_PR.CPU1)
  336. {
  337. Method (APSS, 0, NotSerialized)
  338. {
  339. Return (\_PR.CPU0.APSS)
  340. }
  341. }
  342.  
  343. Scope (\_PR.CPU2)
  344. {
  345. Method (APSS, 0, NotSerialized)
  346. {
  347. Return (\_PR.CPU0.APSS)
  348. }
  349. }
  350.  
  351. Scope (\_PR.CPU3)
  352. {
  353. Method (APSS, 0, NotSerialized)
  354. {
  355. Return (\_PR.CPU0.APSS)
  356. }
  357. }
  358.  
  359. Scope (\_PR.CPU4)
  360. {
  361. Method (APSS, 0, NotSerialized)
  362. {
  363. Return (\_PR.CPU0.APSS)
  364. }
  365. }
  366.  
  367. Scope (\_PR.CPU5)
  368. {
  369. Method (APSS, 0, NotSerialized)
  370. {
  371. Return (\_PR.CPU0.APSS)
  372. }
  373. }
  374.  
  375. Scope (\_PR.CPU6)
  376. {
  377. Method (APSS, 0, NotSerialized)
  378. {
  379. Return (\_PR.CPU0.APSS)
  380. }
  381. }
  382.  
  383. Scope (\_PR.CPU7)
  384. {
  385. Method (APSS, 0, NotSerialized)
  386. {
  387. Return (\_PR.CPU0.APSS)
  388. }
  389. }
  390. }
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