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- `define reset 'h00 // reset state
- `define fetch 'h10 // load instruction to instruction register
- reg [state_width-1 : 0] state = `reset, state_next;
- // FSM - sequential part
- always @(posedge clk) begin
- state <= `reset;
- if(!rst)
- state <= state_next;
- end
- case(state)
- `reset: begin
- state_next = `fetch;
- end
- `fetch: begin
- cp_oe = 1;
- am_we = 1;
- state_next = `fetch + 1;
- end
- `fetch + 'd1: begin
- am_oe = 1;
- state_next = `fetch + 2;
- end
- `fetch + 'd2: begin
- ram_oe = 1;
- ri_we = 1;
- state_next = `reset;
- end
- default: ;
- endcase
- end
- assign disp_state = state;
- endmodule
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