PCMCIA SRAM CPLD ctrl

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY main IS
    PORT ( ce1 : IN  STD_LOGIC;
           ce2 : IN  STD_LOGIC;
           reg : IN  STD_LOGIC;
           a0 : IN  STD_LOGIC;
           oe_even : OUT  STD_LOGIC;    -- OE for even byte
           oe_odd : OUT  STD_LOGIC; -- OE for odd byte
           oe_oddlow : OUT  STD_LOGIC;  -- OE odd byte on d0-d7
           ce_attr : OUT  STD_LOGIC;    -- CE for attribute memory
           ce_upp : OUT  STD_LOGIC; -- CE for upper SRAM
           ce_low : OUT  STD_LOGIC);    -- CE for lower SRAM
END main;

ARCHITECTURE behavioral OF main IS

BEGIN

    ce_low <= '0' WHEN reg='1' AND ce1='0' ELSE '1';
    ce_upp <= '0' WHEN reg='1' AND ce2='0' ELSE '1';

    oe_even <= '0' WHEN reg='1' AND ce1='0' AND ce2='0' ELSE -- x16
           '0' WHEN reg='1' AND ce1='0' AND ce2='1' AND a0='0' ELSE -- x8
           '1';

    oe_odd <= '0' WHEN reg='1' AND ce1='0' AND ce2='0' ELSE -- x16
          '0' WHEN reg='1' AND ce1='1' AND ce2='0' ELSE -- x8
          '1';

    -- separate output enable for odd byte on d7-d0
    oe_oddlow <= '0' WHEN reg='1' AND ce1='0' AND ce2='1' AND a0='1' ELSE -- x8
             '1';

    ce_attr <= '0' WHEN reg='0' AND ce1='0' AND ce2='0' ELSE
           '0' WHEN reg='0' AND ce1='0' AND ce2='1' AND a0='0' ELSE
           '1';

END behavioral;