`timescale 1ns / 1ps

 module top(
        input iClk_32Mhz,
        input iRst_n,

        //input [3:0]iDip,

        input iSpi_sck,
        input iSpi_mosi,
        //input iSpi_miso,
        input iSpi_cs_n,

        input iI2s_lrcin,
        input iI2s_lrcout,
        input iI2s_din,
        input iI2s_bclk,

        //input iRotEncA,
        //input iRotEncB,

        //input iHiZSat,

        output oCodecClk,

        output oI2s_dout,

        //output oInterrupt,
        output [2:0]oLed
    );

    // Clocking
    wire wClkMain;
    wire wPllLocked;
    wire wChipReady;
    assign wChipReady = (iRst_n & wPllLocked);

    // SPI
    wire wSpiNewData;
    wire [15:0] wSpiRegAddr;
    wire [7:0] wSpiData;

    // Registers
    wire [7:0] oDistoLevel;

    //I2S
    wire [15:0] wI2sDataInRight;
    wire [15:0] wI2sDataInLeft;

    reg [15:0] rRightLoopback;
    reg [15:0] rLeftLoopback;

    reg rLastRightReady;
    reg rLastLeftReady;

    wire wRightReady;
    wire wLeftReady;

    // Outputs
    assign oLed[1:0] = oDistoLevel[1:0];
    assign oLed[2] = wChipReady;
    //assign oInterrupt = |oDistoLevel;

    pll chip_pll
    (
        .iClk(iClk_32Mhz),
        .oClk_main(wClkMain),
        .oClkCodec(oCodecClk),
        .oReset(!iRst_n),
        .oLocked(wPllLocked)
    );

    spi spi_in(
        .iClk(wClkMain),
        .iRst_n(wChipReady),

        .iMosi(iSpi_mosi),
        .iSck(iSpi_sck),
        .iCs_n(iSpi_cs_n),
        .oNewData(wSpiNewData),
        .oRegAddr(wSpiRegAddr),
        .oData(wSpiData)
    );


    register_map register_map1(
        .iClk(wClkMain),
        .iRst_n(wChipReady),
        .iAddr(wSpiRegAddr),
        .iData(wSpiData),
        .iLatch(wSpiNewData),

        .oDistoLevel(oDistoLevel)
    );

    i2s_slave i2s_instance
    (
        .iClk(wClkMain),
        .iRst_n(wChipReady),
        .iLrcIn(iI2s_lrcin),
        .iLrcOut(iI2s_lrcout),
        .iBclk(iI2s_bclk),
        .iDin(iI2s_din),

        .iLeftOutData(rLeftLoopback),
        .iRightOutData(rRightLoopback),

        .oDout(oI2s_dout),
        .oLeftInData(wI2sDataInLeft),
        .oRightInData(wI2sDataInRight),
        .oLeftInReady(wLeftReady),
        .oLeftOutStart(),
        .oRightInReady(wRightReady),
        .oRightOutStart()
    );

    always @(posedge wClkMain) begin
        if (!wChipReady)    begin
            rLastRightReady <= 1'b0;
            rLastLeftReady <= 1'b0;
            rRightLoopback <= 16'h0000;
            rLeftLoopback   <= 16'h0000;
        end
        else begin
            rLastRightReady <= wRightReady;
            rLastLeftReady  <= wLeftReady;

            if (!rLastRightReady & wRightReady)
                rRightLoopback <= wI2sDataInRight;
            if (!rLastLeftReady & wLeftReady)
                rLeftLoopback<= wI2sDataInLeft;
        end
    end

endmodule