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Sep 17th, 2015
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  1. #include <xc.h>
  2.  
  3. // CONFIG1H
  4. #pragma config FOSC = INTIO67   // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
  5. #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
  6. #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
  7.  
  8. // CONFIG2L
  9. #pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
  10. #pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
  11. #pragma config BORV = 18        // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)
  12.  
  13. // CONFIG2H
  14. #pragma config WDTEN = OFF      // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)
  15. #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
  16.  
  17. // CONFIG3H
  18. #pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
  19. #pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
  20. #pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
  21. #pragma config HFOFST = OFF     // HFINTOSC Fast Start-up (The system clock is held off until the HFINTOSC is stable.)
  22. #pragma config MCLRE = OFF      // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)
  23.  
  24. // CONFIG4L
  25. #pragma config STVREN = OFF     // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
  26. #pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
  27. #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
  28.  
  29. // CONFIG5L
  30. #pragma config CP0 = OFF        // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
  31. #pragma config CP1 = OFF        // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
  32. #pragma config CP2 = OFF        // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
  33. #pragma config CP3 = OFF        // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
  34.  
  35. // CONFIG5H
  36. #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
  37. #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
  38.  
  39. // CONFIG6L
  40. #pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
  41. #pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
  42. #pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
  43. #pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
  44.  
  45. // CONFIG6H
  46. #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
  47. #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
  48. #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
  49.  
  50. // CONFIG7L
  51. #pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
  52. #pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
  53. #pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
  54. #pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
  55.  
  56. // CONFIG7H
  57. #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
  58.  
  59. #define led1red         LATAbits.LATA4
  60. #define led1green       LATAbits.LATA5
  61. #define led1blue        LATEbits.LATE0
  62.  
  63. #define led2red         LATEbits.LATE1
  64. #define led2green       LATEbits.LATE2
  65. #define led2blue        LATAbits.LATA7
  66.  
  67. #define led3red         LATAbits.LATA6
  68. #define led3green       LATCbits.LATC0
  69. #define led3blue        LATCbits.LATC1
  70.  
  71. #define led4red         LATCbits.LATC2
  72. #define led4green       LATCbits.LATC3
  73. #define led4blue        LATDbits.LATD0
  74.  
  75. #define led5red         LATDbits.LATD1
  76. #define led5green       LATDbits.LATD2
  77. #define led5blue        LATDbits.LATD3
  78.  
  79. #define led6red         LATCbits.LATC4
  80. #define led6green       LATCbits.LATC6
  81. #define led6blue        LATDbits.LATD4
  82.  
  83. #define led7red         LATDbits.LATD5
  84. #define led7green       LATDbits.LATD6
  85. #define led7blue        LATDbits.LATD7
  86.  
  87. #define led8red         LATBbits.LATB0
  88. #define led8green       LATBbits.LATB1
  89. #define led8blue        LATBbits.LATB2
  90.  
  91. #define led9red         LATBbits.LATB3
  92. #define led9green       LATBbits.LATB4
  93. #define led9blue        LATBbits.LATB5
  94.  
  95.  
  96. //demas pines utilizados
  97. #define MCLR            PORTEbits.RE3
  98. #define PGC             LATBbits.LATB6
  99. #define PGD             LATBbits.LATB7
  100. #define ANALOG0         PORTAbits.RA0
  101. #define ANALOG1         PORTAbits.RA1
  102. #define ANALOG2         PORTAbits.RA2
  103. #define ANALOG3         PORTAbits.RA3
  104.  
  105.  
  106.  
  107.  
  108.  
  109. #define     duty1red    dutys[0]
  110. #define     duty1green  dutys[1]
  111. #define     duty1blue   dutys[2]
  112. #define     duty2red    dutys[3]
  113. #define     duty2green  dutys[4]
  114. #define     duty2blue   dutys[5]
  115. #define     duty3red    dutys[6]
  116. #define     duty3green  dutys[7]
  117. #define     duty3blue   dutys[8]
  118. #define     duty4red    dutys[9]
  119. #define     duty4green  dutys[10]
  120. #define     duty4blue   dutys[11]
  121. #define     duty5red    dutys[12]
  122. #define     duty5green  dutys[13]
  123. #define     duty5blue   dutys[14]    
  124. #define     duty6red    dutys[15]
  125. #define     duty6green  dutys[16]    
  126. #define     duty6blue   dutys[17]
  127. #define     duty7red    dutys[18]
  128. #define     duty7green  dutys[19]      
  129. #define     duty7blue   dutys[20]
  130. #define     duty8red    dutys[21]
  131. #define     duty8green  dutys[22]
  132. #define     duty8blue   dutys[23]
  133. #define     duty9red    dutys[24]
  134. #define     duty9green  dutys[25]
  135. #define     duty9blue   dutys[26]
  136.  
  137. unsigned char anchodepulso=0;
  138. unsigned char dutys[27] = { 245,100,100,
  139.                             10,10,10,
  140.                             10,10,10,
  141.                             10,10,10,
  142.                             10,10,10,
  143.                             10,150,10,
  144.                             10,10,10,
  145.                             10,10,10,
  146.                             100,100,100
  147. };
  148.  
  149.  
  150.  
  151.  
  152.  
  153. //pragma usado en xc18
  154. /*
  155. void myISR_Low(void);
  156. void myISR_High(void);
  157.  *
  158.  * #pragma code HIGH_INTERRUPT_VECTOR = 0x08
  159. void High_ISR (void){
  160.     _asm goto myISR_High _endasm
  161. }
  162. #pragma code LOW_INTERRUPT_VECTOR = 0x18
  163. void Low_ISR (void){
  164.     _asm goto myISR_Low _endasm
  165. }
  166. */
  167.  
  168. void interrupt YourHighPriorityISRCode(){
  169.     if(INTCONbits.TMR0IF){
  170.         //INTCONbits.TMR0IE=0;
  171.         anchodepulso++;
  172.        
  173.         if(anchodepulso<=duty1red){
  174.             led1red=1;
  175.         }else led1red=0;
  176.         if(anchodepulso<=duty1green){
  177.             led1green=1;
  178.         }else led1green=0;
  179.          if(anchodepulso<=duty1blue){
  180.             led1blue=1;
  181.         }else led1blue=0;          
  182.         if(anchodepulso<=duty2red){
  183.             led2red=1;
  184.         }else led2red=0;
  185.         if(anchodepulso<=duty2green){
  186.             led2green=1;
  187.         }else led2green=0;
  188.         if(anchodepulso<=duty2blue){
  189.             led2blue=1;
  190.         }else led2blue=0;
  191.        
  192.         if(anchodepulso<=duty3red){
  193.             led3red=1;
  194.         }else led3red=0;
  195.         if(anchodepulso<=duty3green){
  196.             led3green=1;
  197.         }else led3green=0;
  198.         if(anchodepulso<=duty3blue){
  199.             led3blue=1;
  200.         }else led3blue=0;
  201.        
  202.         if(anchodepulso<=duty4red){
  203.             led4red=1;
  204.         }else led4red=0;
  205.         if(anchodepulso<=duty4green){
  206.             led4green=1;
  207.         }else led4green=0;
  208.         if(anchodepulso<=duty4blue){
  209.             led4blue=1;
  210.         }else led4blue=0;
  211.        
  212.         if(anchodepulso<=duty5red){
  213.             led5red=1;
  214.         }else led5red=0;
  215.         if(anchodepulso<=duty5green){
  216.             led5green=1;
  217.         }else led5green=0;
  218.         if(anchodepulso<=duty5blue){
  219.             led5blue=1;
  220.         }else led5blue=0;
  221.        
  222.         if(anchodepulso<=duty6red){
  223.             led6red=1;
  224.         }else led6red=0;
  225.         if(anchodepulso<=duty6green){
  226.             led6green=1;
  227.         }else led6green=0;
  228.         if(anchodepulso<=duty6blue){
  229.             led6blue=1;
  230.         }else led6blue=0;
  231.        
  232.         if(anchodepulso<=duty7red){
  233.             led7red=1;
  234.         }else led7red=0;
  235.         if(anchodepulso<=duty7green){
  236.             led7green=1;
  237.         }else led7green=0;
  238.         if(anchodepulso<=duty7blue){
  239.             led7blue=1;
  240.         }else led7blue=0;
  241.        
  242.         if(anchodepulso<=duty8red){
  243.             led8red=1;
  244.         }else led8red=0;
  245.         if(anchodepulso<=duty8green){
  246.             led8green=1;
  247.         }else led8green=0;
  248.         if(anchodepulso<=duty8blue){
  249.             led8blue=1;
  250.         }else led8blue=0;
  251.        
  252.         if(anchodepulso<=duty9red){
  253.             led9red=1;
  254.         }else led9red=0;
  255.         if(anchodepulso<=duty9green){
  256.             led9green=1;
  257.         }else led9green=0;
  258.         if(anchodepulso<=duty9blue){
  259.             led9blue=1;
  260.         }else led9blue=0;
  261.         if(anchodepulso==255){
  262.             anchodepulso==0;
  263.         }
  264.        
  265.         //INTCONbits.TMR0IE=1;
  266.         //TMR0=255;
  267.         if(anchodepulso == 32) anchodepulso = 0;
  268.         INTCONbits.TMR0IF=0;
  269.         TMR0L = 200;
  270.     }
  271.     INTCONbits.GIE_GIEH=1; //IMPORTANTE HABILITARLAS PORQ SE DESHABILITAN CON INTERRUP
  272. }
  273.  
  274. /*
  275. void interrupt low_priority YourLowPriorityISRCode(){
  276.  
  277.     INTCONbits.PEIE_GIEL=0;//IMPORTANTE HABILITARLAS PORQ SE DESHABILITAN CON INTERRUP
  278. }
  279. */
  280.  
  281. void main(void) {
  282.    
  283.     OSCCONbits.IDLEN=0;
  284.     OSCCONbits.IRCF =0b111; //oscilador interno de 16Mhz
  285.     while(OSCCONbits.OSTS); // sino esta corriendo con oscilador interno quedarse aca
  286.     while(!OSCCONbits.IOFS); // espera que frecuencia del clok sea estable
  287.     OSCCONbits.SCS = 0b11; // clock del sistema sea interno
  288.     OSCTUNEbits.INTSRC=1;
  289.     OSCTUNEbits.PLLEN= 1; //habilito PLL osea que en 16Mhz con PLL DE 4 --> Fosc= 64MHz
  290.     OSCTUNEbits.TUN= 0; //oscilador funcione calibrado de fabrica
  291.    
  292.     INTCONbits.TMR0IE=0;
  293.     INTCONbits.INT0IE = 0;
  294.     INTCONbits.RBIE = 0;
  295.     INTCONbits.PEIE_GIEL=1;
  296.     INTCONbits.GIE_GIEH=1;
  297.  
  298.    
  299.     INTCON2bits.RBPU=0;
  300.     INTCON2bits.TMR0IP=1;
  301.     INTCON2bits.RBIP=0;
  302.    
  303.     INTCON3bits.INT2E=0;
  304.     INTCON3bits.INT1E=0;
  305.     INTCON3bits.INT1IP=0;
  306.     INTCON3bits.INT2IP=0;
  307.    
  308.     PIE1bits.ADIE=0;
  309.     PIE1bits.PSPIE=0;
  310.     PIE1bits.RCIE=0; //INT DEL EUSART
  311.     PIE1bits.TXIE=0; //INT DEL EUSART
  312.     PIE1bits.CCP1IE=0;
  313.     PIE1bits.TMR1IE=0;
  314.     PIE1bits.TMR2IE=0;
  315.    
  316.     PIE2bits.BCLIE=0;
  317.     PIE2bits.C1IE=0;
  318.     PIE2bits.C2IE=0;
  319.     PIE2bits.EEIE=0;
  320.     PIE2bits.HLVDIE=0;
  321.     PIE2bits.TMR3IE=0;
  322.     PIE2bits.CCP2IE=0;
  323.    
  324.     TRISB = 0b00000000; // 6 PWM DOS OCUPADOS POR PROGRAMACION RB6 Y RB7
  325.     TRISC = 0b10000000; // 6 PWM DOS OCUPADOS POR USART RC6 Y RC7
  326.     TRISD = 0b00000000; // 8 PWM
  327.     TRISE = 0b1000;     // 3 PWM  RE3 ES MCLR
  328.     TRISA = 0b00000011; // 4 PWM , SOBRAN 4 ADC RA0  RA1 RA2 Y RA3
  329.    
  330.     T0CONbits.T08BIT = 1;
  331.     T0CONbits.T0CS=0;
  332.     T0CONbits.PSA= 1; // SIN PRESCALER OSEA PRESCALER =1
  333.     TMR0L= 244; // desborda cada 75uS , cuando llega a 100 veces cumple un periodo de 13,333 KHz
  334.     TMR0H = 0;
  335.     INTCONbits.TMR0IE=1;
  336.     INTCONbits.TMR0IF = 0;
  337.     INTCONbits.PEIE_GIEL=0;
  338.     while(1){
  339.        
  340.     }
  341. }
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