Driver

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Driver is
    Port ( clk : in  STD_LOGIC;
           A : out  STD_LOGIC_VECTOR (15 downto 0);
           B : out  STD_LOGIC_VECTOR (15 downto 0);
           op_code : out  STD_LOGIC_VECTOR (2 downto 0));
end Driver;

architecture Behavioral of Driver is

type int_array is array (0 to 7) of Integer ;

signal cnt :Integer:=0 ;
signal op_count : Integer   range 0 to 3;
--signal lastOp:Integer:=0;

signal x:int_array ;
signal y: int_array ;
signal code : int_array ;

begin
x(0) <= 0 ;x(1) <= 1 ;x(2) <= 2 ;x(3) <= 3 ;x(4) <= 4 ;x(5) <= 5 ;x(6) <= 6 ;x(7) <= 7 ;

y(0) <= 8;y(1) <=  9;y(2) <=  10;y(3) <=  11;y(4) <=  12;y(5) <=  13;y(6) <=  14;y(7) <=  15;

code(0) <= 0;code(1) <= 1;code(2) <= 2;code(3) <= 3;code(4) <= 4;code(5) <= 5;code(6) <= 6;code(7) <= 7;

    --x <=(0,1,2,3,4,5,6,7);
    --y <=(8,9,10,11,12,13,14,15);
    --code  <=(0,1,2,3,4,5,6,7);

    driver_process :process(clk)

    begin
            if(clk'event and clk = '1') then
                cnt <= cnt + 1;
                if (cnt = 3)    then  -- clock counter
                --don't forget to change the range
                    A <=conv_std_logic_vector(x(op_count), 16);
                    B <=conv_std_logic_vector(y(op_count), 16);
                    op_code <= conv_std_logic_vector(code(op_count), 3);

    --              lastOp<=op_count+1;
                    op_count <= (op_count+1 mod 8);

                    cnt<=0;
                end if;
            end if;
    end process;
end Behavioral;