OddNumTestBench

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   12:40:07 10/24/2016
-- Design Name:
-- Module Name:   F:/rennnnnnn/lab1/lab1testbench.vhd
-- Project Name:  lab1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: OddNum
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY lab1testbench IS
END lab1testbench;

ARCHITECTURE behavior OF lab1testbench IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT OddNum
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c : IN  std_logic;
         y : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal c : std_logic := '0';

    --Outputs
   signal y : std_logic;
   -- No clocks detected in port list. Replace clock below with
   -- appropriate port name

begin
   uut: OddNum PORT MAP (
          a => a,
          b => b,
          c => c,
          y => y
        );
    tb : process
    begin
        --0
        wait for 100ns;
        a <= '0';
        b <= '0';
        c <= '0';
        --1
        wait for 100ns;
        a <= '0';
        b <= '0';
        c <= '1';
        --2
        wait for 100ns;
        a <= '0';
        b <= '1';
        c <= '0';
        --3
        wait for 100ns;
        a <= '0';
        b <= '1';
        c <= '1';
        --4
        wait for 100ns;
        a <= '1';
        b <= '0';
        c <= '0';
        --5
        wait for 100ns;
        a <= '1';
        b <= '0';
        c <= '1';
        --6
        wait for 100ns;
        a <= '1';
        b <= '1';
        c <= '0';
        --7
        wait for 100ns;
        a <= '1';
        b <= '1';
        c <= '1';
        wait;
    end process;
end;