HelloWorld.vhd:

library ieee;
    use ieee.std_logic_1164.ALL;
    use ieee.numeric_std.ALL;

-- Jednostka główna
entity HelloWorld is
    port(
        clk_in: IN STD_LOGIC;
        input0: IN STD_LOGIC;
        input1: IN STD_LOGIC;
        input2: IN STD_LOGIC;
        input3: IN STD_LOGIC;
        led0: OUT STD_LOGIC;
        led1: OUT STD_LOGIC;
        led2: OUT STD_LOGIC;
        led3: OUT STD_LOGIC
    );
end entity;

-- Architektura jednostki głównej
architecture HelloWorldImpl of HelloWorld is
begin
    u1: work.DelayedInputDebouncer
        generic map (clkCyclesDelay => 1000000)
        port map (clk_in, input0, led0);

    u2: work.DelayedInputDebouncer
        generic map (clkCyclesDelay => 5000000)
        port map (clk_in, input1, led1);

    u3: work.DelayedInputDebouncer
        generic map (clkCyclesDelay => 10000000)
        port map (clk_in, input2, led2);

    u4: work.DelayedInputDebouncer
        generic map (clkCyclesDelay => 20000000)
        port map (clk_in, input3, led3);

end architecture;






DelayedInputDebouncer.vhd:

library ieee;
    use ieee.std_logic_1164.ALL;
    use ieee.numeric_std.ALL;

-- Jednostka główna
entity DelayedInputDebouncer is
    generic (
        clkCyclesDelay: positive := 1000000
    );

    port (
        clk_in: IN STD_LOGIC;
        input: IN STD_LOGIC;
        output: OUT STD_LOGIC
    );
end entity;

-- Architektura jednostki głównej
architecture DelayedInputDebouncerImpl of DelayedInputDebouncer is
    signal counterReset : STD_LOGIC := '0';
    signal counterEnabled : STD_LOGIC := '0';
    signal counterQ : STD_LOGIC;
begin
    u1: work.PositiveCounter
        generic map (target => clkCyclesDelay)
        port map (clk_in, counterEnabled, counterQ, counterReset);

    process (clk_in)
        variable prevInputState : STD_LOGIC := '0';
    begin
        if (rising_edge(clk_in)) then
            if ((input xor prevInputState) = '1') then
                if (counterQ = '1') then
                    prevInputState := not prevInputState;
                    counterReset <= '1';
                else
                    counterEnabled <= '1';
                    counterReset <= '0';
                end if;
            elsif (counterQ = '1') then
                counterReset <= '1';
            end if;
        end if;

        output <= prevInputState;
    end process;
end architecture;






PositiveCounter.vhd:


library ieee;
    use ieee.std_logic_1164.ALL;
    use ieee.numeric_std.ALL;


-- Jednostka licznika od 0 do target
entity PositiveCounter is
    generic (
        target: positive := 1000000
    );

    port (
        clk_in: IN STD_LOGIC;
        enabled: IN STD_LOGIC;
        Q: OUT STD_LOGIC;
        reset: IN STD_LOGIC
    );
end entity;

-- Implementacja licznika
architecture PositiveCounterImpl of PositiveCounter is
begin
    process (clk_in)
        variable clkCounter : integer range 0 to target;
    begin
        if (rising_edge(clk_in)) then
            if (reset = '1') then
                clkCounter := 0;
                Q <= '0';
            elsif (enabled = '1' and clkCounter < target) then
                clkCounter := clkCounter + 1;
                Q <= '0';
            elsif (clkCounter = target) then
                Q <= '1';
            end if;
        end if;
    end process;
end architecture;