Verilog Array init

reg [6:0] expected[0:15];

// This throw an error:
// error: syntax error in reg variable list.
// reg [6:0] expected[0:15] = {
//         7'h3F, 7'h06, 7'h5B, 7'h4F,
//         7'h66, 7'h6D, 7'h7D, 7'h07,
//         7'h7F, 7'h67, 7'h7A, 7'h7C,
//         7'h39, 7'h5E, 7'h79, 7'h71
// };

initial begin

    // Verilog system tasks

    // $dumpfile genera un archivo
    // donde se almacenan todas las
    // variables del diseño
    $dumpfile("bcd2segments.vcd");
    $dumpvars(0, bcd2segments_tb);

    // This throw an error:
    // Cannot assign to array expected. Did you forget a word index?
    // expected = {
    //     7'h3F, 7'h06, 7'h5B, 7'h4F,
    //     7'h66, 7'h6D, 7'h7D, 7'h07,
    //     7'h7F, 7'h67, 7'h7A, 7'h7C,
    //     7'h39, 7'h5E, 7'h79, 7'h71
    // };

    // This is fine
    expected[4'd0] = 7'h3F;
    expected[4'd1] = 7'h06;
    expected[4'd2] = 7'h5B;
    expected[4'd3] = 7'h4F;
    expected[4'd4] = 7'h66;
    expected[4'd5] = 7'h6D;
    expected[4'd6] = 7'h7D;
    expected[4'd7] = 7'h07;
    expected[4'd8] = 7'h7F;
    expected[4'd9] = 7'h67;
    expected[4'd10] = 7'h7A;
    expected[4'd11] = 7'h7C;
    expected[4'd12] = 7'h39;
    expected[4'd13] = 7'h5E;
    expected[4'd14] = 7'h79;
    expected[4'd15] = 7'h71;

end