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  1. /* JZ MXU instructions simulation in C code
  2. *
  3. * fanoble [2007-07-24 20:05:59]
  4. */
  5.  
  6. #ifndef _JZ_MXU_H_
  7. #define _JZ_MXU_H_
  8.  
  9. #define ptn0 0
  10. #define ptn1 1
  11. #define ptn2 2
  12. #define ptn3 3
  13.  
  14. #ifdef WIN32
  15.  
  16. /* MXU registers */
  17.  
  18. #if 0
  19. #define xr0 0
  20. static int xr1, xr2, xr3, xr4, xr5, xr6, xr7, xr8, xr9;
  21. static int xr10, xr11, xr12, xr13, xr14, xr15, xr16;
  22. #else
  23.  
  24. static int mxu_xr[17] = {0};
  25.  
  26. #define xr0 mxu_xr[ 0]
  27. #define xr1 mxu_xr[ 1]
  28. #define xr2 mxu_xr[ 2]
  29. #define xr3 mxu_xr[ 3]
  30. #define xr4 mxu_xr[ 4]
  31. #define xr5 mxu_xr[ 5]
  32. #define xr6 mxu_xr[ 6]
  33. #define xr7 mxu_xr[ 7]
  34. #define xr8 mxu_xr[ 8]
  35. #define xr9 mxu_xr[ 9]
  36. #define xr10 mxu_xr[10]
  37. #define xr11 mxu_xr[11]
  38. #define xr12 mxu_xr[12]
  39. #define xr13 mxu_xr[13]
  40. #define xr14 mxu_xr[14]
  41. #define xr15 mxu_xr[15]
  42. #define xr16 mxu_xr[16]
  43.  
  44. #endif
  45.  
  46. #else /* WIN32 */
  47.  
  48. #define xr0 0
  49. #define xr1 1
  50. #define xr2 2
  51. #define xr3 3
  52. #define xr4 4
  53. #define xr5 5
  54. #define xr6 6
  55. #define xr7 7
  56. #define xr8 8
  57. #define xr9 9
  58. #define xr10 10
  59. #define xr11 11
  60. #define xr12 12
  61. #define xr13 13
  62. #define xr14 14
  63. #define xr15 15
  64. #define xr16 16
  65.  
  66. #endif /* WIN32 */
  67.  
  68. #ifdef WIN32
  69.  
  70. #define S32I2M(xr, r) if (&xr != mxu_xr) xr = r
  71. #define S32M2I(xr) xr
  72. #define S32LDD(xr, p, o) if (&xr != mxu_xr) xr = *(long*)((unsigned long)p + o)
  73. #define S32STD(xr, p, o) *(long*)((unsigned long)p + o) = xr
  74.  
  75. #define S32LDDV(xr, p, o, s) if (&xr != mxu_xr) xr = *(long*)((unsigned long)p + ((o) << s))
  76. #define S32STDV(xr, p, o, s) *(long*)((unsigned long)p + ((o) << s)) = xr
  77.  
  78. #define S32LDIV(xra, rb, rc, strd2) \
  79. {\
  80. if (&xra != mxu_xr) xra = *(long*)((unsigned long)rb + ((rc) << strd2));\
  81. rb = (char*)rb + ((rc) << strd2);\
  82. }
  83.  
  84. #define S32SDIV(xra, rb, rc, strd2) \
  85. {\
  86. *(long*)((unsigned long)rb + ((rc) << strd2)) = xra;\
  87. rb = (char*)rb + ((rc) << strd2);\
  88. }
  89.  
  90. #define S32LDI(xra, rb, o) \
  91. {\
  92. if (&xra != mxu_xr) xra = *(long*)((unsigned long)rb + o);\
  93. rb = (char*)rb + o;\
  94. }
  95.  
  96. #define S32SDI(xra, rb, o) \
  97. {\
  98. *(long*)((unsigned long)rb + o) = xra;\
  99. rb = (char*)rb + o;\
  100. }
  101.  
  102. #define S32LDIV(xra, rb, rc, strd2) \
  103. {\
  104. if (&xra != mxu_xr) xra = *(long*)((unsigned long)rb + ((rc) << strd2));\
  105. rb = (char*)rb + ((rc) << strd2);\
  106. }
  107.  
  108. #define S32SDIV(xra, rb, rc, strd2) \
  109. {\
  110. *(long*)((unsigned long)rb + ((rc) << strd2)) = xra;\
  111. rb = (char*)rb + ((rc) << strd2);\
  112. }
  113.  
  114. #define Q16ADD_AS_WW(a, b, c, d) \
  115. {\
  116. short bh = b >> 16;\
  117. short bl = b & 0xFFFF;\
  118. short ch = c >> 16;\
  119. short cl = c & 0xFFFF;\
  120. int ah = bh + ch;\
  121. int al = bl + cl;\
  122. int dh = bh - ch;\
  123. int dl = bl - cl;\
  124. if (&a != mxu_xr) a = (ah << 16) | (al & 0xFFFF);\
  125. if (&d != mxu_xr) d = (dh << 16) | (dl & 0xFFFF);\
  126. }
  127.  
  128. #define Q16ADD_AA_WW(a, b, c, d) \
  129. {\
  130. short bh = b >> 16;\
  131. short bl = b & 0xFFFF;\
  132. short ch = c >> 16;\
  133. short cl = c & 0xFFFF;\
  134. int ah = bh + ch;\
  135. int al = bl + cl;\
  136. if (&a != mxu_xr) a = (ah << 16) | (al & 0xFFFF);\
  137. if (&d != mxu_xr) d = (ah << 16) | (al & 0xFFFF);\
  138. }
  139.  
  140. #define D16MUL_LW(a, b, c, d)\
  141. {\
  142. short bl = b & 0xFFFF;\
  143. short cl = c & 0xFFFF;\
  144. short ch = c >> 16;\
  145. if (&a != mxu_xr) a = ch * bl;\
  146. if (&d != mxu_xr) d = cl * bl;\
  147. }
  148.  
  149. #define D16MUL_WW(a, b, c, d)\
  150. {\
  151. short bh = b >> 16;\
  152. short bl = b & 0xFFFF;\
  153. short ch = c >> 16;\
  154. short cl = c & 0xFFFF;\
  155. if (&a != mxu_xr) a = ch * bh;\
  156. if (&d != mxu_xr) d = cl * bl;\
  157. }
  158.  
  159. #define D16MAC_AA_LW(a, b, c, d)\
  160. {\
  161. short bl = b & 0xFFFF;\
  162. short cl = c & 0xFFFF;\
  163. short ch = c >> 16;\
  164. if (&a != mxu_xr) a += ch * bl;\
  165. if (&d != mxu_xr) d += cl * bl;\
  166. }
  167.  
  168. #define D16MUL_HW(a, b, c, d)\
  169. {\
  170. short bh = b >> 16;\
  171. short cl = c & 0xFFFF;\
  172. short ch = c >> 16;\
  173. if (&a != mxu_xr) a = ch * bh;\
  174. if (&d != mxu_xr) d = cl * bh;\
  175. }
  176.  
  177. #define D16MAC_AA_HW(a, b, c, d)\
  178. {\
  179. short bh = b >> 16;\
  180. short cl = c & 0xFFFF;\
  181. short ch = c >> 16;\
  182. if (&a != mxu_xr) a += ch * bh;\
  183. if (&d != mxu_xr) d += cl * bh;\
  184. }
  185.  
  186. #define D32SLL(a, b, c, d, sft)\
  187. {\
  188. if (&a != mxu_xr) a = b << sft;\
  189. if (&d != mxu_xr) d = c << sft;\
  190. }
  191.  
  192. #define D32SARL(a, b, c, sft) if (&a != mxu_xr) a = (((long)b >> sft) << 16) | (((long)c >> sft) & 0xFFFF)
  193.  
  194. #define S32SFL(a, b, c, d, ptn) \
  195. {\
  196. unsigned char b3 = (unsigned char)((unsigned long)b >> 24);\
  197. unsigned char b2 = (unsigned char)((unsigned long)b >> 16);\
  198. unsigned char b1 = (unsigned char)((unsigned long)b >> 8);\
  199. unsigned char b0 = (unsigned char)((unsigned long)b >> 0);\
  200. unsigned char c3 = (unsigned char)((unsigned long)c >> 24);\
  201. unsigned char c2 = (unsigned char)((unsigned long)c >> 16);\
  202. unsigned char c1 = (unsigned char)((unsigned long)c >> 8);\
  203. unsigned char c0 = (unsigned char)((unsigned long)c >> 0);\
  204. unsigned char a3, a2, a1, a0, d3, d2, d1, d0;\
  205. if (ptn0 == ptn) \
  206. {\
  207. a3 = b3;\
  208. a2 = c3;\
  209. a1 = b2;\
  210. a0 = c2;\
  211. d3 = b1;\
  212. d2 = c1;\
  213. d1 = b0;\
  214. d0 = c0;\
  215. }\
  216. else if (ptn1 == ptn)\
  217. {\
  218. a3 = b3;\
  219. a2 = b1;\
  220. a1 = c3;\
  221. a0 = c1;\
  222. d3 = b2;\
  223. d2 = b0;\
  224. d1 = c2;\
  225. d0 = c0;\
  226. }\
  227. else if (ptn2 == ptn)\
  228. {\
  229. a3 = b3;\
  230. a2 = c3;\
  231. a1 = b1;\
  232. a0 = c1;\
  233. d3 = b2;\
  234. d2 = c2;\
  235. d1 = b0;\
  236. d0 = c0;\
  237. }\
  238. else if (ptn3 == ptn)\
  239. {\
  240. a3 = b3;\
  241. a2 = b2;\
  242. a1 = c3;\
  243. a0 = c2;\
  244. d3 = b1;\
  245. d2 = b0;\
  246. d1 = c1;\
  247. d0 = c0;\
  248. }\
  249. if (&a != mxu_xr) a = ((unsigned long)a3 << 24) | ((unsigned long)a2 << 16) | ((unsigned long)a1 << 8) | (unsigned long)a0;\
  250. if (&d != mxu_xr) d = ((unsigned long)d3 << 24) | ((unsigned long)d2 << 16) | ((unsigned long)d1 << 8) | (unsigned long)d0;\
  251. }
  252.  
  253. #define D32SAR(a, b, c, d, sft)\
  254. {\
  255. if (&a != mxu_xr) a = (long)b >> sft;\
  256. if (&d != mxu_xr) d = (long)c >> sft;\
  257. }
  258.  
  259. #define D32SLR(a, b, c, d, sft)\
  260. {\
  261. if (&a != mxu_xr) a = (unsigned long)b >> sft;\
  262. if (&d != mxu_xr) d = (unsigned long)c >> sft;\
  263. }
  264.  
  265. #define D32ACC_AA(a, b, c, d)\
  266. {\
  267. int _b = b;\
  268. int _c = c;\
  269. int _a = a;\
  270. int _d = d;\
  271. if (&a != mxu_xr) a = _a + _b + _c;\
  272. if (&d != mxu_xr) d = _d + _b + _c;\
  273. }
  274.  
  275. #define D32ACC_AS(a, b, c, d)\
  276. {\
  277. int _b = b;\
  278. int _c = c;\
  279. int _a = a;\
  280. int _d = d;\
  281. if (&a != mxu_xr) a = _a + _b + _c;\
  282. if (&d != mxu_xr) d = _d + _b - _c;\
  283. }
  284.  
  285. #define D32ADD_AS(a, b, c, d)\
  286. {\
  287. int _b = b;\
  288. int _c = c;\
  289. if (&a != mxu_xr) a = _b + _c;\
  290. if (&d != mxu_xr) d = _b - _c;\
  291. }
  292.  
  293. #define D32ADD_SS(a, b, c, d)\
  294. {\
  295. int _b = b;\
  296. int _c = c;\
  297. if (&a != mxu_xr) a = _b - _c;\
  298. if (&d != mxu_xr) d = _b - _c;\
  299. }
  300.  
  301. #define D32ADD_AA(a, b, c, d)\
  302. {\
  303. int _b = b;\
  304. int _c = c;\
  305. if (&a != mxu_xr) a = _b + _c;\
  306. if (&d != mxu_xr) d = _b + _c;\
  307. }
  308.  
  309. #define Q8ADDE_AA(xra, xrb, xrc, xrd) \
  310. {\
  311. unsigned char b3 = (unsigned char)((unsigned long)xrb >> 24);\
  312. unsigned char b2 = (unsigned char)((unsigned long)xrb >> 16);\
  313. unsigned char b1 = (unsigned char)((unsigned long)xrb >> 8);\
  314. unsigned char b0 = (unsigned char)((unsigned long)xrb >> 0);\
  315. unsigned char c3 = (unsigned char)((unsigned long)xrc >> 24);\
  316. unsigned char c2 = (unsigned char)((unsigned long)xrc >> 16);\
  317. unsigned char c1 = (unsigned char)((unsigned long)xrc >> 8);\
  318. unsigned char c0 = (unsigned char)((unsigned long)xrc >> 0);\
  319. short ah, al, dh, dl;\
  320. ah = b3 + c3;\
  321. al = b2 + c2;\
  322. dh = b1 + c1;\
  323. dl = b0 + c0;\
  324. if (&xra != mxu_xr) xra = ((unsigned long)ah << 16) | (unsigned short)al;\
  325. if (&xrd != mxu_xr) xrd = ((unsigned long)dh << 16) | (unsigned short)dl;\
  326. }
  327.  
  328. #define Q16SAT(xra, xrb, xrc) \
  329. {\
  330. short bh = xrb >> 16;\
  331. short bl = xrb & 0xFFFF;\
  332. short ch = xrc >> 16;\
  333. short cl = xrc & 0xFFFF;\
  334. if (bh > 255) bh = 255;\
  335. if (bh < 0) bh = 0;\
  336. if (bl > 255) bl = 255;\
  337. if (bl < 0) bl = 0;\
  338. if (ch > 255) ch = 255;\
  339. if (ch < 0) ch = 0;\
  340. if (cl > 255) cl = 255;\
  341. if (cl < 0) cl = 0;\
  342. if (&xra != mxu_xr) xra = ((unsigned)bh << 24) | ((unsigned)bl << 16) | ((unsigned)ch << 8) | (unsigned)cl;\
  343. }
  344.  
  345. #define Q8SAD(xra, xrb, xrc, xrd) \
  346. {\
  347. short b3 = (unsigned char)((unsigned long)xrb >> 24);\
  348. short b2 = (unsigned char)((unsigned long)xrb >> 16);\
  349. short b1 = (unsigned char)((unsigned long)xrb >> 8);\
  350. short b0 = (unsigned char)((unsigned long)xrb >> 0);\
  351. short c3 = (unsigned char)((unsigned long)xrc >> 24);\
  352. short c2 = (unsigned char)((unsigned long)xrc >> 16);\
  353. short c1 = (unsigned char)((unsigned long)xrc >> 8);\
  354. short c0 = (unsigned char)((unsigned long)xrc >> 0);\
  355. int int0, int1, int2, int3;\
  356. int3 = labs(b3 - c3);\
  357. int2 = labs(b2 - c2);\
  358. int1 = labs(b1 - c1);\
  359. int0 = labs(b0 - c0);\
  360. if (&xra != mxu_xr) xra = int0 + int1 + int2 + int3;\
  361. if (&xrd != mxu_xr) xrd += int0 + int1 + int2 + int3;\
  362. }
  363.  
  364. #define Q8AVGR(xra, xrb, xrc) \
  365. {\
  366. short b3 = (unsigned char)((unsigned long)xrb >> 24);\
  367. short b2 = (unsigned char)((unsigned long)xrb >> 16);\
  368. short b1 = (unsigned char)((unsigned long)xrb >> 8);\
  369. short b0 = (unsigned char)((unsigned long)xrb >> 0);\
  370. short c3 = (unsigned char)((unsigned long)xrc >> 24);\
  371. short c2 = (unsigned char)((unsigned long)xrc >> 16);\
  372. short c1 = (unsigned char)((unsigned long)xrc >> 8);\
  373. short c0 = (unsigned char)((unsigned long)xrc >> 0);\
  374. unsigned char a3, a2, a1, a0;\
  375. a3 = (unsigned char)((b3 + c3 + 1) >> 1);\
  376. a2 = (unsigned char)((b2 + c2 + 1) >> 1);\
  377. a1 = (unsigned char)((b1 + c1 + 1) >> 1);\
  378. a0 = (unsigned char)((b0 + c0 + 1) >> 1);\
  379. if (&xra != mxu_xr) xra = ((unsigned long)a3 << 24) | ((unsigned long)a2 << 16) | ((unsigned long)a1 << 8) | (unsigned long)a0;\
  380. }
  381.  
  382. #define S32ALN(xra, xrb, xrc, rs) \
  383. {\
  384. if (0 == rs)\
  385. {\
  386. if (&xra != mxu_xr) xra = xrb;\
  387. }\
  388. else if (1 == rs)\
  389. {\
  390. if (&xra != mxu_xr) xra = (xrb << 8) | ((unsigned long)xrc >> 24);\
  391. }\
  392. else if (2 == rs)\
  393. {\
  394. if (&xra != mxu_xr) xra = (xrb << 16) | ((unsigned long)xrc >> 16);\
  395. }\
  396. else if (3 == rs)\
  397. {\
  398. if (&xra != mxu_xr) xra = (xrb << 24) | ((unsigned long)xrc >> 8);\
  399. }\
  400. else if (4 == rs)\
  401. {\
  402. if (&xra != mxu_xr) xra = xrc;\
  403. }\
  404. }
  405.  
  406. #else /* WIN32 */
  407.  
  408. /***********************************LD/SD***********************************/
  409. #define S32LDD(xra,rb,s12) \
  410. do { \
  411. __asm__ __volatile ("S32LDD xr%0,%z1,%2" \
  412. : \
  413. :"K"(xra),"d" (rb),"I"(s12)); \
  414. } while (0)
  415.  
  416. #define S32STD(xra,rb,s12) \
  417. do { \
  418. __asm__ __volatile ("S32STD xr%0,%z1,%2" \
  419. : \
  420. :"K"(xra),"d" (rb),"I"(s12):"memory"); \
  421. } while (0)
  422.  
  423. #define S32LDDV(xra,rb,rc,strd2) \
  424. do { \
  425. __asm__ __volatile ("S32LDDV xr%0,%z1,%z2,%3" \
  426. : \
  427. :"K"(xra),"d" (rb),"d"(rc),"K"(strd2)); \
  428. } while (0)
  429.  
  430. #define S32STDV(xra,rb,rc,strd2) \
  431. do { \
  432. __asm__ __volatile ("S32STDV xr%0,%z1,%z2,%3" \
  433. : \
  434. :"K"(xra),"d" (rb),"d"(rc),"K"(strd2):"memory"); \
  435. } while (0)
  436.  
  437. #define S32LDI(xra,rb,s12) \
  438. do { \
  439. __asm__ __volatile ("S32LDI xr%1,%z0,%2" \
  440. :"+d" (rb) \
  441. :"K"(xra),"I"(s12)); \
  442. } while (0)
  443.  
  444. #define S32SDI(xra,rb,s12) \
  445. do { \
  446. __asm__ __volatile ("S32SDI xr%1,%z0,%2" \
  447. :"+d" (rb) \
  448. :"K"(xra),"I"(s12):"memory"); \
  449. } while (0)
  450.  
  451. #define S32LDIV(xra,rb,rc,strd2) \
  452. do { \
  453. __asm__ __volatile ("S32LDIV xr%1,%z0,%z2,%3" \
  454. :"+d" (rb) \
  455. :"K"(xra),"d"(rc),"K"(strd2)); \
  456. } while (0)
  457.  
  458. #define S32SDIV(xra,rb,rc,strd2) \
  459. do { \
  460. __asm__ __volatile ("S32SDIV xr%1,%z0,%z2,%3" \
  461. :"+d" (rb) \
  462. :"K"(xra),"d"(rc),"K"(strd2):"memory"); \
  463. } while (0)
  464.  
  465. /***********************************D16MUL***********************************/
  466. #define D16MUL_WW(xra,xrb,xrc,xrd) \
  467. do { \
  468. __asm__ __volatile ("D16MUL xr%0,xr%1,xr%2,xr%3,WW" \
  469. : \
  470. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  471. } while (0)
  472.  
  473. #define D16MUL_LW(xra,xrb,xrc,xrd) \
  474. do { \
  475. __asm__ __volatile ("D16MUL xr%0,xr%1,xr%2,xr%3,LW" \
  476. : \
  477. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  478. } while (0)
  479.  
  480. #define D16MUL_HW(xra,xrb,xrc,xrd) \
  481. do { \
  482. __asm__ __volatile ("D16MUL xr%0,xr%1,xr%2,xr%3,HW" \
  483. : \
  484. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  485. } while (0)
  486.  
  487. #define D16MUL_XW(xra,xrb,xrc,xrd) \
  488. do { \
  489. __asm__ __volatile ("D16MUL xr%0,xr%1,xr%2,xr%3,XW" \
  490. : \
  491. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  492. } while (0)
  493.  
  494. /**********************************D16MULF*******************************/
  495. #define D16MULF_WW(xra,xrb,xrc) \
  496. do { \
  497. __asm__ __volatile ("D16MULF xr%0,xr%1,xr%2,WW" \
  498. : \
  499. :"K"(xra),"K"(xrb),"K"(xrc)); \
  500. } while (0)
  501.  
  502. #define D16MULF_LW(xra,xrb,xrc) \
  503. do { \
  504. __asm__ __volatile ("D16MULF xr%0,xr%1,xr%2,LW" \
  505. : \
  506. :"K"(xra),"K"(xrb),"K"(xrc)); \
  507. } while (0)
  508.  
  509. #define D16MULF_HW(xra,xrb,xrc) \
  510. do { \
  511. __asm__ __volatile ("D16MULF xr%0,xr%1,xr%2,HW" \
  512. : \
  513. :"K"(xra),"K"(xrb),"K"(xrc)); \
  514. } while (0)
  515.  
  516. #define D16MULF_XW(xra,xrb,xrc) \
  517. do { \
  518. __asm__ __volatile ("D16MULF xr%0,xr%1,xr%2,XW" \
  519. : \
  520. :"K"(xra),"K"(xrb),"K"(xrc)); \
  521. } while (0)
  522.  
  523. /***********************************D16MAC********************************/
  524. #define D16MAC_AA_WW(xra,xrb,xrc,xrd) \
  525. do { \
  526. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,AA,WW" \
  527. : \
  528. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  529. } while (0)
  530.  
  531. #define D16MAC_AA_LW(xra,xrb,xrc,xrd) \
  532. do { \
  533. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,AA,LW" \
  534. : \
  535. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  536. } while (0)
  537.  
  538. #define D16MAC_AA_HW(xra,xrb,xrc,xrd) \
  539. do { \
  540. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,AA,HW" \
  541. : \
  542. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  543. } while (0)
  544.  
  545. #define D16MAC_AA_XW(xra,xrb,xrc,xrd) \
  546. do { \
  547. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,AA,XW" \
  548. : \
  549. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  550. } while (0)
  551.  
  552. #define D16MAC_AS_WW(xra,xrb,xrc,xrd) \
  553. do { \
  554. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,AS,WW" \
  555. : \
  556. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  557. } while (0)
  558.  
  559. #define D16MAC_AS_LW(xra,xrb,xrc,xrd) \
  560. do { \
  561. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,AS,LW" \
  562. : \
  563. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  564. } while (0)
  565.  
  566. #define D16MAC_AS_HW(xra,xrb,xrc,xrd) \
  567. do { \
  568. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,AS,HW" \
  569. : \
  570. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  571. } while (0)
  572.  
  573. #define D16MAC_AS_XW(xra,xrb,xrc,xrd) \
  574. do { \
  575. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,AS,XW" \
  576. : \
  577. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  578. } while (0)
  579.  
  580. #define D16MAC_SA_WW(xra,xrb,xrc,xrd) \
  581. do { \
  582. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,SA,WW" \
  583. : \
  584. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  585. } while (0)
  586.  
  587. #define D16MAC_SA_LW(xra,xrb,xrc,xrd) \
  588. do { \
  589. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,SA,LW" \
  590. : \
  591. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  592. } while (0)
  593.  
  594. #define D16MAC_SA_HW(xra,xrb,xrc,xrd) \
  595. do { \
  596. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,SA,HW" \
  597. : \
  598. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  599. } while (0)
  600.  
  601. #define D16MAC_SA_XW(xra,xrb,xrc,xrd) \
  602. do { \
  603. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,SA,XW" \
  604. : \
  605. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  606. } while (0)
  607.  
  608. #define D16MAC_SS_WW(xra,xrb,xrc,xrd) \
  609. do { \
  610. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,SS,WW" \
  611. : \
  612. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  613. } while (0)
  614.  
  615. #define D16MAC_SS_LW(xra,xrb,xrc,xrd) \
  616. do { \
  617. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,SS,LW" \
  618. : \
  619. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  620. } while (0)
  621.  
  622. #define D16MAC_SS_HW(xra,xrb,xrc,xrd) \
  623. do { \
  624. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,SS,HW" \
  625. : \
  626. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  627. } while (0)
  628.  
  629. #define D16MAC_SS_XW(xra,xrb,xrc,xrd) \
  630. do { \
  631. __asm__ __volatile ("D16MAC xr%0,xr%1,xr%2,xr%3,SS,XW" \
  632. : \
  633. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  634. } while (0)
  635.  
  636. /**********************************D16MACF*******************************/
  637. #define D16MACF_AA_WW(xra,xrb,xrc,xrd) \
  638. do { \
  639. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,AA,WW" \
  640. : \
  641. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  642. } while (0)
  643.  
  644. #define D16MACF_AA_LW(xra,xrb,xrc,xrd) \
  645. do { \
  646. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,AA,LW" \
  647. : \
  648. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  649. } while (0)
  650.  
  651. #define D16MACF_AA_HW(xra,xrb,xrc,xrd) \
  652. do { \
  653. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,AA,HW" \
  654. : \
  655. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  656. } while (0)
  657.  
  658. #define D16MACF_AA_XW(xra,xrb,xrc,xrd) \
  659. do { \
  660. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,AA,XW" \
  661. : \
  662. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  663. } while (0)
  664.  
  665. #define D16MACF_AS_WW(xra,xrb,xrc,xrd) \
  666. do { \
  667. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,AS,WW" \
  668. : \
  669. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  670. } while (0)
  671.  
  672. #define D16MACF_AS_LW(xra,xrb,xrc,xrd) \
  673. do { \
  674. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,AS,LW" \
  675. : \
  676. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  677. } while (0)
  678.  
  679. #define D16MACF_AS_HW(xra,xrb,xrc,xrd) \
  680. do { \
  681. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,AS,HW" \
  682. : \
  683. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  684. } while (0)
  685.  
  686. #define D16MACF_AS_XW(xra,xrb,xrc,xrd) \
  687. do { \
  688. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,AS,XW" \
  689. : \
  690. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  691. } while (0)
  692.  
  693. #define D16MACF_SA_WW(xra,xrb,xrc,xrd) \
  694. do { \
  695. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,SA,WW" \
  696. : \
  697. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  698. } while (0)
  699.  
  700. #define D16MACF_SA_LW(xra,xrb,xrc,xrd) \
  701. do { \
  702. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,SA,LW" \
  703. : \
  704. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  705. } while (0)
  706.  
  707. #define D16MACF_SA_HW(xra,xrb,xrc,xrd) \
  708. do { \
  709. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,SA,HW" \
  710. : \
  711. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  712. } while (0)
  713.  
  714. #define D16MACF_SA_XW(xra,xrb,xrc,xrd) \
  715. do { \
  716. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,SA,XW" \
  717. : \
  718. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  719. } while (0)
  720.  
  721. #define D16MACF_SS_WW(xra,xrb,xrc,xrd) \
  722. do { \
  723. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,SS,WW" \
  724. : \
  725. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  726. } while (0)
  727.  
  728. #define D16MACF_SS_LW(xra,xrb,xrc,xrd) \
  729. do { \
  730. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,SS,LW" \
  731. : \
  732. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  733. } while (0)
  734.  
  735. #define D16MACF_SS_HW(xra,xrb,xrc,xrd) \
  736. do { \
  737. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,SS,HW" \
  738. : \
  739. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  740. } while (0)
  741.  
  742. #define D16MACF_SS_XW(xra,xrb,xrc,xrd) \
  743. do { \
  744. __asm__ __volatile ("D16MACF xr%0,xr%1,xr%2,xr%3,SS,XW" \
  745. : \
  746. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  747. } while (0)
  748.  
  749. /**********************************D16MADL*******************************/
  750. #define D16MADL_AA_WW(xra,xrb,xrc,xrd) \
  751. do { \
  752. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,AA,WW" \
  753. : \
  754. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  755. } while (0)
  756.  
  757. #define D16MADL_AA_LW(xra,xrb,xrc,xrd) \
  758. do { \
  759. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,AA,LW" \
  760. : \
  761. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  762. } while (0)
  763.  
  764. #define D16MADL_AA_HW(xra,xrb,xrc,xrd) \
  765. do { \
  766. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,AA,HW" \
  767. : \
  768. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  769. } while (0)
  770.  
  771. #define D16MADL_AA_XW(xra,xrb,xrc,xrd) \
  772. do { \
  773. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,AA,XW" \
  774. : \
  775. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  776. } while (0)
  777.  
  778. #define D16MADL_AS_WW(xra,xrb,xrc,xrd) \
  779. do { \
  780. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,AS,WW" \
  781. : \
  782. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  783. } while (0)
  784.  
  785. #define D16MADL_AS_LW(xra,xrb,xrc,xrd) \
  786. do { \
  787. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,AS,LW" \
  788. : \
  789. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  790. } while (0)
  791.  
  792. #define D16MADL_AS_HW(xra,xrb,xrc,xrd) \
  793. do { \
  794. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,AS,HW" \
  795. : \
  796. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  797. } while (0)
  798.  
  799. #define D16MADL_AS_XW(xra,xrb,xrc,xrd) \
  800. do { \
  801. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,AS,XW" \
  802. : \
  803. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  804. } while (0)
  805.  
  806. #define D16MADL_SA_WW(xra,xrb,xrc,xrd) \
  807. do { \
  808. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,SA,WW" \
  809. : \
  810. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  811. } while (0)
  812.  
  813. #define D16MADL_SA_LW(xra,xrb,xrc,xrd) \
  814. do { \
  815. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,SA,LW" \
  816. : \
  817. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  818. } while (0)
  819.  
  820. #define D16MADL_SA_HW(xra,xrb,xrc,xrd) \
  821. do { \
  822. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,SA,HW" \
  823. : \
  824. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  825. } while (0)
  826.  
  827. #define D16MADL_SA_XW(xra,xrb,xrc,xrd) \
  828. do { \
  829. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,SA,XW" \
  830. : \
  831. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  832. } while (0)
  833.  
  834. #define D16MADL_SS_WW(xra,xrb,xrc,xrd) \
  835. do { \
  836. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,SS,WW" \
  837. : \
  838. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  839. } while (0)
  840.  
  841. #define D16MADL_SS_LW(xra,xrb,xrc,xrd) \
  842. do { \
  843. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,SS,LW" \
  844. : \
  845. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  846. } while (0)
  847.  
  848. #define D16MADL_SS_HW(xra,xrb,xrc,xrd) \
  849. do { \
  850. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,SS,HW" \
  851. : \
  852. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  853. } while (0)
  854.  
  855. #define D16MADL_SS_XW(xra,xrb,xrc,xrd) \
  856. do { \
  857. __asm__ __volatile ("D16MADL xr%0,xr%1,xr%2,xr%3,SS,XW" \
  858. : \
  859. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  860. } while (0)
  861.  
  862. /***********************************S16MAD*******************************/
  863. #define S16MAD_A_HH(xra,xrb,xrc,xrd) \
  864. do { \
  865. __asm__ __volatile ("S16MAD xr%0,xr%1,xr%2,xr%3,A,0" \
  866. : \
  867. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  868. } while (0)
  869.  
  870. #define S16MAD_A_LL(xra,xrb,xrc,xrd) \
  871. do { \
  872. __asm__ __volatile ("S16MAD xr%0,xr%1,xr%2,xr%3,A,1" \
  873. : \
  874. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  875. } while (0)
  876.  
  877. #define S16MAD_A_HL(xra,xrb,xrc,xrd) \
  878. do { \
  879. __asm__ __volatile ("S16MAD xr%0,xr%1,xr%2,xr%3,A,2" \
  880. : \
  881. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  882. } while (0)
  883.  
  884. #define S16MAD_A_LH(xra,xrb,xrc,xrd) \
  885. do { \
  886. __asm__ __volatile ("S16MAD xr%0,xr%1,xr%2,xr%3,A,3" \
  887. : \
  888. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  889. } while (0)
  890.  
  891. #define S16MAD_S_HH(xra,xrb,xrc,xrd) \
  892. do { \
  893. __asm__ __volatile ("S16MAD xr%0,xr%1,xr%2,xr%3,S,0" \
  894. : \
  895. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  896. } while (0)
  897.  
  898. #define S16MAD_S_LL(xra,xrb,xrc,xrd) \
  899. do { \
  900. __asm__ __volatile ("S16MAD xr%0,xr%1,xr%2,xr%3,S,1" \
  901. : \
  902. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  903. } while (0)
  904.  
  905. #define S16MAD_S_HL(xra,xrb,xrc,xrd) \
  906. do { \
  907. __asm__ __volatile ("S16MAD xr%0,xr%1,xr%2,xr%3,S,2" \
  908. : \
  909. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  910. } while (0)
  911.  
  912. #define S16MAD_S_LH(xra,xrb,xrc,xrd) \
  913. do { \
  914. __asm__ __volatile ("S16MAD xr%0,xr%1,xr%2,xr%3,S,3" \
  915. : \
  916. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  917. } while (0)
  918.  
  919. /***********************************Q8MUL********************************/
  920. #define Q8MUL(xra,xrb,xrc,xrd) \
  921. do { \
  922. __asm__ __volatile ("Q8MUL xr%0,xr%1,xr%2,xr%3" \
  923. : \
  924. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  925. } while (0)
  926.  
  927. /***********************************Q8MAC********************************/
  928. #define Q8MAC_AA(xra,xrb,xrc,xrd) \
  929. do { \
  930. __asm__ __volatile ("Q8MAC xr%0,xr%1,xr%2,xr%3,AA" \
  931. : \
  932. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  933. } while (0)
  934.  
  935. #define Q8MAC_AS(xra,xrb,xrc,xrd) \
  936. do { \
  937. __asm__ __volatile ("Q8MAC xr%0,xr%1,xr%2,xr%3,AS" \
  938. : \
  939. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  940. } while (0)
  941.  
  942. #define Q8MAC_SA(xra,xrb,xrc,xrd) \
  943. do { \
  944. __asm__ __volatile ("Q8MAC xr%0,xr%1,xr%2,xr%3,SA" \
  945. : \
  946. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  947. } while (0)
  948.  
  949. #define Q8MAC_SS(xra,xrb,xrc,xrd) \
  950. do { \
  951. __asm__ __volatile ("Q8MAC xr%0,xr%1,xr%2,xr%3,SS" \
  952. : \
  953. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  954. } while (0)
  955.  
  956. /***********************************Q8MADL********************************/
  957. #define Q8MADL_AA(xra,xrb,xrc,xrd) \
  958. do { \
  959. __asm__ __volatile ("Q8MADL xr%0,xr%1,xr%2,xr%3,AA" \
  960. : \
  961. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  962. } while (0)
  963.  
  964. #define Q8MADL_AS(xra,xrb,xrc,xrd) \
  965. do { \
  966. __asm__ __volatile ("Q8MADL xr%0,xr%1,xr%2,xr%3,AS" \
  967. : \
  968. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  969. } while (0)
  970.  
  971. #define Q8MADL_SA(xra,xrb,xrc,xrd) \
  972. do { \
  973. __asm__ __volatile ("Q8MADL xr%0,xr%1,xr%2,xr%3,SA" \
  974. : \
  975. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  976. } while (0)
  977.  
  978. #define Q8MADL_SS(xra,xrb,xrc,xrd) \
  979. do { \
  980. __asm__ __volatile ("Q8MADL xr%0,xr%1,xr%2,xr%3,SS" \
  981. : \
  982. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  983. } while (0)
  984.  
  985. /***********************************D32ADD********************************/
  986. #define D32ADD_AA(xra,xrb,xrc,xrd) \
  987. do { \
  988. __asm__ __volatile ("D32ADD xr%0,xr%1,xr%2,xr%3,AA" \
  989. : \
  990. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  991. } while (0)
  992.  
  993. #define D32ADD_AS(xra,xrb,xrc,xrd) \
  994. do { \
  995. __asm__ __volatile ("D32ADD xr%0,xr%1,xr%2,xr%3,AS" \
  996. : \
  997. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  998. } while (0)
  999.  
  1000. #define D32ADD_SA(xra,xrb,xrc,xrd) \
  1001. do { \
  1002. __asm__ __volatile ("D32ADD xr%0,xr%1,xr%2,xr%3,SA" \
  1003. : \
  1004. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1005. } while (0)
  1006.  
  1007. #define D32ADD_SS(xra,xrb,xrc,xrd) \
  1008. do { \
  1009. __asm__ __volatile ("D32ADD xr%0,xr%1,xr%2,xr%3,SS" \
  1010. : \
  1011. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1012. } while (0)
  1013.  
  1014. /***********************************D32ACC********************************/
  1015. #define D32ACC_AA(xra,xrb,xrc,xrd) \
  1016. do { \
  1017. __asm__ __volatile ("D32ACC xr%0,xr%1,xr%2,xr%3,AA" \
  1018. : \
  1019. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1020. } while (0)
  1021.  
  1022. #define D32ACC_AS(xra,xrb,xrc,xrd) \
  1023. do { \
  1024. __asm__ __volatile ("D32ACC xr%0,xr%1,xr%2,xr%3,AS" \
  1025. : \
  1026. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1027. } while (0)
  1028.  
  1029. #define D32ACC_SA(xra,xrb,xrc,xrd) \
  1030. do { \
  1031. __asm__ __volatile ("D32ACC xr%0,xr%1,xr%2,xr%3,SA" \
  1032. : \
  1033. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1034. } while (0)
  1035.  
  1036. #define D32ACC_SS(xra,xrb,xrc,xrd) \
  1037. do { \
  1038. __asm__ __volatile ("D32ACC xr%0,xr%1,xr%2,xr%3,SS" \
  1039. : \
  1040. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1041. } while (0)
  1042.  
  1043. /***********************************S32CPS********************************/
  1044. #define S32CPS(xra,xrb,xrc) \
  1045. do { \
  1046. __asm__ __volatile ("S32CPS xr%0,xr%1,xr%2" \
  1047. : \
  1048. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1049. } while (0)
  1050.  
  1051. #define S32ABS(xra,xrb) \
  1052. do { \
  1053. __asm__ __volatile ("S32CPS xr%0,xr%1,xr%2" \
  1054. : \
  1055. :"K"(xra),"K"(xrb),"K"(xrb)); \
  1056. } while (0)
  1057.  
  1058. /***********************************Q16ADD********************************/
  1059. #define Q16ADD_AA_WW(xra,xrb,xrc,xrd) \
  1060. do { \
  1061. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,AA,WW" \
  1062. : \
  1063. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1064. } while (0)
  1065.  
  1066. #define Q16ADD_AA_LW(xra,xrb,xrc,xrd) \
  1067. do { \
  1068. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,AA,LW" \
  1069. : \
  1070. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1071. } while (0)
  1072.  
  1073. #define Q16ADD_AA_HW(xra,xrb,xrc,xrd) \
  1074. do { \
  1075. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,AA,HW" \
  1076. : \
  1077. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1078. } while (0)
  1079.  
  1080. #define Q16ADD_AA_XW(xra,xrb,xrc,xrd) \
  1081. do { \
  1082. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,AA,XW" \
  1083. : \
  1084. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1085. } while (0)
  1086. #define Q16ADD_AS_WW(xra,xrb,xrc,xrd) \
  1087. do { \
  1088. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,AS,WW" \
  1089. : \
  1090. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1091. } while (0)
  1092.  
  1093. #define Q16ADD_AS_LW(xra,xrb,xrc,xrd) \
  1094. do { \
  1095. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,AS,LW" \
  1096. : \
  1097. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1098. } while (0)
  1099.  
  1100. #define Q16ADD_AS_HW(xra,xrb,xrc,xrd) \
  1101. do { \
  1102. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,AS,HW" \
  1103. : \
  1104. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1105. } while (0)
  1106.  
  1107. #define Q16ADD_AS_XW(xra,xrb,xrc,xrd) \
  1108. do { \
  1109. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,AS,XW" \
  1110. : \
  1111. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1112. } while (0)
  1113.  
  1114. #define Q16ADD_SA_WW(xra,xrb,xrc,xrd) \
  1115. do { \
  1116. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,SA,WW" \
  1117. : \
  1118. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1119. } while (0)
  1120.  
  1121. #define Q16ADD_SA_LW(xra,xrb,xrc,xrd) \
  1122. do { \
  1123. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,SA,LW" \
  1124. : \
  1125. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1126. } while (0)
  1127.  
  1128. #define Q16ADD_SA_HW(xra,xrb,xrc,xrd) \
  1129. do { \
  1130. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,SA,HW" \
  1131. : \
  1132. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1133. } while (0)
  1134.  
  1135. #define Q16ADD_SA_XW(xra,xrb,xrc,xrd) \
  1136. do { \
  1137. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,SA,XW" \
  1138. : \
  1139. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1140. } while (0)
  1141.  
  1142. #define Q16ADD_SS_WW(xra,xrb,xrc,xrd) \
  1143. do { \
  1144. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,SS,WW" \
  1145. : \
  1146. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1147. } while (0)
  1148.  
  1149. #define Q16ADD_SS_LW(xra,xrb,xrc,xrd) \
  1150. do { \
  1151. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,SS,LW" \
  1152. : \
  1153. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1154. } while (0)
  1155.  
  1156. #define Q16ADD_SS_HW(xra,xrb,xrc,xrd) \
  1157. do { \
  1158. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,SS,HW" \
  1159. : \
  1160. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1161. } while (0)
  1162.  
  1163. #define Q16ADD_SS_XW(xra,xrb,xrc,xrd) \
  1164. do { \
  1165. __asm__ __volatile ("Q16ADD xr%0,xr%1,xr%2,xr%3,SS,XW" \
  1166. : \
  1167. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1168. } while (0)
  1169.  
  1170. /***********************************Q16ACC********************************/
  1171. #define Q16ACC_AA(xra,xrb,xrc,xrd) \
  1172. do { \
  1173. __asm__ __volatile ("Q16ACC xr%0,xr%1,xr%2,xr%3,AA" \
  1174. : \
  1175. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1176. } while (0)
  1177.  
  1178. #define Q16ACC_AS(xra,xrb,xrc,xrd) \
  1179. do { \
  1180. __asm__ __volatile ("Q16ACC xr%0,xr%1,xr%2,xr%3,AS" \
  1181. : \
  1182. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1183. } while (0)
  1184.  
  1185. #define Q16ACC_SA(xra,xrb,xrc,xrd) \
  1186. do { \
  1187. __asm__ __volatile ("Q16ACC xr%0,xr%1,xr%2,xr%3,SA" \
  1188. : \
  1189. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1190. } while (0)
  1191.  
  1192. #define Q16ACC_SS(xra,xrb,xrc,xrd) \
  1193. do { \
  1194. __asm__ __volatile ("Q16ACC xr%0,xr%1,xr%2,xr%3,SS" \
  1195. : \
  1196. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1197. } while (0)
  1198.  
  1199. /***********************************D16CPS********************************/
  1200. #define D16CPS(xra,xrb,xrc) \
  1201. do { \
  1202. __asm__ __volatile ("D16CPS xr%0,xr%1,xr%2" \
  1203. : \
  1204. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1205. } while (0)
  1206.  
  1207. #define D16ABS(xra,xrb) \
  1208. do { \
  1209. __asm__ __volatile ("D16CPS xr%0,xr%1,xr%2" \
  1210. : \
  1211. :"K"(xra),"K"(xrb),"K"(xrb)); \
  1212. } while (0)
  1213.  
  1214. /*******************************D16AVG/D16AVGR*****************************/
  1215. #define D16AVG(xra,xrb,xrc) \
  1216. do { \
  1217. __asm__ __volatile ("D16AVG xr%0,xr%1,xr%2" \
  1218. : \
  1219. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1220. } while (0)
  1221. #define D16AVGR(xra,xrb,xrc) \
  1222. do { \
  1223. __asm__ __volatile ("D16AVGR xr%0,xr%1,xr%2" \
  1224. : \
  1225. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1226. } while (0)
  1227.  
  1228. /************************************Q8ADD********************************/
  1229. #define Q8ADD_AA(xra,xrb,xrc) \
  1230. do { \
  1231. __asm__ __volatile ("Q8ADD xr%0,xr%1,xr%2,AA" \
  1232. : \
  1233. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1234. } while (0)
  1235.  
  1236. #define Q8ADD_AS(xra,xrb,xrc) \
  1237. do { \
  1238. __asm__ __volatile ("Q8ADD xr%0,xr%1,xr%2,AS" \
  1239. : \
  1240. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1241. } while (0)
  1242.  
  1243. #define Q8ADD_SA(xra,xrb,xrc) \
  1244. do { \
  1245. __asm__ __volatile ("Q8ADD xr%0,xr%1,xr%2,SA" \
  1246. : \
  1247. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1248. } while (0)
  1249.  
  1250. #define Q8ADD_SS(xra,xrb,xrc) \
  1251. do { \
  1252. __asm__ __volatile ("Q8ADD xr%0,xr%1,xr%2,SS" \
  1253. : \
  1254. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1255. } while (0)
  1256.  
  1257. /************************************Q8ADDE********************************/
  1258. #define Q8ADDE_AA(xra,xrb,xrc,xrd) \
  1259. do { \
  1260. __asm__ __volatile ("Q8ADDE xr%0,xr%1,xr%2,xr%3,AA" \
  1261. : \
  1262. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1263. } while (0)
  1264.  
  1265. #define Q8ADDE_AS(xra,xrb,xrc,xrd) \
  1266. do { \
  1267. __asm__ __volatile ("Q8ADDE xr%0,xr%1,xr%2,xr%3,AS" \
  1268. : \
  1269. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1270. } while (0)
  1271.  
  1272. #define Q8ADDE_SA(xra,xrb,xrc,xrd) \
  1273. do { \
  1274. __asm__ __volatile ("Q8ADDE xr%0,xr%1,xr%2,xr%3,SA" \
  1275. : \
  1276. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1277. } while (0)
  1278.  
  1279. #define Q8ADDE_SS(xra,xrb,xrc,xrd) \
  1280. do { \
  1281. __asm__ __volatile ("Q8ADDE xr%0,xr%1,xr%2,xr%3,SS" \
  1282. : \
  1283. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1284. } while (0)
  1285.  
  1286. /************************************Q8ACCE********************************/
  1287. #define Q8ACCE_AA(xra,xrb,xrc,xrd) \
  1288. do { \
  1289. __asm__ __volatile ("Q8ACCE xr%0,xr%1,xr%2,xr%3,AA" \
  1290. : \
  1291. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1292. } while (0)
  1293.  
  1294. #define Q8ACCE_AS(xra,xrb,xrc,xrd) \
  1295. do { \
  1296. __asm__ __volatile ("Q8ACCE xr%0,xr%1,xr%2,xr%3,AS" \
  1297. : \
  1298. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1299. } while (0)
  1300.  
  1301. #define Q8ACCE_SA(xra,xrb,xrc,xrd) \
  1302. do { \
  1303. __asm__ __volatile ("Q8ACCE xr%0,xr%1,xr%2,xr%3,SA" \
  1304. : \
  1305. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1306. } while (0)
  1307.  
  1308. #define Q8ACCE_SS(xra,xrb,xrc,xrd) \
  1309. do { \
  1310. __asm__ __volatile ("Q8ACCE xr%0,xr%1,xr%2,xr%3,SS" \
  1311. : \
  1312. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1313. } while (0)
  1314.  
  1315. /************************************Q8ABD********************************/
  1316. #define Q8ABD(xra,xrb,xrc) \
  1317. do { \
  1318. __asm__ __volatile ("Q8ABD xr%0,xr%1,xr%2" \
  1319. : \
  1320. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1321. } while (0)
  1322.  
  1323. /************************************Q8SLT********************************/
  1324. #define Q8SLT(xra,xrb,xrc) \
  1325. do { \
  1326. __asm__ __volatile ("Q8SLT xr%0,xr%1,xr%2" \
  1327. : \
  1328. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1329. } while (0)
  1330.  
  1331. /************************************Q8SAD********************************/
  1332. #define Q8SAD(xra,xrb,xrc,xrd) \
  1333. do { \
  1334. __asm__ __volatile ("Q8SAD xr%0,xr%1,xr%2,xr%3" \
  1335. : \
  1336. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd)); \
  1337. } while (0)
  1338.  
  1339. /********************************Q8AVG/Q8AVGR*****************************/
  1340. #define Q8AVG(xra,xrb,xrc) \
  1341. do { \
  1342. __asm__ __volatile ("Q8AVG xr%0,xr%1,xr%2" \
  1343. : \
  1344. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1345. } while (0)
  1346. #define Q8AVGR(xra,xrb,xrc) \
  1347. do { \
  1348. __asm__ __volatile ("Q8AVGR xr%0,xr%1,xr%2" \
  1349. : \
  1350. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1351. } while (0)
  1352.  
  1353. /**********************************D32SHIFT******************************/
  1354. #define D32SLL(xra,xrb,xrc,xrd,SFT4) \
  1355. do { \
  1356. __asm__ __volatile ("D32SLL xr%0,xr%1,xr%2,xr%3,%4" \
  1357. : \
  1358. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
  1359. } while (0)
  1360.  
  1361. #define D32SLR(xra,xrb,xrc,xrd,SFT4) \
  1362. do { \
  1363. __asm__ __volatile ("D32SLR xr%0,xr%1,xr%2,xr%3,%4" \
  1364. : \
  1365. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
  1366. } while (0)
  1367.  
  1368. #define D32SAR(xra,xrb,xrc,xrd,SFT4) \
  1369. do { \
  1370. __asm__ __volatile ("D32SAR xr%0,xr%1,xr%2,xr%3,%4" \
  1371. : \
  1372. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
  1373. } while (0)
  1374.  
  1375. #define D32SARL(xra,xrb,xrc,SFT4) \
  1376. do { \
  1377. __asm__ __volatile ("D32SARL xr%0,xr%1,xr%2,%3" \
  1378. : \
  1379. :"K"(xra),"K"(xrb),"K"(xrc),"K"(SFT4)); \
  1380. } while (0)
  1381.  
  1382. #define D32SLLV(xra,xrd,rb) \
  1383. do { \
  1384. __asm__ __volatile ("D32SLLV xr%0,xr%1,%z2" \
  1385. : \
  1386. :"K"(xra),"K"(xrd),"d"(rb)); \
  1387. } while (0)
  1388.  
  1389. #define D32SLRV(xra,xrd,rb) \
  1390. do { \
  1391. __asm__ __volatile ("D32SLRV xr%0,xr%1,%z2" \
  1392. : \
  1393. :"K"(xra),"K"(xrd),"d"(rb)); \
  1394. } while (0)
  1395.  
  1396. #define D32SARV(xra,xrd,rb) \
  1397. do { \
  1398. __asm__ __volatile ("D32SARV xr%0,xr%1,%z2" \
  1399. : \
  1400. :"K"(xra),"K"(xrd),"d"(rb)); \
  1401. } while (0)
  1402.  
  1403. #define D32SARW(xra,xrb,xrc,rb) \
  1404. do { \
  1405. __asm__ __volatile ("D32SARW xr%0,xr%1,xr%2,%3" \
  1406. : \
  1407. :"K"(xra),"K"(xrb),"K"(xrc),"d"(rb)); \
  1408. } while (0)
  1409.  
  1410. /**********************************Q16SHIFT******************************/
  1411. #define Q16SLL(xra,xrb,xrc,xrd,SFT4) \
  1412. do { \
  1413. __asm__ __volatile ("Q16SLL xr%0,xr%1,xr%2,xr%3,%4" \
  1414. : \
  1415. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
  1416. } while (0)
  1417.  
  1418. #define Q16SLR(xra,xrb,xrc,xrd,SFT4) \
  1419. do { \
  1420. __asm__ __volatile ("Q16SLR xr%0,xr%1,xr%2,xr%3,%4" \
  1421. : \
  1422. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
  1423. } while (0)
  1424.  
  1425. #define Q16SAR(xra,xrb,xrc,xrd,SFT4) \
  1426. do { \
  1427. __asm__ __volatile ("Q16SAR xr%0,xr%1,xr%2,xr%3,%4" \
  1428. : \
  1429. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(SFT4)); \
  1430. } while (0)
  1431.  
  1432. #define Q16SLLV(xra,xrd,rb) \
  1433. do { \
  1434. __asm__ __volatile ("Q16SLLV xr%0,xr%1,%z2" \
  1435. : \
  1436. :"K"(xra),"K"(xrd),"d"(rb)); \
  1437. } while (0)
  1438.  
  1439. #define Q16SLRV(xra,xrd,rb) \
  1440. do { \
  1441. __asm__ __volatile ("Q16SLRV xr%0,xr%1,%z2" \
  1442. : \
  1443. :"K"(xra),"K"(xrd),"d"(rb)); \
  1444. } while (0)
  1445.  
  1446. #define Q16SARV(xra,xrd,rb) \
  1447. do { \
  1448. __asm__ __volatile ("Q16SARV xr%0,xr%1,%z2" \
  1449. : \
  1450. :"K"(xra),"K"(xrd),"d"(rb)); \
  1451. } while (0)
  1452.  
  1453. /*********************************MAX/MIN*********************************/
  1454. #define S32MAX(xra,xrb,xrc) \
  1455. do { \
  1456. __asm__ __volatile ("S32MAX xr%0,xr%1,xr%2" \
  1457. : \
  1458. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1459. } while (0)
  1460.  
  1461. #define S32MIN(xra,xrb,xrc) \
  1462. do { \
  1463. __asm__ __volatile ("S32MIN xr%0,xr%1,xr%2" \
  1464. : \
  1465. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1466. } while (0)
  1467.  
  1468. #define D16MAX(xra,xrb,xrc) \
  1469. do { \
  1470. __asm__ __volatile ("D16MAX xr%0,xr%1,xr%2" \
  1471. : \
  1472. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1473. } while (0)
  1474.  
  1475. #define D16MIN(xra,xrb,xrc) \
  1476. do { \
  1477. __asm__ __volatile ("D16MIN xr%0,xr%1,xr%2" \
  1478. : \
  1479. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1480. } while (0)
  1481.  
  1482. #define Q8MAX(xra,xrb,xrc) \
  1483. do { \
  1484. __asm__ __volatile ("Q8MAX xr%0,xr%1,xr%2" \
  1485. : \
  1486. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1487. } while (0)
  1488.  
  1489. #define Q8MIN(xra,xrb,xrc) \
  1490. do { \
  1491. __asm__ __volatile ("Q8MIN xr%0,xr%1,xr%2" \
  1492. : \
  1493. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1494. } while (0)
  1495.  
  1496. /*************************************MOVE********************************/
  1497. #define S32I2M(xra,rb) \
  1498. do { \
  1499. __asm__ __volatile ("S32I2M xr%0,%z1" \
  1500. : \
  1501. :"K"(xra),"d"(rb)); \
  1502. } while (0)
  1503.  
  1504. #define S32M2I(xra) \
  1505. __extension__ ({ \
  1506. int __d; \
  1507. __asm__ __volatile ("S32M2I xr%1, %0" \
  1508. :"=d"(__d) \
  1509. :"K"(xra)); \
  1510. __d; \
  1511. })
  1512.  
  1513. /*********************************S32SFL**********************************/
  1514. #define S32SFL(xra,xrb,xrc,xrd,optn2) \
  1515. do { \
  1516. __asm__ __volatile ("S32SFL xr%0,xr%1,xr%2,xr%3,ptn%4" \
  1517. : \
  1518. :"K"(xra),"K"(xrb),"K"(xrc),"K"(xrd),"K"(optn2)); \
  1519. } while (0)
  1520.  
  1521. /*********************************S32ALN**********************************/
  1522. #define S32ALN(xra,xrb,xrc,rs) \
  1523. do { \
  1524. __asm__ __volatile ("S32ALN xr%0,xr%1,xr%2,%z3" \
  1525. : \
  1526. :"K"(xra),"K"(xrb),"K"(xrc),"d"(rs)); \
  1527. } while (0)
  1528.  
  1529. /*********************************Q16SAT**********************************/
  1530. #define Q16SAT(xra,xrb,xrc) \
  1531. do { \
  1532. __asm__ __volatile ("Q16SAT xr%0,xr%1,xr%2" \
  1533. : \
  1534. :"K"(xra),"K"(xrb),"K"(xrc)); \
  1535. } while (0)
  1536.  
  1537. // cache ops
  1538.  
  1539. // cache
  1540. #define Index_Invalidate_I 0x00
  1541. #define Index_Writeback_Inv_D 0x01
  1542. #define Index_Load_Tag_I 0x04
  1543. #define Index_Load_Tag_D 0x05
  1544. #define Index_Store_Tag_I 0x08
  1545. #define Index_Store_Tag_D 0x09
  1546. #define Hit_Invalidate_I 0x10
  1547. #define Hit_Invalidate_D 0x11
  1548. #define Hit_Writeback_Inv_D 0x15
  1549. #define Hit_Writeback_I 0x18
  1550. #define Hit_Writeback_D 0x19
  1551.  
  1552. // pref
  1553. #define PrefLoad 0
  1554. #define PrefStore 1
  1555. #define PrefLoadStreamed 4
  1556. #define PrefStoreStreamed 5
  1557. #define PrefLoadRetained 6
  1558. #define PrefStoreRetained 7
  1559. #define PrefWBInval 25
  1560. #define PrefNudge 25
  1561. #define PrefPreForStore 30
  1562.  
  1563. #define mips_pref(base, offset, op) \
  1564. __asm__ __volatile__( \
  1565. " .set noreorder \n" \
  1566. " pref %1, %2(%0) \n" \
  1567. " .set reorder" \
  1568. : \
  1569. : "r" (base), "i" (op), "i" (offset))
  1570.  
  1571. #define cache_op(op, addr) \
  1572. __asm__ __volatile__( \
  1573. " .set noreorder \n" \
  1574. " cache %0, %1 \n" \
  1575. " .set reorder" \
  1576. : \
  1577. : "i" (op), "m" (*(unsigned char *)(addr)))
  1578. #define i_pref(hint,base,offset) \
  1579. ({ __asm__ __volatile__("pref %0,%2(%1)"::"i"(hint),"r"(base),"i"(offset):"memory");})
  1580. struct unaligned_32 { unsigned int l; } __attribute__((packed));
  1581. #define LD32(a) (((const struct unaligned_32 *) (a))->l)
  1582. #define ST32(a, b) (((struct unaligned_32 *) (a))->l) = (b)
  1583.  
  1584. #define REVERSE_LD32(xra, xrb, rb, s12) \
  1585. __extension__ ({ \
  1586. int __d; \
  1587. __asm__ __volatile ("S32LDD xr%1,%z3,%4\n\t" \
  1588. "S32SFL xr%1,xr%1, xr%1, xr%2, ptn0\n\t" \
  1589. "S32SFL xr%1,xr%2, xr%1, xr%2, ptn3\n\t" \
  1590. "S32SFL xr%1,xr%2, xr%1, xr%2, ptn2\n\t" \
  1591. "S32M2I xr%1,%0" \
  1592. :"=d"(__d) \
  1593. :"K"(xra), "K"(xrb), "d"(rb), "I"(s12)); \
  1594. __d; \
  1595. })
  1596.  
  1597. #define IU_CLZ(rb) \
  1598. __extension__ ({ \
  1599. int __d; \
  1600. __asm__ __volatile ("clz %0, %1" \
  1601. :"=d"(__d) \
  1602. :"d"(rb)); \
  1603. __d; \
  1604. })
  1605.  
  1606. #endif /* WIN32 */
  1607.  
  1608. #endif /* _JZ_MXU_H_ */
  1609.  
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