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Feb 6th, 2016
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  1. module multiplier(prod, busy, mc, mp, clk, start);
  2. output [5:0] prod;
  3. output busy;
  4. input [2:0] mc, mp;
  5. input clk, start;
  6. reg [2:0] A, Q, M;
  7. reg Q_1;
  8. reg [3:0] count;
  9.  
  10. wire [2:0] sum, difference;
  11.  
  12. always @(posedge clk)
  13. begin
  14. if (start) begin
  15. A <= 3'b0;
  16. M <= mc;
  17. Q <= mp;
  18. Q_1 <= 1'b0;
  19. count <= 4'b0;
  20. end
  21. else begin
  22. case ({Q[0], Q_1})
  23. 2'b0_1 : {A, Q, Q_1} <= {sum[2], sum, Q};
  24. 2'b1_0 : {A, Q, Q_1} <= {difference[2], difference, Q};
  25. default: {A, Q, Q_1} <= {A[2], A, Q};
  26. endcase
  27. count <= count + 1'b1;
  28. end
  29. end
  30.  
  31. alu adder (sum, A, M, 1'b0);
  32. alu subtracter (difference, A, ~M, 1'b1);
  33.  
  34. assign prod = {A, Q};
  35. assign busy = (count < 2);
  36.  
  37.  
  38.  
  39. endmodule
  40. //The following is an alu.
  41. //It is an adder, but capable of subtraction:
  42. //Recall that subtraction means adding the two's complement--
  43. //a - b = a + (-b) = a + (inverted b + 1)
  44. //The 1 will be coming in as cin (carry-in)
  45. module alu(out, a, b, cin);
  46. output [2:0] out;
  47. input [2:0] a;
  48. input [2:0] b;
  49. input cin;
  50.  
  51. assign out = a + b + cin;
  52.  
  53. endmodule
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