Info: Saving generation log to /home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/systems/sockit/data/sockit_generation_1.rpt
Info: Starting: Create block symbol file (.bsf)
Info: ip-generate --project-directory=/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/systems/sockit/data/ --output-directory=/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/build/sockit/src/qsys/ --report-file=bsf:/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/systems/sockit/data/sockit.bsf --system-info=DEVICE_FAMILY="Cyclone V" --system-info=DEVICE=5CSXFC6D6F31C8ES --system-info=DEVICE_SPEEDGRADE=8_H6 --component-file=/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/systems/sockit/data/sockit.qsys
Progress: Loading data/sockit.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 13.0]
Progress: Parameterizing module clk_0
Progress: Adding hps_0 [altera_hps 13.0.1]
Progress: Parameterizing module hps_0
Progress: Adding mem_if_ddr3_emif_0 [altera_mem_if_ddr3_emif 13.0]
Progress: Parameterizing module mem_if_ddr3_emif_0
Progress: Adding mm_bridge_0 [altera_avalon_mm_bridge 13.0]
Progress: Parameterizing module mm_bridge_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: sockit.hps_0: Setting the slave port width of interface f2h_sdram0 to 32 results in bandwidth under-utilization.  Altera recommends you set the interface data width to 64-bit or greater.
Info: sockit.hps_0: Peripheral EMAC1 pin mapping: TX_CLK:MIXED1IO0, TXD0:MIXED1IO1, TXD1:MIXED1IO2, TXD2:MIXED1IO3, TXD3:MIXED1IO4, RXD0:MIXED1IO5, MDIO:MIXED1IO6, MDC:MIXED1IO7, RX_CTL:MIXED1IO8, TX_CTL:MIXED1IO9, RX_CLK:MIXED1IO10, RXD1:MIXED1IO11, RXD2:MIXED1IO12, RXD3:MIXED1IO13
Info: sockit.hps_0: Peripheral QSPI pin mapping: IO0:MIXED1IO15, IO1:MIXED1IO16, IO2:MIXED1IO17, IO3:MIXED1IO18, SS0:MIXED1IO19, CLK:MIXED1IO20
Info: sockit.hps_0: Peripheral SDIO pin mapping: CMD:FLASHIO0, D0:FLASHIO2, D1:FLASHIO3, CLK:FLASHIO9, D2:FLASHIO10, D3:FLASHIO11
Info: sockit.hps_0: Peripheral USB1 pin mapping: D0:EMACIO1, D1:EMACIO2, D2:EMACIO3, D3:EMACIO4, D4:EMACIO5, D5:EMACIO6, D6:EMACIO7, D7:EMACIO8, CLK:EMACIO10, STP:EMACIO11, DIR:EMACIO12, NXT:EMACIO13
Info: sockit.hps_0: Peripheral SPIM0 pin mapping: CLK:GENERALIO9, MOSI:GENERALIO10, MISO:GENERALIO11, SS0:GENERALIO12
Info: sockit.hps_0: Peripheral SPIM1 pin mapping: CLK:GENERALIO15, MOSI:GENERALIO16, MISO:GENERALIO17, SS0:GENERALIO18
Info: sockit.hps_0: Peripheral UART0 pin mapping: RX:GENERALIO1, TX:GENERALIO2
Info: sockit.hps_0: Peripheral I2C1 pin mapping: SDA:GENERALIO3, SCL:GENERALIO4
Warning: sockit.hps_0.fpga_interfaces.emac0_tx_reset: Associated reset sinks not declared
Warning: sockit.hps_0.fpga_interfaces.emac0_rx_reset: Associated reset sinks not declared
Warning: sockit.mem_if_ddr3_emif_0: The 'Type' value must be set to Bidirectional if you plan to simulate the example design.
Info: ip-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: ip-generate --project-directory=/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/systems/sockit/data/ --output-directory=/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/build/sockit/src/qsys/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/systems/sockit/data/sockit.sopcinfo --report-file=html:/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/systems/sockit/data/sockit.html --report-file=qip:/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/build/sockit/src/qsys/synthesis/sockit.qip --report-file=cmp:/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/systems/sockit/data/sockit.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone V" --system-info=DEVICE=5CSXFC6D6F31C8ES --system-info=DEVICE_SPEEDGRADE=8_H6 --component-file=/home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/systems/sockit/data/sockit.qsys --language=VERILOG
Progress: Loading data/sockit.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 13.0]
Progress: Parameterizing module clk_0
Progress: Adding hps_0 [altera_hps 13.0.1]
Progress: Parameterizing module hps_0
Progress: Adding mem_if_ddr3_emif_0 [altera_mem_if_ddr3_emif 13.0]
Progress: Parameterizing module mem_if_ddr3_emif_0
Progress: Adding mm_bridge_0 [altera_avalon_mm_bridge 13.0]
Progress: Parameterizing module mm_bridge_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: sockit.hps_0: Setting the slave port width of interface f2h_sdram0 to 32 results in bandwidth under-utilization.  Altera recommends you set the interface data width to 64-bit or greater.
Info: sockit.hps_0: Peripheral EMAC1 pin mapping: TX_CLK:MIXED1IO0, TXD0:MIXED1IO1, TXD1:MIXED1IO2, TXD2:MIXED1IO3, TXD3:MIXED1IO4, RXD0:MIXED1IO5, MDIO:MIXED1IO6, MDC:MIXED1IO7, RX_CTL:MIXED1IO8, TX_CTL:MIXED1IO9, RX_CLK:MIXED1IO10, RXD1:MIXED1IO11, RXD2:MIXED1IO12, RXD3:MIXED1IO13
Info: sockit.hps_0: Peripheral QSPI pin mapping: IO0:MIXED1IO15, IO1:MIXED1IO16, IO2:MIXED1IO17, IO3:MIXED1IO18, SS0:MIXED1IO19, CLK:MIXED1IO20
Info: sockit.hps_0: Peripheral SDIO pin mapping: CMD:FLASHIO0, D0:FLASHIO2, D1:FLASHIO3, CLK:FLASHIO9, D2:FLASHIO10, D3:FLASHIO11
Info: sockit.hps_0: Peripheral USB1 pin mapping: D0:EMACIO1, D1:EMACIO2, D2:EMACIO3, D3:EMACIO4, D4:EMACIO5, D5:EMACIO6, D6:EMACIO7, D7:EMACIO8, CLK:EMACIO10, STP:EMACIO11, DIR:EMACIO12, NXT:EMACIO13
Info: sockit.hps_0: Peripheral SPIM0 pin mapping: CLK:GENERALIO9, MOSI:GENERALIO10, MISO:GENERALIO11, SS0:GENERALIO12
Info: sockit.hps_0: Peripheral SPIM1 pin mapping: CLK:GENERALIO15, MOSI:GENERALIO16, MISO:GENERALIO17, SS0:GENERALIO18
Info: sockit.hps_0: Peripheral UART0 pin mapping: RX:GENERALIO1, TX:GENERALIO2
Info: sockit.hps_0: Peripheral I2C1 pin mapping: SDA:GENERALIO3, SCL:GENERALIO4
Warning: sockit.hps_0.fpga_interfaces.emac0_tx_reset: Associated reset sinks not declared
Warning: sockit.hps_0.fpga_interfaces.emac0_rx_reset: Associated reset sinks not declared
Warning: sockit.mem_if_ddr3_emif_0: The 'Type' value must be set to Bidirectional if you plan to simulate the example design.
Info: sockit: Generating sockit "sockit" for QUARTUS_SYNTH
Info: pipeline_bridge_swap_transform: After transform: 4 modules, 29 connections
Info: No custom instruction connections, skipping transform
Info: merlin_translator_transform: After transform: 6 modules, 35 connections
Info: merlin_domain_transform: After transform: 16 modules, 85 connections
Info: merlin_router_transform: After transform: 22 modules, 103 connections
Info: merlin_burst_transform: After transform: 24 modules, 109 connections
Info: com_altera_sopcmodel_transforms_avalon_CombinedWidthTransform: After transform: 25 modules, 113 connections
Info: reset_adaptation_transform: After transform: 29 modules, 119 connections
Info: merlin_network_to_switch_transform: After transform: 39 modules, 139 connections
Info: merlin_mm_transform: After transform: 39 modules, 139 connections
Info: hps_0: "Doing Pretransform for module: hps_0"
Warning: hps_0: Setting the slave port width of interface f2h_sdram0 to 32 results in bandwidth under-utilization.  Altera recommends you set the interface data width to 64-bit or greater.
Info: hps_0: Peripheral EMAC1 pin mapping: TX_CLK:MIXED1IO0, TXD0:MIXED1IO1, TXD1:MIXED1IO2, TXD2:MIXED1IO3, TXD3:MIXED1IO4, RXD0:MIXED1IO5, MDIO:MIXED1IO6, MDC:MIXED1IO7, RX_CTL:MIXED1IO8, TX_CTL:MIXED1IO9, RX_CLK:MIXED1IO10, RXD1:MIXED1IO11, RXD2:MIXED1IO12, RXD3:MIXED1IO13
Info: hps_0: Peripheral QSPI pin mapping: IO0:MIXED1IO15, IO1:MIXED1IO16, IO2:MIXED1IO17, IO3:MIXED1IO18, SS0:MIXED1IO19, CLK:MIXED1IO20
Info: hps_0: Peripheral SDIO pin mapping: CMD:FLASHIO0, D0:FLASHIO2, D1:FLASHIO3, CLK:FLASHIO9, D2:FLASHIO10, D3:FLASHIO11
Info: hps_0: Peripheral USB1 pin mapping: D0:EMACIO1, D1:EMACIO2, D2:EMACIO3, D3:EMACIO4, D4:EMACIO5, D5:EMACIO6, D6:EMACIO7, D7:EMACIO8, CLK:EMACIO10, STP:EMACIO11, DIR:EMACIO12, NXT:EMACIO13
Info: hps_0: Peripheral SPIM0 pin mapping: CLK:GENERALIO9, MOSI:GENERALIO10, MISO:GENERALIO11, SS0:GENERALIO12
Info: hps_0: Peripheral SPIM1 pin mapping: CLK:GENERALIO15, MOSI:GENERALIO16, MISO:GENERALIO17, SS0:GENERALIO18
Info: hps_0: Peripheral UART0 pin mapping: RX:GENERALIO1, TX:GENERALIO2
Info: hps_0: Peripheral I2C1 pin mapping: SDA:GENERALIO3, SCL:GENERALIO4
Warning: hps_0.fpga_interfaces.emac0_tx_reset: Associated reset sinks not declared
Warning: hps_0.fpga_interfaces.emac0_rx_reset: Associated reset sinks not declared
Info: pipeline_bridge_swap_transform: After transform: 2 modules, 0 connections
Info: No custom instruction connections, skipping transform
Info: No Avalon connections, skipping transform
Info: merlin_translator_transform: After transform: 2 modules, 0 connections
Info: hps_0: "sockit" instantiated altera_hps "hps_0"
Info: pipeline_bridge_swap_transform: After transform: 21 modules, 38 connections
Info: No custom instruction connections, skipping transform
Info: merlin_translator_transform: After transform: 21 modules, 38 connections
Info: mem_if_ddr3_emif_0: "sockit" instantiated altera_mem_if_ddr3_emif "mem_if_ddr3_emif_0"
Info: mm_bridge_0: "sockit" instantiated altera_avalon_mm_bridge "mm_bridge_0"
Info: mem_if_ddr3_emif_0_avl_1_translator: "sockit" instantiated altera_merlin_slave_translator "mem_if_ddr3_emif_0_avl_1_translator"
Info: hps_0_h2f_axi_master_agent: "sockit" instantiated altera_merlin_axi_master_ni "hps_0_h2f_axi_master_agent"
Info: mem_if_ddr3_emif_0_avl_1_translator_avalon_universal_slave_0_agent: "sockit" instantiated altera_merlin_slave_agent "mem_if_ddr3_emif_0_avl_1_translator_avalon_universal_slave_0_agent"
Info: mem_if_ddr3_emif_0_avl_1_translator_avalon_universal_slave_0_agent_rsp_fifo: "sockit" instantiated altera_avalon_sc_fifo "mem_if_ddr3_emif_0_avl_1_translator_avalon_universal_slave_0_agent_rsp_fifo"
Info: addr_router: "sockit" instantiated altera_merlin_router "addr_router"
Info: id_router: "sockit" instantiated altera_merlin_router "id_router"
Info: addr_router_002: "sockit" instantiated altera_merlin_router "addr_router_002"
Info: id_router_001: "sockit" instantiated altera_merlin_router "id_router_001"
Info: burst_adapter: "sockit" instantiated altera_merlin_burst_adapter "burst_adapter"
Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/build/sockit/src/qsys/synthesis/submodules/altera_merlin_address_alignment.sv
Info: width_adapter: "sockit" instantiated altera_merlin_combined_width_adapter "width_adapter"
Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/build/sockit/src/qsys/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/build/sockit/src/qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/build/sockit/src/qsys/synthesis/submodules/altera_avalon_sc_fifo.v
Info: rst_controller: "sockit" instantiated altera_reset_controller "rst_controller"
Info: cmd_xbar_demux: "sockit" instantiated altera_merlin_demultiplexer "cmd_xbar_demux"
Info: cmd_xbar_mux: "sockit" instantiated altera_merlin_multiplexer "cmd_xbar_mux"
Info: rsp_xbar_demux: "sockit" instantiated altera_merlin_demultiplexer "rsp_xbar_demux"
Info: cmd_xbar_demux_002: "sockit" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_002"
Info: cmd_xbar_mux_001: "sockit" instantiated altera_merlin_multiplexer "cmd_xbar_mux_001"
Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/orpsoc-cores/build/sockit/src/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_xbar_demux_001: "sockit" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_001"
Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
Info: pipeline_bridge_swap_transform: After transform: 1 modules, 0 connections
Info: No custom instruction connections, skipping transform
Info: No Avalon connections, skipping transform
Info: merlin_translator_transform: After transform: 1 modules, 0 connections
Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
Info: pll0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_pll "pll0"
Info: p0: Generating clock pair generator
Info: p0: Generating sockit_mem_if_ddr3_emif_0_p0_altdqdqs
Info: p0:
Info: p0: *****************************
Info: p0:
Info: p0: Remember to run the sockit_mem_if_ddr3_emif_0_p0_pin_assignments.tcl
Info: p0: script after running Synthesis and before Fitting.
Info: p0:
Info: p0: *****************************
Info: p0:
Info: p0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
    while executing
"error "An error occurred""
    (procedure "_error" line 8)
    invoked from within
"_error "Cannot find $seq_file""
    ("if" then script line 2)
    invoked from within
"if {[file exists $seq_file] == 0} {
		_error "Cannot find $seq_file"
	}"
    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
    invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
    invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
    ("if" then script line 2)
    invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
		set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
    (procedure "generate_qsys_sequencer_sw" line 777)
    invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."
    invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."
    ("if" else script line 2)
    invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
		set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
    (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 195)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
    invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
    invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
		set file_name [file tail $genera..."
    (procedure "generate_synth" line 8)
    invoked from within
"generate_synth sockit_mem_if_ddr3_emif_0_s0"
Info: s0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_qseq "s0"
Error: Generation stopped, 4 or more modules remaining
Info: sockit: Done sockit" with 30 modules, 76 files, 1585580 bytes
Error: ip-generate failed with exit code 1: 3 Errors, 7 Warnings
Info: Finished: Create HDL design files for synthesis