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- entity vga_sdram is
- generic (
- -- VGA Info
- HD : integer := 640; -- Horizontal display area
- HF : integer := 16; -- Horizontal front porch
- HB : integer := 48; -- Horizontal back porch
- HR : integer := 96; -- Horizontal retrace
- VD : integer := 480; -- Vertical display area
- VF : integer := 10; -- Vertical front porch
- VB : integer := 31; -- Vertical back porch
- VR : integer := 2; -- Vertical retrace
- -- bits per pixels
- RED_WIDTH : integer := 4;
- GREEN_WIDTH : integer := 4;
- BLUE_WIDTH : integer := 4;
- ADDR_WIDTH : integer := 22;
- DATA_WIDTH : integer := 16;
- BUF_WIDTH : integer := 12
- );
- port (
- clock : in std_logic;
- reset : in std_logic;
- -- VGA interface
- hsync : out std_logic;
- vsync : out std_logic;
- red : out std_logic_vector(RED_WIDTH - 1 downto 0);
- green : out std_logic_vector(GREEN_WIDTH - 1 downto 0);
- blue : out std_logic_vector(BLUE_WIDTH - 1 downto 0);
- -- sdram interface
- mem_busy : in std_logic;
- mem_strobe : out std_logic;
- mem_wr : out std_logic;
- mem_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
- mem_nwords : out std_logic_vector(BUF_WIDTH - 1 downto 0);
- buf_clock : in std_logic;
- buf_wr : in std_logic;
- buf_addr : in std_logic_vector(BUF_WIDTH - 1 downto 0);
- buf_data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
- buf_data_o : out std_logic_vector(DATA_WIDTH - 1 downto 0)
- );
- end vga_sdram;
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