library ieee;
use ieee.std_logic_1164.all;

entity Upp2 is port (
SW0,SW1,SW2,SW3: in std_logic;
HEX0: out std_logic_vector(6 downto 0));
end Upp2;

architecture arch of Upp2 is
begin
    process(SW0,SW1,SW2,SW3)
        variable swich: std_logic_vector(3 downto 0);
    begin

    swich := SW3 & SW2 & SW1 & SW0;
    case swich is
        when "0000" =>
           HEX0 <= "1000000";
        when "0001" =>
           HEX0 <= "1111001";
        when "0010" =>
           HEX0 <= "0100100";
        when "0011" =>
           HEX0 <= "0110000";
        when "0100" =>
           HEX0 <= "0011001";
        when "0101" =>
           HEX0 <= "0010010";
        when "0110" =>
           HEX0 <= "0000010";
        when "0111" =>
           HEX0 <= "1111000";
        when "1000" =>
           HEX0 <= "0000000";
        when "1001" =>
           HEX0 <= "0011000";
        when others =>
           HEX0 <= "0111111";
    end case;
     end process;
end arch;