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Minsoc Synthesis log

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Nov 12th, 2012
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  1. make prepare
  2. make[1]: Entering directory `/home/aurabindo/minsoc/syn'
  3. rm -rf xst
  4. mkdir xst
  5. make[1]: Leaving directory `/home/aurabindo/minsoc/syn'
  6. xst -ifn "..//syn/buildSupport/minsoc_top.xst"
  7. Release 13.2 - xst O.61xd (lin)
  8. Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
  9. -->
  10. Parameter TMPDIR set to ./xst
  11.  
  12.  
  13. Total REAL time to Xst completion: 0.00 secs
  14. Total CPU time to Xst completion: 0.07 secs
  15.  
  16. -->
  17.  
  18. TABLE OF CONTENTS
  19. 1) Synthesis Options Summary
  20. 2) HDL Compilation
  21. 3) Design Hierarchy Analysis
  22. 4) HDL Analysis
  23. 5) HDL Synthesis
  24. 5.1) HDL Synthesis Report
  25. 6) Advanced HDL Synthesis
  26. 6.1) Advanced HDL Synthesis Report
  27. 7) Low Level Synthesis
  28. 8) Partition Report
  29. 9) Final Report
  30. 9.1) Device utilization summary
  31. 9.2) Partition Resource Summary
  32. 9.3) TIMING REPORT
  33.  
  34.  
  35. =========================================================================
  36. * Synthesis Options Summary *
  37. =========================================================================
  38. ---- Source Parameters
  39. Verilog Include Directory : { "/home/aurabindo/minsoc/prj/../backend" "/home/aurabindo/minsoc/prj/../rtl/verilog" "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_startup" "/home/aurabindo/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" "/home/aurabindo/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" "/home/aurabindo/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" "/home/aurabindo/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" }
  40. Input File Name : "/home/aurabindo/minsoc/prj/../prj/xilinx/minsoc_top.prj"
  41. Input Format : Verilog
  42.  
  43. ---- Target Parameters
  44. Output File Name : "minsoc_top"
  45. Output Format : NGC
  46. Target Device : xc3s500e-4-fg320
  47.  
  48. ---- Source Options
  49. Top Module Name : minsoc_top
  50.  
  51. ---- Target Options
  52. Add IO Buffers : yes
  53.  
  54. ---- General Options
  55. Optimization Goal : Speed
  56. Optimization Effort : 1
  57.  
  58. =========================================================================
  59.  
  60.  
  61. =========================================================================
  62. * HDL Compilation *
  63. =========================================================================
  64. Compiling verilog file "/home/aurabindo/minsoc/prj/../prj/xilinx/minsoc_top.prj" in library work
  65. Compiling verilog include file "/home/aurabindo/minsoc/prj/../backend/minsoc_defines.v"
  66. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/timescale.v"
  67. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_top.v"
  68. Compiling verilog include file "/home/aurabindo/minsoc/prj/../backend/minsoc_defines.v"
  69. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v"
  70. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v"
  71. Module <minsoc_top> compiled
  72. Module <minsoc_tc_top> compiled
  73. Module <tc_mi_to_st> compiled
  74. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v"
  75. Compiling verilog include file "/home/aurabindo/minsoc/prj/../backend/minsoc_defines.v"
  76. Module <tc_si_to_mt> compiled
  77. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v"
  78. Module <minsoc_onchip_ram> compiled
  79. Module <minsoc_onchip_ram_top> compiled
  80. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v"
  81. Compiling verilog include file "/home/aurabindo/minsoc/prj/../backend/minsoc_defines.v"
  82. Module <mux2> compiled
  83. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/altera_pll.v"
  84. Compiling verilog include file "/home/aurabindo/minsoc/prj/../backend/minsoc_defines.v"
  85. Module <minsoc_clock_manager> compiled
  86. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/xilinx_dcm.v"
  87. Compiling verilog include file "/home/aurabindo/minsoc/prj/../backend/minsoc_defines.v"
  88. Module <altera_pll> compiled
  89. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v"
  90. Compiling verilog include file "/home/aurabindo/minsoc/prj/../backend/minsoc_defines.v"
  91. Module <xilinx_dcm> compiled
  92. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v"
  93. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v"
  94. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/timescale.v"
  95. Module <minsoc_xilinx_internal_jtag> compiled
  96. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v"
  97. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v"
  98. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v"
  99. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/timescale.v"
  100. Module <spi_flash_top> compiled
  101. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v"
  102. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v"
  103. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/timescale.v"
  104. Module <spi_flash_shift> compiled
  105. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v"
  106. Compiling verilog include file "/home/aurabindo/minsoc/prj/../backend/minsoc_defines.v"
  107. Module <spi_flash_clgen> compiled
  108. Compiling verilog include file "/home/aurabindo/minsoc/prj/src/blackboxes/adbg_top.v"
  109. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v"
  110. Module <OR1K_startup> compiled
  111. Compiling verilog include file "/home/aurabindo/minsoc/prj/src/blackboxes/ethmac.v"
  112. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v"
  113. Module <adbg_top> compiled
  114. Compiling verilog include file "/home/aurabindo/minsoc/prj/src/blackboxes/or1200_top.v"
  115. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v"
  116. Module <ethmac> compiled
  117. Compiling verilog include file "/home/aurabindo/minsoc/prj/src/blackboxes/uart_top.v"
  118. Compiling verilog include file "/home/aurabindo/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v"
  119. Module <or1200_top> compiled
  120. Module <uart_top> compiled
  121. No errors in compilation
  122. Analysis of file <"/home/aurabindo/minsoc/prj/../prj/xilinx/minsoc_top.prj"> succeeded.
  123.  
  124.  
  125. =========================================================================
  126. * Design Hierarchy Analysis *
  127. =========================================================================
  128. Analyzing hierarchy for module <minsoc_top> in library <work>.
  129.  
  130. Analyzing hierarchy for module <minsoc_clock_manager> in library <work> with parameters.
  131. divisor = "00000000000000000000000000000010"
  132.  
  133. Analyzing hierarchy for module <minsoc_xilinx_internal_jtag> in library <work> with parameters.
  134. virtex_jtag_chain = "00000000000000000000000000000001"
  135.  
  136. Analyzing hierarchy for module <minsoc_onchip_ram_top> in library <work> with parameters.
  137. adr_width = "00000000000000000000000000001101"
  138. aw_int = "00000000000000000000000000001011"
  139. blocks = "00000000000000000000000000000100"
  140. mux_in_nr = "00000000000000000000000000000100"
  141. mux_out_nr = "00000000000000000000000000000011"
  142. slices = "00000000000000000000000000000010"
  143.  
  144. Analyzing hierarchy for module <minsoc_tc_top> in library <work> with parameters.
  145. t0_addr = "00000000"
  146. t0_addr_w = "00000000000000000000000000001000"
  147. t1_addr = "00000100"
  148. t1_addr_w = "00000000000000000000000000001000"
  149. t28_addr = "1001"
  150. t28c_addr_w = "00000000000000000000000000000100"
  151. t28i_addr_w = "00000000000000000000000000001000"
  152. t2_addr = "10010111"
  153. t3_addr = "10010010"
  154. t4_addr = "10011101"
  155. t5_addr = "10010000"
  156. t6_addr = "10010100"
  157. t7_addr = "10011110"
  158. t8_addr = "10011111"
  159.  
  160. Analyzing hierarchy for module <xilinx_dcm> in library <work> with parameters.
  161. divisor = "00000000000000000000000000000010"
  162.  
  163. Analyzing hierarchy for module <mux2> in library <work> with parameters.
  164. dw = "00000000000000000000000000100000"
  165.  
  166. Analyzing hierarchy for module <minsoc_onchip_ram> in library <work> with parameters.
  167. aw = "00000000000000000000000000001011"
  168. dw = "00000000000000000000000000001000"
  169.  
  170. Analyzing hierarchy for module <tc_mi_to_st> in library <work> with parameters.
  171. multitarg = "00000000000000000000000000000000"
  172. t0_addr = "00000000"
  173. t0_addr_w = "00000000000000000000000000001000"
  174. t17_addr = "00000000"
  175. t17_addr_w = "00000000000000000000000000001000"
  176.  
  177. Analyzing hierarchy for module <tc_mi_to_st> in library <work> with parameters.
  178. multitarg = "00000000000000000000000000000001"
  179. t0_addr = "00000100"
  180. t0_addr_w = "00000000000000000000000000001000"
  181. t17_addr = "1001"
  182. t17_addr_w = "00000000000000000000000000000100"
  183.  
  184. Analyzing hierarchy for module <tc_si_to_mt> in library <work> with parameters.
  185. t0_addr = "00000100"
  186. t0_addr_w = "00000000000000000000000000001000"
  187. t17_addr_w = "00000000000000000000000000001000"
  188. t1_addr = "10010111"
  189. t2_addr = "10010010"
  190. t3_addr = "10011101"
  191. t4_addr = "10010000"
  192. t5_addr = "10010100"
  193. t6_addr = "10011110"
  194. t7_addr = "10011111"
  195.  
  196.  
  197. =========================================================================
  198. * HDL Analysis *
  199. =========================================================================
  200. Analyzing top module <minsoc_top>.
  201. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_top.v" line 285: Delay is ignored for synthesis.
  202. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_top.v" line 291: Delay is ignored for synthesis.
  203. WARNING:Xst:2211 - "/home/aurabindo/minsoc/prj/src/blackboxes/adbg_top.v" line 406: Instantiating black box module <adbg_top>.
  204. WARNING:Xst:2211 - "/home/aurabindo/minsoc/prj/src/blackboxes/or1200_top.v" line 522: Instantiating black box module <or1200_top>.
  205. WARNING:Xst:2211 - "/home/aurabindo/minsoc/prj/src/blackboxes/uart_top.v" line 673: Instantiating black box module <uart_top>.
  206. Module <minsoc_top> is correct for synthesis.
  207.  
  208. Set user-defined property "aw = 00000020" for instance <or1200_top> in unit <minsoc_top>.
  209. Set user-defined property "dw = 00000020" for instance <or1200_top> in unit <minsoc_top>.
  210. Set user-defined property "ppic_ints = 00000014" for instance <or1200_top> in unit <minsoc_top>.
  211. Set user-defined property "uart_addr_width = 00000005" for instance <uart_top> in unit <minsoc_top>.
  212. Set user-defined property "uart_data_width = 00000020" for instance <uart_top> in unit <minsoc_top>.
  213. Analyzing module <minsoc_clock_manager> in library <work>.
  214. divisor = 32'sb00000000000000000000000000000010
  215. Module <minsoc_clock_manager> is correct for synthesis.
  216.  
  217. Analyzing module <xilinx_dcm> in library <work>.
  218. divisor = 32'sb00000000000000000000000000000010
  219. Module <xilinx_dcm> is correct for synthesis.
  220.  
  221. Set user-defined property "CAPACITANCE = DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <xilinx_dcm>.
  222. Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <CLKIN_IBUFG_INST> in unit <xilinx_dcm>.
  223. Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <CLKIN_IBUFG_INST> in unit <xilinx_dcm>.
  224. Set user-defined property "IOSTANDARD = DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <xilinx_dcm>.
  225. Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  226. Set user-defined property "CLKFX_DIVIDE = 1" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  227. Set user-defined property "CLKFX_MULTIPLY = 4" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  228. Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  229. Set user-defined property "CLKIN_PERIOD = 0.000000" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  230. Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  231. Set user-defined property "CLK_FEEDBACK = 1X" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  232. Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  233. Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  234. Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  235. Set user-defined property "DSS_MODE = NONE" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  236. Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  237. Set user-defined property "FACTORY_JF = C080" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  238. Set user-defined property "PHASE_SHIFT = 0" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  239. Set user-defined property "STARTUP_WAIT = FALSE" for instance <DCM_SP_inst> in unit <xilinx_dcm>.
  240. Analyzing module <minsoc_xilinx_internal_jtag> in library <work>.
  241. virtex_jtag_chain = 32'sb00000000000000000000000000000001
  242. Module <minsoc_xilinx_internal_jtag> is correct for synthesis.
  243.  
  244. Analyzing module <minsoc_onchip_ram_top> in library <work>.
  245. adr_width = 32'sb00000000000000000000000000001101
  246. aw_int = 32'sb00000000000000000000000000001011
  247. blocks = 32'sb00000000000000000000000000000100
  248. mux_in_nr = 32'sb00000000000000000000000000000100
  249. mux_out_nr = 32'sb00000000000000000000000000000011
  250. slices = 32'sb00000000000000000000000000000010
  251. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v" line 118: Delay is ignored for synthesis.
  252. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v" line 120: Delay is ignored for synthesis.
  253. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v" line 132: Delay is ignored for synthesis.
  254. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v" line 134: Delay is ignored for synthesis.
  255. Module <minsoc_onchip_ram_top> is correct for synthesis.
  256.  
  257. Analyzing module <mux2> in library <work>.
  258. dw = 32'sb00000000000000000000000000100000
  259. Module <mux2> is correct for synthesis.
  260.  
  261. Analyzing module <minsoc_onchip_ram> in library <work>.
  262. aw = 32'sb00000000000000000000000000001011
  263. dw = 32'sb00000000000000000000000000001000
  264. Module <minsoc_onchip_ram> is correct for synthesis.
  265.  
  266. Set user-defined property "INIT = 000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  267. Set user-defined property "INITP_00 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  268. Set user-defined property "INITP_01 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  269. Set user-defined property "INITP_02 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  270. Set user-defined property "INITP_03 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  271. Set user-defined property "INITP_04 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  272. Set user-defined property "INITP_05 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  273. Set user-defined property "INITP_06 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  274. Set user-defined property "INITP_07 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  275. Set user-defined property "INIT_00 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  276. Set user-defined property "INIT_01 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  277. Set user-defined property "INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  278. Set user-defined property "INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  279. Set user-defined property "INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  280. Set user-defined property "INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  281. Set user-defined property "INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  282. Set user-defined property "INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  283. Set user-defined property "INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  284. Set user-defined property "INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  285. Set user-defined property "INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  286. Set user-defined property "INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  287. Set user-defined property "INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  288. Set user-defined property "INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  289. Set user-defined property "INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  290. Set user-defined property "INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  291. Set user-defined property "INIT_10 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  292. Set user-defined property "INIT_11 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  293. Set user-defined property "INIT_12 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  294. Set user-defined property "INIT_13 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  295. Set user-defined property "INIT_14 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  296. Set user-defined property "INIT_15 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  297. Set user-defined property "INIT_16 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  298. Set user-defined property "INIT_17 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  299. Set user-defined property "INIT_18 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  300. Set user-defined property "INIT_19 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  301. Set user-defined property "INIT_1A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  302. Set user-defined property "INIT_1B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  303. Set user-defined property "INIT_1C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  304. Set user-defined property "INIT_1D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  305. Set user-defined property "INIT_1E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  306. Set user-defined property "INIT_1F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  307. Set user-defined property "INIT_20 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  308. Set user-defined property "INIT_21 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  309. Set user-defined property "INIT_22 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  310. Set user-defined property "INIT_23 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  311. Set user-defined property "INIT_24 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  312. Set user-defined property "INIT_25 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  313. Set user-defined property "INIT_26 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  314. Set user-defined property "INIT_27 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  315. Set user-defined property "INIT_28 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  316. Set user-defined property "INIT_29 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  317. Set user-defined property "INIT_2A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  318. Set user-defined property "INIT_2B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  319. Set user-defined property "INIT_2C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  320. Set user-defined property "INIT_2D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  321. Set user-defined property "INIT_2E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  322. Set user-defined property "INIT_2F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  323. Set user-defined property "INIT_30 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  324. Set user-defined property "INIT_31 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  325. Set user-defined property "INIT_32 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  326. Set user-defined property "INIT_33 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  327. Set user-defined property "INIT_34 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  328. Set user-defined property "INIT_35 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  329. Set user-defined property "INIT_36 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  330. Set user-defined property "INIT_37 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  331. Set user-defined property "INIT_38 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  332. Set user-defined property "INIT_39 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  333. Set user-defined property "INIT_3A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  334. Set user-defined property "INIT_3B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  335. Set user-defined property "INIT_3C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  336. Set user-defined property "INIT_3D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  337. Set user-defined property "INIT_3E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  338. Set user-defined property "INIT_3F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  339. Set user-defined property "SRVAL = 000" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  340. Set user-defined property "WRITE_MODE = WRITE_FIRST" for instance <ramb16_s9> in unit <minsoc_onchip_ram>.
  341. Analyzing module <minsoc_tc_top> in library <work>.
  342. t0_addr = 8'b00000000
  343. t0_addr_w = 32'sb00000000000000000000000000001000
  344. t1_addr = 8'b00000100
  345. t1_addr_w = 32'sb00000000000000000000000000001000
  346. t28_addr = 4'b1001
  347. t28c_addr_w = 32'sb00000000000000000000000000000100
  348. t28i_addr_w = 32'sb00000000000000000000000000001000
  349. t2_addr = 8'b10010111
  350. t3_addr = 8'b10010010
  351. t4_addr = 8'b10011101
  352. t5_addr = 8'b10010000
  353. t6_addr = 8'b10010100
  354. t7_addr = 8'b10011110
  355. t8_addr = 8'b10011111
  356. Module <minsoc_tc_top> is correct for synthesis.
  357.  
  358. Analyzing module <tc_mi_to_st.1> in library <work>.
  359. multitarg = 32'sb00000000000000000000000000000000
  360. t0_addr = 8'b00000000
  361. t0_addr_w = 32'sb00000000000000000000000000001000
  362. t17_addr = 8'b00000000
  363. t17_addr_w = 32'sb00000000000000000000000000001000
  364. "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" line 1310: Found Parallel Case directive in module <tc_mi_to_st.1>.
  365. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" line 1326: Delay is ignored for synthesis.
  366. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" line 1328: Delay is ignored for synthesis.
  367. Module <tc_mi_to_st.1> is correct for synthesis.
  368.  
  369. Analyzing module <tc_mi_to_st.2> in library <work>.
  370. multitarg = 32'sb00000000000000000000000000000001
  371. t0_addr = 8'b00000100
  372. t0_addr_w = 32'sb00000000000000000000000000001000
  373. t17_addr = 4'b1001
  374. t17_addr_w = 32'sb00000000000000000000000000000100
  375. "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" line 1310: Found Parallel Case directive in module <tc_mi_to_st.2>.
  376. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" line 1326: Delay is ignored for synthesis.
  377. WARNING:Xst:916 - "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" line 1328: Delay is ignored for synthesis.
  378. Module <tc_mi_to_st.2> is correct for synthesis.
  379.  
  380. Analyzing module <tc_si_to_mt> in library <work>.
  381. t0_addr = 8'b00000100
  382. t0_addr_w = 32'sb00000000000000000000000000001000
  383. t17_addr_w = 32'sb00000000000000000000000000001000
  384. t1_addr = 8'b10010111
  385. t2_addr = 8'b10010010
  386. t3_addr = 8'b10011101
  387. t4_addr = 8'b10010000
  388. t5_addr = 8'b10010100
  389. t6_addr = 8'b10011110
  390. t7_addr = 8'b10011111
  391. Module <tc_si_to_mt> is correct for synthesis.
  392.  
  393.  
  394. =========================================================================
  395. * HDL Synthesis *
  396. =========================================================================
  397.  
  398. Performing bidirectional port resolution...
  399.  
  400. Synthesizing Unit <mux2>.
  401. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v".
  402. Unit <mux2> synthesized.
  403.  
  404.  
  405. Synthesizing Unit <tc_mi_to_st_1>.
  406. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v".
  407. WARNING:Xst:646 - Signal <t0_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  408. INFO:Xst:2117 - HDL ADVISOR - Mux Selector <req_won> of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
  409. - add an 'INIT' attribute on signal <req_won> (optimization is then done without any risk)
  410. - use the attribute 'signal_encoding user' to avoid onehot optimization
  411. - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
  412. Using one-hot encoding for signal <req_r>.
  413. Using one-hot encoding for signal <req_won>.
  414. Found 8-bit register for signal <req_r>.
  415. Unit <tc_mi_to_st_1> synthesized.
  416.  
  417.  
  418. Synthesizing Unit <tc_mi_to_st_2>.
  419. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v".
  420. WARNING:Xst:646 - Signal <t0_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  421. INFO:Xst:2117 - HDL ADVISOR - Mux Selector <req_won> of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
  422. - add an 'INIT' attribute on signal <req_won> (optimization is then done without any risk)
  423. - use the attribute 'signal_encoding user' to avoid onehot optimization
  424. - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
  425. Using one-hot encoding for signal <req_r>.
  426. Using one-hot encoding for signal <req_won>.
  427. Found 8-bit register for signal <req_r>.
  428. Unit <tc_mi_to_st_2> synthesized.
  429.  
  430.  
  431. Synthesizing Unit <tc_si_to_mt>.
  432. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v".
  433. WARNING:Xst:646 - Signal <t7_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  434. WARNING:Xst:646 - Signal <t6_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  435. WARNING:Xst:646 - Signal <t5_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  436. WARNING:Xst:646 - Signal <t4_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  437. WARNING:Xst:646 - Signal <t3_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  438. WARNING:Xst:646 - Signal <t2_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  439. WARNING:Xst:646 - Signal <t1_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  440. WARNING:Xst:646 - Signal <t0_out<71>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  441. Unit <tc_si_to_mt> synthesized.
  442.  
  443.  
  444. Synthesizing Unit <minsoc_xilinx_internal_jtag>.
  445. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v".
  446. INFO:Xst:1608 - Relative priorities of control signals on register <update_out> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  447. WARNING:Xst:2474 - Clock and clock enable of register <update_out> are driven by the same logic. The clock enable is removed.
  448. Found 1-bit register for signal <update_out>.
  449. Summary:
  450. inferred 1 D-type flip-flop(s).
  451. Unit <minsoc_xilinx_internal_jtag> synthesized.
  452.  
  453.  
  454. Synthesizing Unit <minsoc_tc_top>.
  455. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_tc_top.v".
  456. Unit <minsoc_tc_top> synthesized.
  457.  
  458.  
  459. Synthesizing Unit <xilinx_dcm>.
  460. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/xilinx_dcm.v".
  461. Unit <xilinx_dcm> synthesized.
  462.  
  463.  
  464. Synthesizing Unit <minsoc_onchip_ram>.
  465. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v".
  466. Found 8-bit tristate buffer for signal <doq>.
  467. Summary:
  468. inferred 8 Tristate(s).
  469. Unit <minsoc_onchip_ram> synthesized.
  470.  
  471.  
  472. Synthesizing Unit <minsoc_clock_manager>.
  473. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v".
  474. Unit <minsoc_clock_manager> synthesized.
  475.  
  476.  
  477. Synthesizing Unit <minsoc_onchip_ram_top>.
  478. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v".
  479. WARNING:Xst:647 - Input <wb_adr_i<31:24>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  480. WARNING:Xst:647 - Input <wb_adr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  481. Found 1-bit register for signal <ack_re>.
  482. Found 1-bit register for signal <ack_we>.
  483. Summary:
  484. inferred 2 D-type flip-flop(s).
  485. Unit <minsoc_onchip_ram_top> synthesized.
  486.  
  487.  
  488. Synthesizing Unit <minsoc_top>.
  489. Related source file is "/home/aurabindo/minsoc/prj/../rtl/verilog/minsoc_top.v".
  490. WARNING:Xst:646 - Signal <wb_us_adr_i<31:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  491. WARNING:Xst:646 - Signal <wb_sp_we_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  492. WARNING:Xst:646 - Signal <wb_sp_stb_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  493. WARNING:Xst:646 - Signal <wb_sp_sel_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  494. WARNING:Xst:646 - Signal <wb_sp_dat_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  495. WARNING:Xst:646 - Signal <wb_sp_cyc_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  496. WARNING:Xst:646 - Signal <wb_sp_adr_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  497. WARNING:Xst:646 - Signal <wb_fs_we_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  498. WARNING:Xst:646 - Signal <wb_fs_stb_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  499. WARNING:Xst:646 - Signal <wb_fs_sel_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  500. WARNING:Xst:646 - Signal <wb_fs_dat_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  501. WARNING:Xst:646 - Signal <wb_fs_cyc_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  502. WARNING:Xst:646 - Signal <wb_fs_adr_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  503. WARNING:Xst:646 - Signal <wb_es_we_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  504. WARNING:Xst:646 - Signal <wb_es_stb_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  505. WARNING:Xst:646 - Signal <wb_es_sel_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  506. WARNING:Xst:646 - Signal <wb_es_dat_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  507. WARNING:Xst:646 - Signal <wb_es_cyc_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  508. WARNING:Xst:646 - Signal <wb_es_adr_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  509. WARNING:Xst:646 - Signal <wb_em_err_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  510. WARNING:Xst:646 - Signal <wb_em_dat_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  511. WARNING:Xst:646 - Signal <wb_em_ack_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  512. WARNING:Xst:1780 - Signal <spi_flash_ss> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  513. WARNING:Xst:1780 - Signal <spi_flash_sclk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  514. WARNING:Xst:1780 - Signal <spi_flash_mosi> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  515. WARNING:Xst:1780 - Signal <spi_flash_miso> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  516. WARNING:Xst:1780 - Signal <eth_mdoe> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  517. WARNING:Xst:1780 - Signal <eth_mdo> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  518. WARNING:Xst:646 - Signal <dbg_wp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  519. WARNING:Xst:646 - Signal <dbg_lss> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  520. WARNING:Xst:646 - Signal <dbg_is> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  521. WARNING:Xst:1780 - Signal <dbg_ewt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  522. Found 1-bit register for signal <rst_r>.
  523. Found 1-bit register for signal <wb_rst>.
  524. Summary:
  525. inferred 2 D-type flip-flop(s).
  526. Unit <minsoc_top> synthesized.
  527.  
  528.  
  529. =========================================================================
  530. HDL Synthesis Report
  531.  
  532. Macro Statistics
  533. # Registers : 7
  534. 1-bit register : 5
  535. 8-bit register : 2
  536. # Tristates : 16
  537. 8-bit tristate buffer : 16
  538.  
  539. =========================================================================
  540.  
  541. =========================================================================
  542. * Advanced HDL Synthesis *
  543. =========================================================================
  544.  
  545.  
  546. =========================================================================
  547. Advanced HDL Synthesis Report
  548.  
  549. Macro Statistics
  550. # Registers : 21
  551. Flip-Flops : 21
  552.  
  553. =========================================================================
  554.  
  555. =========================================================================
  556. * Low Level Synthesis *
  557. =========================================================================
  558. WARNING:Xst:1710 - FF/Latch <req_r_7> (without init value) has a constant value of 0 in block <tc_mi_to_st_1>. This FF/Latch will be trimmed during the optimization process.
  559. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <req_r_6> (without init value) has a constant value of 0 in block <tc_mi_to_st_1>. This FF/Latch will be trimmed during the optimization process.
  560. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <req_r_2> (without init value) has a constant value of 0 in block <tc_mi_to_st_1>. This FF/Latch will be trimmed during the optimization process.
  561. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <req_r_1> (without init value) has a constant value of 0 in block <tc_mi_to_st_1>. This FF/Latch will be trimmed during the optimization process.
  562. WARNING:Xst:1710 - FF/Latch <req_r_7> (without init value) has a constant value of 0 in block <tc_mi_to_st_2>. This FF/Latch will be trimmed during the optimization process.
  563. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <req_r_6> (without init value) has a constant value of 0 in block <tc_mi_to_st_2>. This FF/Latch will be trimmed during the optimization process.
  564. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <req_r_2> (without init value) has a constant value of 0 in block <tc_mi_to_st_2>. This FF/Latch will be trimmed during the optimization process.
  565. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <req_r_1> (without init value) has a constant value of 0 in block <tc_mi_to_st_2>. This FF/Latch will be trimmed during the optimization process.
  566. WARNING:Xst:2042 - Unit minsoc_onchip_ram: 8 internal tristates are replaced by logic (pull-up yes): doq<0>, doq<1>, doq<2>, doq<3>, doq<4>, doq<5>, doq<6>, doq<7>.
  567.  
  568. Optimizing unit <minsoc_top> ...
  569.  
  570. Optimizing unit <tc_si_to_mt> ...
  571.  
  572. Optimizing unit <minsoc_onchip_ram> ...
  573.  
  574. Optimizing unit <tc_mi_to_st_1> ...
  575.  
  576. Optimizing unit <tc_mi_to_st_2> ...
  577.  
  578. Optimizing unit <minsoc_onchip_ram_top> ...
  579.  
  580. Optimizing unit <minsoc_tc_top> ...
  581. WARNING:Xst:2677 - Node <tc_top/t18_ch_upper/req_r_0> of sequential type is unconnected in block <minsoc_top>.
  582. WARNING:Xst:2677 - Node <tc_top/t0_ch/req_r_0> of sequential type is unconnected in block <minsoc_top>.
  583.  
  584. Mapping all equations...
  585. WARNING:Xst:2036 - Inserting OBUF on port <uart_stx> driven by black box <uart_top>. Possible simulation mismatch.
  586. Building and optimizing final netlist ...
  587.  
  588. Final Macro Processing ...
  589.  
  590. =========================================================================
  591. Final Register Report
  592.  
  593. Macro Statistics
  594. # Registers : 11
  595. Flip-Flops : 11
  596.  
  597. =========================================================================
  598.  
  599. =========================================================================
  600. * Partition Report *
  601. =========================================================================
  602.  
  603. Partition Implementation Status
  604. -------------------------------
  605.  
  606. No Partitions were found in this design.
  607.  
  608. -------------------------------
  609.  
  610. =========================================================================
  611. * Final Report *
  612. =========================================================================
  613. Final Results
  614. Top Level Output File Name : minsoc_top
  615. Output Format : NGC
  616. Optimization Goal : Speed
  617. Keep Hierarchy : no
  618.  
  619. Design Statistics
  620. # IOs : 4
  621.  
  622. Cell Usage :
  623. # BELS : 531
  624. # GND : 1
  625. # LUT2 : 4
  626. # LUT2_L : 1
  627. # LUT3 : 142
  628. # LUT3_L : 1
  629. # LUT4 : 316
  630. # LUT4_D : 10
  631. # LUT4_L : 18
  632. # MUXF5 : 38
  633. # FlipFlops/Latches : 11
  634. # FD : 1
  635. # FDC : 7
  636. # FDC_1 : 1
  637. # FDCP_1 : 1
  638. # FDP : 1
  639. # RAMS : 16
  640. # RAMB16_S9 : 16
  641. # Clock Buffers : 2
  642. # BUFG : 2
  643. # IO Buffers : 4
  644. # IBUF : 2
  645. # IBUFG : 1
  646. # OBUF : 1
  647. # DCMs : 1
  648. # DCM_SP : 1
  649. # Others : 4
  650. # adbg_top : 1
  651. # BSCAN_SPARTAN3 : 1
  652. # or1200_top : 1
  653. # uart_top : 1
  654. =========================================================================
  655.  
  656. Device utilization summary:
  657. ---------------------------
  658.  
  659. Selected Device : 3s500efg320-4
  660.  
  661. Number of Slices: 270 out of 4656 5%
  662. Number of Slice Flip Flops: 11 out of 9312 0%
  663. Number of 4 input LUTs: 492 out of 9312 5%
  664. Number of IOs: 4
  665. Number of bonded IOBs: 4 out of 232 1%
  666. Number of BRAMs: 16 out of 20 80%
  667. Number of GCLKs: 2 out of 24 8%
  668. Number of DCMs: 1 out of 4 25%
  669.  
  670. ---------------------------
  671. Partition Resource Summary:
  672. ---------------------------
  673.  
  674. No Partitions were found in this design.
  675.  
  676. ---------------------------
  677.  
  678.  
  679. =========================================================================
  680. TIMING REPORT
  681.  
  682. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  683. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  684. GENERATED AFTER PLACE-and-ROUTE.
  685.  
  686. Clock Information:
  687. ------------------
  688. -----------------------------------+-----------------------------------------------+-------+
  689. Clock Signal | Clock buffer(FF name) | Load |
  690. -----------------------------------+-----------------------------------------------+-------+
  691. clk | clk_adjust/minsoc_xilinx_dcm/DCM_SP_inst:CLKDV| 26 |
  692. debug_select | NONE(tap_top/update_out) | 1 |
  693. -----------------------------------+-----------------------------------------------+-------+
  694. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
  695.  
  696. Asynchronous Control Signals Information:
  697. ----------------------------------------
  698. ---------------------------------------------------------+----------------------------+-------+
  699. Control Signal | Buffer(FF name) | Load |
  700. ---------------------------------------------------------+----------------------------+-------+
  701. wb_rst(wb_rst:Q) | NONE(onchip_ram_top/ack_re)| 8 |
  702. reset | IBUF | 1 |
  703. tap_top/update_bscan(tap_top/BSCAN_SPARTAN3_inst:UPDATE) | NONE(tap_top/update_out) | 1 |
  704. tap_top/update_out_and0000(tap_top/update_out_and00001:O)| NONE(tap_top/update_out) | 1 |
  705. ---------------------------------------------------------+----------------------------+-------+
  706.  
  707. Timing Summary:
  708. ---------------
  709. Speed Grade: -4
  710.  
  711. Minimum period: 6.991ns (Maximum Frequency: 143.039MHz)
  712. Minimum input arrival time before clock: 14.341ns
  713. Maximum output required time after clock: 16.141ns
  714. Maximum combinational path delay: 18.317ns
  715.  
  716. Timing Detail:
  717. --------------
  718. All values displayed in nanoseconds (ns)
  719.  
  720. =========================================================================
  721. Timing constraint: Default period analysis for Clock 'clk'
  722. Clock period: 6.991ns (frequency: 143.039MHz)
  723. Total number of paths / destination ports: 5702 / 361
  724. -------------------------------------------------------------------------
  725. Delay: 6.991ns (Levels of Logic = 4)
  726. Source: tc_top/t0_ch/req_r_3 (FF)
  727. Destination: onchip_ram_top/ack_we (FF)
  728. Source Clock: clk rising 0.5X
  729. Destination Clock: clk falling 0.5X
  730.  
  731. Data Path: tc_top/t0_ch/req_r_3 to onchip_ram_top/ack_we
  732. Gate Net
  733. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  734. ---------------------------------------- ------------
  735. FDC:C->Q 5 0.591 0.712 tc_top/t0_ch/req_r_3 (tc_top/t0_ch/req_r_3)
  736. LUT4_D:I1->O 5 0.704 0.637 tc_top/t0_ch/req_cont_SW0 (N188)
  737. LUT4:I3->O 95 0.704 1.317 tc_top/t0_ch/req_won<5> (tc_top/t0_ch/req_won<5>)
  738. LUT3:I2->O 3 0.704 0.610 tc_top/t0_ch/t0_out<32> (wb_ss_we_i)
  739. LUT3:I1->O 1 0.704 0.000 onchip_ram_top/ack_we_and00001 (onchip_ram_top/ack_we_and0000)
  740. FDC_1:D 0.308 onchip_ram_top/ack_we
  741. ----------------------------------------
  742. Total 6.991ns (3.715ns logic, 3.276ns route)
  743. (53.1% logic, 46.9% route)
  744.  
  745. =========================================================================
  746. Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  747. Total number of paths / destination ports: 61362 / 344
  748. -------------------------------------------------------------------------
  749. Offset: 14.341ns (Levels of Logic = 10)
  750. Source: dbg_top:wb_adr_o<24> (PAD)
  751. Destination: onchip_ram_top/MEM[0].block_ram_0/ramb16_s9 (RAM)
  752. Destination Clock: clk rising 0.5X
  753.  
  754. Data Path: dbg_top:wb_adr_o<24> to onchip_ram_top/MEM[0].block_ram_0/ramb16_s9
  755. Gate Net
  756. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  757. ---------------------------------------- ------------
  758. adbg_top:wb_adr_o<24> 3 0.000 0.706 dbg_top (wb_dm_adr_o<24>)
  759. LUT4:I0->O 1 0.704 0.000 tc_top/t0_ch/req_i_3_and0000161 (tc_top/t0_ch/req_i_3_and0000161)
  760. MUXF5:I1->O 3 0.321 0.706 tc_top/t0_ch/req_i_3_and000016_f5 (tc_top/t0_ch/req_i_3_and000016)
  761. LUT2:I0->O 4 0.704 0.762 tc_top/t0_ch/req_i_3_and000032 (tc_top/t0_ch/req_i<3>)
  762. LUT4_D:I0->O 5 0.704 0.637 tc_top/t0_ch/req_cont_SW0 (N188)
  763. LUT4:I3->O 95 0.704 1.286 tc_top/t0_ch/req_won<5> (tc_top/t0_ch/req_won<5>)
  764. LUT4:I3->O 2 0.704 0.482 tc_top/t0_ch/t0_out<35>_SW0_SW0 (N235)
  765. LUT3_L:I2->LO 1 0.704 0.275 tc_top/t0_ch/t0_out<35> (wb_ss_sel_i<2>)
  766. LUT3:I0->O 1 0.704 0.424 onchip_ram_top/we_SW0 (N190)
  767. LUT4_D:I3->O 3 0.704 0.566 onchip_ram_top/we (onchip_ram_top/we)
  768. LUT3:I2->O 4 0.704 0.587 onchip_ram_top/_and00021 (onchip_ram_top/_and0002)
  769. RAMB16_S9:WE 1.253 onchip_ram_top/MEM[2].block_ram_0/ramb16_s9
  770. ----------------------------------------
  771. Total 14.341ns (7.910ns logic, 6.431ns route)
  772. (55.2% logic, 44.8% route)
  773.  
  774. =========================================================================
  775. Timing constraint: Default OFFSET OUT AFTER for Clock 'debug_select'
  776. Total number of paths / destination ports: 1 / 1
  777. -------------------------------------------------------------------------
  778. Offset: 0.591ns (Levels of Logic = 0)
  779. Source: tap_top/update_out (FF)
  780. Destination: dbg_top:update_dr_i (PAD)
  781. Source Clock: debug_select falling
  782.  
  783. Data Path: tap_top/update_out to dbg_top:update_dr_i
  784. Gate Net
  785. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  786. ---------------------------------------- ------------
  787. FDCP_1:C->Q 0 0.591 0.000 tap_top/update_out (tap_top/update_out)
  788. adbg_top:update_dr_i 0.000 dbg_top
  789. ----------------------------------------
  790. Total 0.591ns (0.591ns logic, 0.000ns route)
  791. (100.0% logic, 0.0% route)
  792.  
  793. =========================================================================
  794. Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  795. Total number of paths / destination ports: 116799 / 150
  796. -------------------------------------------------------------------------
  797. Offset: 16.141ns (Levels of Logic = 13)
  798. Source: tc_top/t18_ch_upper/req_r_3 (FF)
  799. Destination: dbg_top:wb_ack_i (PAD)
  800. Source Clock: clk rising 0.5X
  801.  
  802. Data Path: tc_top/t18_ch_upper/req_r_3 to dbg_top:wb_ack_i
  803. Gate Net
  804. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  805. ---------------------------------------- ------------
  806. FDC:C->Q 3 0.591 0.610 tc_top/t18_ch_upper/req_r_3 (tc_top/t18_ch_upper/req_r_3)
  807. LUT4:I1->O 5 0.704 0.808 tc_top/t18_ch_upper/req_cont_SW0 (N216)
  808. LUT4:I0->O 1 0.704 0.000 tc_top/t18_ch_upper/req_won<3>11 (tc_top/t18_ch_upper/req_won<3>1)
  809. MUXF5:I1->O 87 0.321 1.455 tc_top/t18_ch_upper/req_won<3>1_f5 (tc_top/t18_ch_upper/req_won<3>)
  810. LUT4:I0->O 1 0.704 0.595 tc_top/t18_ch_upper/t0_out<66>_SW0 (N200)
  811. LUT3:I0->O 2 0.704 0.451 tc_top/t18_ch_upper/t0_out<66> (tc_top/z_wb_adr_i<29>)
  812. LUT4:I3->O 1 0.704 0.455 tc_top/t18_ch_lower/req_t_1_and00001_SW0 (N210)
  813. LUT4:I2->O 4 0.704 0.666 tc_top/t18_ch_lower/req_t_1_and00001 (tc_top/t18_ch_lower/N2)
  814. LUT4:I1->O 1 0.704 0.000 tc_top/t18_ch_lower/i0_out<10>1158_F (N321)
  815. MUXF5:I0->O 3 0.321 0.706 tc_top/t18_ch_lower/i0_out<10>1158 (tc_top/t18_ch_lower/i0_out<10>1158)
  816. LUT4:I0->O 1 0.704 0.000 tc_top/t18_ch_lower/i0_out<10>11731 (tc_top/t18_ch_lower/i0_out<10>1173)
  817. MUXF5:I0->O 33 0.321 1.267 tc_top/t18_ch_lower/i0_out<10>1173_f5 (tc_top/t18_ch_lower/N6)
  818. LUT4:I3->O 3 0.704 0.535 tc_top/t18_ch_lower/i0_out<9>1 (tc_top/z_wb_dat_t<7>)
  819. LUT4:I3->O 0 0.704 0.000 tc_top/i5_wb_dat_o<7>1 (wb_rim_dat_i<7>)
  820. or1200_top:iwb_dat_i<7> 0.000 or1200_top
  821. ----------------------------------------
  822. Total 16.141ns (8.594ns logic, 7.547ns route)
  823. (53.2% logic, 46.8% route)
  824.  
  825. =========================================================================
  826. Timing constraint: Default path analysis
  827. Total number of paths / destination ports: 1134497 / 257
  828. -------------------------------------------------------------------------
  829. Delay: 18.317ns (Levels of Logic = 15)
  830. Source: dbg_top:wb_adr_o<30> (PAD)
  831. Destination: dbg_top:wb_ack_i (PAD)
  832.  
  833. Data Path: dbg_top:wb_adr_o<30> to dbg_top:wb_ack_i
  834. Gate Net
  835. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  836. ---------------------------------------- ------------
  837. adbg_top:wb_adr_o<30> 3 0.000 0.706 dbg_top (wb_dm_adr_o<30>)
  838. LUT3:I0->O 1 0.704 0.455 tc_top/t18_ch_upper/req_i_3_and000045_SW0 (N245)
  839. LUT4:I2->O 5 0.704 0.808 tc_top/t18_ch_upper/req_i_3_and000045 (tc_top/t18_ch_upper/req_i<3>)
  840. LUT4:I0->O 5 0.704 0.808 tc_top/t18_ch_upper/req_cont_SW0 (N216)
  841. LUT4:I0->O 1 0.704 0.000 tc_top/t18_ch_upper/req_won<3>11 (tc_top/t18_ch_upper/req_won<3>1)
  842. MUXF5:I1->O 87 0.321 1.455 tc_top/t18_ch_upper/req_won<3>1_f5 (tc_top/t18_ch_upper/req_won<3>)
  843. LUT4:I0->O 1 0.704 0.595 tc_top/t18_ch_upper/t0_out<66>_SW0 (N200)
  844. LUT3:I0->O 2 0.704 0.451 tc_top/t18_ch_upper/t0_out<66> (tc_top/z_wb_adr_i<29>)
  845. LUT4:I3->O 1 0.704 0.455 tc_top/t18_ch_lower/req_t_1_and00001_SW0 (N210)
  846. LUT4:I2->O 4 0.704 0.666 tc_top/t18_ch_lower/req_t_1_and00001 (tc_top/t18_ch_lower/N2)
  847. LUT4:I1->O 1 0.704 0.000 tc_top/t18_ch_lower/i0_out<10>1158_F (N321)
  848. MUXF5:I0->O 3 0.321 0.706 tc_top/t18_ch_lower/i0_out<10>1158 (tc_top/t18_ch_lower/i0_out<10>1158)
  849. LUT4:I0->O 1 0.704 0.000 tc_top/t18_ch_lower/i0_out<10>11731 (tc_top/t18_ch_lower/i0_out<10>1173)
  850. MUXF5:I0->O 33 0.321 1.267 tc_top/t18_ch_lower/i0_out<10>1173_f5 (tc_top/t18_ch_lower/N6)
  851. LUT4:I3->O 3 0.704 0.535 tc_top/t18_ch_lower/i0_out<9>1 (tc_top/z_wb_dat_t<7>)
  852. LUT4:I3->O 0 0.704 0.000 tc_top/i5_wb_dat_o<7>1 (wb_rim_dat_i<7>)
  853. or1200_top:iwb_dat_i<7> 0.000 or1200_top
  854. ----------------------------------------
  855. Total 18.317ns (9.411ns logic, 8.906ns route)
  856. (51.4% logic, 48.6% route)
  857.  
  858. =========================================================================
  859. WARNING:Xst:616 - Invalid property "aw 00000020": Did not attach to or1200_top.
  860. WARNING:Xst:616 - Invalid property "dw 00000020": Did not attach to or1200_top.
  861. WARNING:Xst:616 - Invalid property "ppic_ints 00000014": Did not attach to or1200_top.
  862. WARNING:Xst:616 - Invalid property "uart_addr_width 00000005": Did not attach to uart_top.
  863. WARNING:Xst:616 - Invalid property "uart_data_width 00000020": Did not attach to uart_top.
  864.  
  865.  
  866. Total REAL time to Xst completion: 13.00 secs
  867. Total CPU time to Xst completion: 12.48 secs
  868.  
  869. -->
  870.  
  871.  
  872. Total memory usage is 169508 kilobytes
  873.  
  874. Number of errors : 0 ( 0 filtered)
  875. Number of warnings : 75 ( 0 filtered)
  876. Number of infos : 4 ( 0 filtered)
  877.  
  878. make prepare
  879. make[1]: Entering directory `/home/aurabindo/minsoc/syn'
  880. rm -rf xst
  881. mkdir xst
  882. make[1]: Leaving directory `/home/aurabindo/minsoc/syn'
  883. xst -ifn "..//syn/buildSupport/or1200_top.xst"
  884. Release 13.2 - xst O.61xd (lin)
  885. Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
  886. -->
  887. Parameter TMPDIR set to ./xst
  888.  
  889.  
  890. Total REAL time to Xst completion: 0.00 secs
  891. Total CPU time to Xst completion: 0.07 secs
  892.  
  893. -->
  894.  
  895. TABLE OF CONTENTS
  896. 1) Synthesis Options Summary
  897. 2) HDL Compilation
  898. 3) Design Hierarchy Analysis
  899. 4) HDL Analysis
  900. 5) HDL Synthesis
  901. 5.1) HDL Synthesis Report
  902. 6) Advanced HDL Synthesis
  903. 6.1) Advanced HDL Synthesis Report
  904. 7) Low Level Synthesis
  905. 8) Partition Report
  906. 9) Final Report
  907. 9.1) Device utilization summary
  908. 9.2) Partition Resource Summary
  909. 9.3) TIMING REPORT
  910.  
  911.  
  912. =========================================================================
  913. * Synthesis Options Summary *
  914. =========================================================================
  915. ---- Source Parameters
  916. Verilog Include Directory : { "/home/aurabindo/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" }
  917. Input File Name : "/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj"
  918. Input Format : Verilog
  919.  
  920. ---- Target Parameters
  921. Output File Name : "or1200_top"
  922. Output Format : NGC
  923. Target Device : xc3s500e-4-fg320
  924.  
  925. ---- Source Options
  926. Top Module Name : or1200_top
  927.  
  928. ---- Target Options
  929. Add IO Buffers : no
  930.  
  931. ---- General Options
  932. Optimization Goal : Speed
  933. Optimization Effort : 1
  934.  
  935. =========================================================================
  936.  
  937.  
  938. =========================================================================
  939. * HDL Compilation *
  940. =========================================================================
  941. Compiling verilog file "/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj" in library work
  942. ERROR:HDLParsers:3464 - Library work mapped to physical location xst/work does not exist.
  943. ERROR:HDLCompilers:219 - Open of logical library 'work' failed
  944. Analysis of file <"/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj"> failed.
  945. -->
  946.  
  947.  
  948. Total memory usage is 147372 kilobytes
  949.  
  950. Number of errors : 2 ( 0 filtered)
  951. Number of warnings : 0 ( 0 filtered)
  952. Number of infos : 0 ( 0 filtered)
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