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  1. HEAD is now at 937d5a7... board: rename NITROKEY_LITE to NITROKEY_START
  2. root@compile:~/nitrokey-upfix/regnual# ./configure --target=NITROKEY_START --vidpid="20a0:4211"
  3. -bash: ./configure: No such file or directory
  4. root@compile:~/nitrokey-upfix/regnual# cd ../src
  5. root@compile:~/nitrokey-upfix/src# ./configure --target=NITROKEY_START --vidpid="20a0:4211"
  6. Configured for target: NITROKEY_START
  7. Debug option disabled
  8. Configured for bare system (no-DFU)
  9. PIN pad option disabled
  10. CERT.3 Data Object is NOT supported
  11. Key generation on device is NOT supported
  12. root@compile:~/nitrokey-upfix/src# make
  13.  
  14. arm-none-eabi-gcc -x assembler-with-cpp -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -Wa,-amhls=../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/crt0.lst -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/crt0.s -o ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/crt0.o
  15.  
  16. arm-none-eabi-gcc -x assembler-with-cpp -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -Wa,-amhls=../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/vectors.lst -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/vectors.s -o ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x/vectors.o
  17.  
  18. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chcore.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore.c -o ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore.o
  19.  
  20. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v7m.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chcore_v7m.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v7m.c -o ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/chcore_v7m.o
  21.  
  22. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/nvic.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/nvic.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/nvic.c -o ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/nvic.o
  23.  
  24. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/core_cm3.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.c -o ../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis/core_cm3.o
  25.  
  26. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chsys.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chsys.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chsys.c -o ../ChibiOS_2.0.8/os/kernel/src/chsys.o
  27.  
  28. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chdebug.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chdebug.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chdebug.c -o ../ChibiOS_2.0.8/os/kernel/src/chdebug.o
  29.  
  30. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chlists.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chlists.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chlists.c -o ../ChibiOS_2.0.8/os/kernel/src/chlists.o
  31.  
  32. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chvt.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chvt.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chvt.c -o ../ChibiOS_2.0.8/os/kernel/src/chvt.o
  33.  
  34. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chschd.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chschd.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chschd.c -o ../ChibiOS_2.0.8/os/kernel/src/chschd.o
  35.  
  36. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chthreads.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chthreads.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chthreads.c -o ../ChibiOS_2.0.8/os/kernel/src/chthreads.o
  37.  
  38. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chregistry.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chregistry.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chregistry.c -o ../ChibiOS_2.0.8/os/kernel/src/chregistry.o
  39.  
  40. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chsem.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chsem.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chsem.c -o ../ChibiOS_2.0.8/os/kernel/src/chsem.o
  41.  
  42. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chmtx.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chmtx.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chmtx.c -o ../ChibiOS_2.0.8/os/kernel/src/chmtx.o
  43.  
  44. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chcond.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chcond.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chcond.c -o ../ChibiOS_2.0.8/os/kernel/src/chcond.o
  45.  
  46. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chevents.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chevents.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chevents.c -o ../ChibiOS_2.0.8/os/kernel/src/chevents.o
  47.  
  48. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chmsg.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chmsg.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chmsg.c -o ../ChibiOS_2.0.8/os/kernel/src/chmsg.o
  49.  
  50. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chmboxes.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chmboxes.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chmboxes.c -o ../ChibiOS_2.0.8/os/kernel/src/chmboxes.o
  51.  
  52. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chqueues.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chqueues.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chqueues.c -o ../ChibiOS_2.0.8/os/kernel/src/chqueues.o
  53.  
  54. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chmemcore.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chmemcore.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chmemcore.c -o ../ChibiOS_2.0.8/os/kernel/src/chmemcore.o
  55.  
  56. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chheap.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chheap.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chheap.c -o ../ChibiOS_2.0.8/os/kernel/src/chheap.o
  57.  
  58. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/kernel/src/chmempools.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/chmempools.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/kernel/src/chmempools.c -o ../ChibiOS_2.0.8/os/kernel/src/chmempools.o
  59.  
  60. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/src/hal.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/hal.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/src/hal.c -o ../ChibiOS_2.0.8/os/hal/src/hal.o
  61.  
  62. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/src/adc.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/adc.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/src/adc.c -o ../ChibiOS_2.0.8/os/hal/src/adc.o
  63.  
  64. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/src/can.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/can.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/src/can.c -o ../ChibiOS_2.0.8/os/hal/src/can.o
  65.  
  66. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/src/mac.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/mac.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/src/mac.c -o ../ChibiOS_2.0.8/os/hal/src/mac.o
  67.  
  68. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/src/pal.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/pal.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/src/pal.c -o ../ChibiOS_2.0.8/os/hal/src/pal.o
  69.  
  70. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/src/pwm.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/pwm.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/src/pwm.c -o ../ChibiOS_2.0.8/os/hal/src/pwm.o
  71.  
  72. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/src/serial.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/serial.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/src/serial.c -o ../ChibiOS_2.0.8/os/hal/src/serial.o
  73.  
  74. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/src/spi.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/spi.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/src/spi.c -o ../ChibiOS_2.0.8/os/hal/src/spi.o
  75.  
  76. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/src/mmc_spi.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/mmc_spi.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/src/mmc_spi.c -o ../ChibiOS_2.0.8/os/hal/src/mmc_spi.o
  77.  
  78. arm-none-eabi-gcc -c -mcpu=cortex-m3 -mfix-cortex-m3-ldrd -O3 -Os -ggdb -fomit-frame-pointer -falign-functions=16 -ffunction-sections -fdata-sections -Wall -Wextra -Wstrict-prototypes -Wa,-alms=../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.lst -DCORTEX_USE_BASEPRI=TRUE -DTHUMB_PRESENT -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -MD -MP -MF .dep/hal_lld.o.d -mthumb -DTHUMB -I . -I../polarssl-0.14.0/include -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/STM32F10x -I../ChibiOS_2.0.8/os/ports/GCC/ARMCMx/cmsis -I../ChibiOS_2.0.8/os/kernel/include -I../ChibiOS_2.0.8/os/hal/include -I../ChibiOS_2.0.8/os/hal/platforms/STM32 -I../boards/common -I../boards/NITROKEY_START -I../ChibiOS_2.0.8/os/various ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c -o ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.o
  79. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:54:4: error: 'VAL_GPIOAODR' undeclared here (not in a function)
  80. {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
  81. ^
  82. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:54:18: error: 'VAL_GPIOACRL' undeclared here (not in a function)
  83. {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
  84. ^
  85. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:54:32: error: 'VAL_GPIOACRH' undeclared here (not in a function)
  86. {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
  87. ^
  88. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:54:3: warning: missing initializer for field 'odr' of 'stm32_gpio_setup_t' [-Wmissing-field-initializers]
  89. {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
  90. ^
  91. In file included from ../ChibiOS_2.0.8/os/hal/include/pal.h:120:0,
  92. from ../ChibiOS_2.0.8/os/hal/include/hal.h:43,
  93. from ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:36:
  94. ../ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.h:63:17: note: 'odr' declared here
  95. uint32_t odr;
  96. ^
  97. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:55:4: error: 'VAL_GPIOBODR' undeclared here (not in a function)
  98. {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
  99. ^
  100. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:55:18: error: 'VAL_GPIOBCRL' undeclared here (not in a function)
  101. {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
  102. ^
  103. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:55:32: error: 'VAL_GPIOBCRH' undeclared here (not in a function)
  104. {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
  105. ^
  106. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:55:3: warning: missing initializer for field 'odr' of 'stm32_gpio_setup_t' [-Wmissing-field-initializers]
  107. {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
  108. ^
  109. In file included from ../ChibiOS_2.0.8/os/hal/include/pal.h:120:0,
  110. from ../ChibiOS_2.0.8/os/hal/include/hal.h:43,
  111. from ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:36:
  112. ../ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.h:63:17: note: 'odr' declared here
  113. uint32_t odr;
  114. ^
  115. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:56:4: error: 'VAL_GPIOCODR' undeclared here (not in a function)
  116. {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
  117. ^
  118. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:56:18: error: 'VAL_GPIOCCRL' undeclared here (not in a function)
  119. {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
  120. ^
  121. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:56:32: error: 'VAL_GPIOCCRH' undeclared here (not in a function)
  122. {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
  123. ^
  124. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:56:3: warning: missing initializer for field 'odr' of 'stm32_gpio_setup_t' [-Wmissing-field-initializers]
  125. {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
  126. ^
  127. In file included from ../ChibiOS_2.0.8/os/hal/include/pal.h:120:0,
  128. from ../ChibiOS_2.0.8/os/hal/include/hal.h:43,
  129. from ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:36:
  130. ../ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.h:63:17: note: 'odr' declared here
  131. uint32_t odr;
  132. ^
  133. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:57:4: error: 'VAL_GPIODODR' undeclared here (not in a function)
  134. {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
  135. ^
  136. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:57:18: error: 'VAL_GPIODCRL' undeclared here (not in a function)
  137. {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
  138. ^
  139. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:57:32: error: 'VAL_GPIODCRH' undeclared here (not in a function)
  140. {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
  141. ^
  142. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:57:3: warning: missing initializer for field 'odr' of 'stm32_gpio_setup_t' [-Wmissing-field-initializers]
  143. {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
  144. ^
  145. In file included from ../ChibiOS_2.0.8/os/hal/include/pal.h:120:0,
  146. from ../ChibiOS_2.0.8/os/hal/include/hal.h:43,
  147. from ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:36:
  148. ../ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.h:63:17: note: 'odr' declared here
  149. uint32_t odr;
  150. ^
  151. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:59:4: error: 'VAL_GPIOEODR' undeclared here (not in a function)
  152. {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
  153. ^
  154. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:59:18: error: 'VAL_GPIOECRL' undeclared here (not in a function)
  155. {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
  156. ^
  157. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:59:32: error: 'VAL_GPIOECRH' undeclared here (not in a function)
  158. {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
  159. ^
  160. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:59:3: warning: missing initializer for field 'odr' of 'stm32_gpio_setup_t' [-Wmissing-field-initializers]
  161. {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
  162. ^
  163. In file included from ../ChibiOS_2.0.8/os/hal/include/pal.h:120:0,
  164. from ../ChibiOS_2.0.8/os/hal/include/hal.h:43,
  165. from ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:36:
  166. ../ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.h:63:17: note: 'odr' declared here
  167. uint32_t odr;
  168. ^
  169. ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:65:1: warning: missing initializer for field 'PAData' of 'PALConfig' [-Wmissing-field-initializers]
  170. };
  171. ^
  172. In file included from ../ChibiOS_2.0.8/os/hal/include/pal.h:120:0,
  173. from ../ChibiOS_2.0.8/os/hal/include/hal.h:43,
  174. from ../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.c:36:
  175. ../ChibiOS_2.0.8/os/hal/platforms/STM32/pal_lld.h:79:25: note: 'PAData' declared here
  176. stm32_gpio_setup_t PAData;
  177. ^
  178. ../ChibiOS_2.0.8/os/ports/GCC/ARM/rules.mk:115: recipe for target '../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.o' failed
  179. make: *** [../ChibiOS_2.0.8/os/hal/platforms/STM32/hal_lld.o] Error 1
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