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Feb 8th, 2016
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VHDL 0.17 KB | None | 0 0
  1.  
  2. entity Not1 is
  3.     Port ( a : in  STD_LOGIC;
  4.            z : out  STD_LOGIC);
  5. end Not1;
  6.  
  7. architecture Behavioral of Not1 is
  8.  
  9. begin
  10.  
  11. z <= not a;
  12.  
  13. end Behavioral;
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