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By: a guest on Apr 29th, 2012  |  syntax: None  |  size: 2.94 KB  |  views: 39  |  expires: Never
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  1. #ifndef _SPU_H_
  2. #define _SPU_H_
  3.  
  4. #include "types.h"
  5. #include "netrpc.h"
  6.  
  7. /*! SPU privlege 1 registers. (u64) */
  8. #define _OFFSET_MFC_SR1 0x0000
  9. #define _OFFSET_INT_Stat_class0 0x0140
  10. #define _OFFSET_INT_Stat_class1 0x0148
  11. #define _OFFSET_INT_Stat_class2 0x0150
  12. #define _OFFSET_MFC_DSISR 0x0610
  13. #define _OFFSET_MFC_DAR 0x0620
  14. #define _OFFSET_MFC_DSIPR 0x0800
  15. #define _OFFSET_MFC_LSCRR 0x0810
  16. #define _OFFSET_MFC_CER 0x0c00
  17. #define _OFFSET_EXECUTION_STATUS 0x0f00
  18. #define _OFFSET_TRANSITION_NOTIFIER 0x0f10
  19.  
  20. /*! SPU privlege 2 registers. (u64) */
  21. #define _OFFSET_SLB_Index 0x1108
  22. #define _OFFSET_SLB_ESID 0x1110
  23. #define _OFFSET_SLB_VSID 0x1118
  24. #define _OFFSET_SLB_Invalidate_Entry 0x1120
  25. #define _OFFSET_SLB_Invalidate_All 0x1128
  26. #define _OFFSET_SPU_OutIntrMbox 0x4000
  27. #define _OFFSET_SPU_PrivCntl 0x4040
  28. #define _OFFSET_SPU_ChnlIndex 0x4060
  29. #define _OFFSET_SPU_ChnlCnt 0x4068
  30. #define _OFFSET_SPU_ChnlData 0x4070
  31. #define _OFFSET_SPU_Cfg 0x4078
  32.  
  33. /*! SPU problem registers. (u32) */
  34. #define _OFFSET_MFC_LSA 0x3004
  35. #define _OFFSET_MFC_EAH 0x3008
  36. #define _OFFSET_MFC_EAL 0x300c
  37. #define _OFFSET_MFC_Size 0x3010
  38. #define _OFFSET_MFC_Tag 0x3010
  39. #define _OFFSET_MFC_ClassID_CMD 0x3014
  40. #define _OFFSET_MFC_CMDStatus 0x3014
  41. #define _OFFSET_MFC_QStatus 0x3104
  42. #define _OFFSET_Prxy_QueryType 0x3204
  43. #define _OFFSET_Prxy_QueryMask 0x321c
  44. #define _OFFSET_Prxy_TagStatus 0x322c
  45. #define _OFFSET_SPU_Out_Mbox 0x4004
  46. #define _OFFSET_SPU_In_Mbox 0x400c
  47. #define _OFFSET_SPU_Mbox_Stat 0x4014
  48. #define _OFFSET_SPU_RunCntl 0x401c
  49. #define _OFFSET_SPU_Status 0x4024
  50. #define _OFFSET_SPU_NPC 0x4034
  51. #define _OFFSET_SPU_Sig_Notify_1 0x1400c
  52. #define _OFFSET_SPU_Sig_Notify_2 0x1c00c
  53.  
  54. /*! Register adress macros. */
  55. #define SPU_RADDR(base, offset) (base + offset)
  56.  
  57. /*! Max. SPU SLB entries. */
  58. #define SPU_SLB_MAX_ENTRIES 8
  59.  
  60. /*! SPU_RunCntl values. */
  61. #define SPU_RunCntl_STOP_REQ 0x0
  62. #define SPU_RunCntl_RUN_REQ 0x1
  63. #define SPU_RunCntl_ISOLATION_EXIT_REQ 0x2
  64. #define SPU_RunCntl_ISOLATION_REQ 0x3
  65.  
  66. void spu_slb_invalidate_all(netrpc_ctxt_t *ctxt, u64 spu_priv2);
  67. s32 spu_slb_set_entry(netrpc_ctxt_t *ctxt, u64 spu_priv2, u64 index, u64 esid, u64 vsid);
  68. void spu_in_mbox_write(netrpc_ctxt_t *ctxt, u64 spu_problem, u32 val);
  69. void spu_in_mbox_write_64(netrpc_ctxt_t *ctxt, u64 spu_problem, u64 val);
  70. void spu_sig_notify_1_2_write_64(netrpc_ctxt_t *ctxt, u64 spu_problem, u64 val);
  71. void spu_isolation_req_enable(netrpc_ctxt_t *ctxt, u64 spu_priv2);
  72. void spu_isolation_req(netrpc_ctxt_t *ctxt, u64 spu_problem);
  73. void spu_stop_req(netrpc_ctxt_t *ctxt, u64 spu_problem);
  74. void spu_runcntl_req(netrpc_ctxt_t *ctxt, u64 spu_problem, u32 req);
  75. u8 spu_mbox_stat_intr_out_mbox_count(netrpc_ctxt_t *ctxt, u64 spu_problem);
  76. u8 spu_mbox_stat_in_mbox_count(netrpc_ctxt_t *ctxt, u64 spu_problem);
  77. u8 spu_mbox_stat_out_mbox_count(netrpc_ctxt_t *ctxt, u64 spu_problem);
  78. u8 spu_mfc_cmd_exec(netrpc_ctxt_t *ctxt, u64 spu_problem, u32 lsa, u64 ea, u16 size, u16 tag, u16 classid, u16 cmd);
  79. u8 spu_mfc_cmd_tag_status(netrpc_ctxt_t *ctxt, u64 spu_problem, u8 tag);
  80.  
  81. #endif
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