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tinymembench on Orange Pi PC with 4.6.0-rc1

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Apr 8th, 2016
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  1. tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
  2.  
  3. ==========================================================================
  4. == Memory bandwidth tests ==
  5. == ==
  6. == Note 1: 1MB = 1000000 bytes ==
  7. == Note 2: Results for 'copy' tests show how many bytes can be ==
  8. == copied per second (adding together read and writen ==
  9. == bytes would have provided twice higher numbers) ==
  10. == Note 3: 2-pass copy means that we are using a small temporary buffer ==
  11. == to first fetch data into it, and only then write it to the ==
  12. == destination (source -> L1 cache, L1 cache -> destination) ==
  13. == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
  14. == brackets ==
  15. ==========================================================================
  16.  
  17. C copy backwards : 267.2 MB/s
  18. C copy backwards (32 byte blocks) : 1030.5 MB/s
  19. C copy backwards (64 byte blocks) : 977.2 MB/s
  20. C copy : 958.0 MB/s
  21. C copy prefetched (32 bytes step) : 875.4 MB/s
  22. C copy prefetched (64 bytes step) : 988.5 MB/s
  23. C 2-pass copy : 728.3 MB/s
  24. C 2-pass copy prefetched (32 bytes step) : 698.6 MB/s
  25. C 2-pass copy prefetched (64 bytes step) : 727.6 MB/s
  26. C fill : 3351.5 MB/s (0.1%)
  27. C fill (shuffle within 16 byte blocks) : 3337.1 MB/s
  28. C fill (shuffle within 32 byte blocks) : 339.8 MB/s
  29. C fill (shuffle within 64 byte blocks) : 345.5 MB/s
  30. ---
  31. standard memcpy : 986.4 MB/s (0.1%)
  32. standard memset : 2552.1 MB/s
  33. ---
  34. NEON read : 1275.5 MB/s
  35. NEON read prefetched (32 bytes step) : 1402.5 MB/s
  36. NEON read prefetched (64 bytes step) : 1451.8 MB/s
  37. NEON read 2 data streams : 359.6 MB/s
  38. NEON read 2 data streams prefetched (32 bytes step) : 686.1 MB/s
  39. NEON read 2 data streams prefetched (64 bytes step) : 735.2 MB/s
  40. NEON copy : 978.5 MB/s
  41. NEON copy prefetched (32 bytes step) : 1060.0 MB/s
  42. NEON copy prefetched (64 bytes step) : 1129.4 MB/s
  43. NEON unrolled copy : 1066.0 MB/s
  44. NEON unrolled copy prefetched (32 bytes step) : 933.3 MB/s
  45. NEON unrolled copy prefetched (64 bytes step) : 1059.3 MB/s
  46. NEON copy backwards : 1041.5 MB/s
  47. NEON copy backwards prefetched (32 bytes step) : 1041.2 MB/s
  48. NEON copy backwards prefetched (64 bytes step) : 1074.2 MB/s
  49. NEON 2-pass copy : 814.4 MB/s
  50. NEON 2-pass copy prefetched (32 bytes step) : 884.2 MB/s
  51. NEON 2-pass copy prefetched (64 bytes step) : 906.5 MB/s
  52. NEON unrolled 2-pass copy : 707.5 MB/s
  53. NEON unrolled 2-pass copy prefetched (32 bytes step) : 668.3 MB/s
  54. NEON unrolled 2-pass copy prefetched (64 bytes step) : 707.3 MB/s
  55. NEON fill : 3355.7 MB/s (0.2%)
  56. NEON fill backwards : 3335.6 MB/s
  57. VFP copy : 1070.8 MB/s
  58. VFP 2-pass copy : 719.4 MB/s
  59. ARM fill (STRD) : 2552.5 MB/s
  60. ARM fill (STM with 8 registers) : 3339.0 MB/s
  61. ARM fill (STM with 4 registers) : 3021.9 MB/s
  62. ARM copy prefetched (incr pld) : 1093.1 MB/s
  63. ARM copy prefetched (wrap pld) : 1066.5 MB/s
  64. ARM 2-pass copy prefetched (incr pld) : 791.2 MB/s
  65. ARM 2-pass copy prefetched (wrap pld) : 776.5 MB/s
  66.  
  67. ==========================================================================
  68. == Memory latency test ==
  69. == ==
  70. == Average time is measured for random memory accesses in the buffers ==
  71. == of different sizes. The larger is the buffer, the more significant ==
  72. == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
  73. == accesses. For extremely large buffer sizes we are expecting to see ==
  74. == page table walk with several requests to SDRAM for almost every ==
  75. == memory access (though 64MiB is not nearly large enough to experience ==
  76. == this effect to its fullest). ==
  77. == ==
  78. == Note 1: All the numbers are representing extra time, which needs to ==
  79. == be added to L1 cache latency. The cycle timings for L1 cache ==
  80. == latency can be usually found in the processor documentation. ==
  81. == Note 2: Dual random read means that we are simultaneously performing ==
  82. == two independent memory accesses at a time. In the case if ==
  83. == the memory subsystem can't handle multiple outstanding ==
  84. == requests, dual random read has the same timings as two ==
  85. == single reads performed one after another. ==
  86. ==========================================================================
  87.  
  88. block size : single random read / dual random read
  89. 1024 : 0.0 ns / 0.0 ns
  90. 2048 : 0.0 ns / 0.0 ns
  91. 4096 : 0.0 ns / 0.0 ns
  92. 8192 : 0.0 ns / 0.0 ns
  93. 16384 : 0.0 ns / 0.0 ns
  94. 32768 : 0.0 ns / 0.0 ns
  95. 65536 : 6.2 ns / 10.8 ns
  96. 131072 : 9.6 ns / 15.1 ns
  97. 262144 : 11.3 ns / 16.7 ns
  98. 524288 : 13.5 ns / 19.0 ns
  99. 1048576 : 89.2 ns / 137.4 ns
  100. 2097152 : 134.0 ns / 181.2 ns
  101. 4194304 : 157.1 ns / 197.1 ns
  102. 8388608 : 170.7 ns / 206.4 ns
  103. 16777216 : 180.4 ns / 215.2 ns
  104. 33554432 : 191.0 ns / 230.2 ns
  105. 67108864 : 204.3 ns / 254.3 ns
  106.  
  107.  
  108.  
  109.  
  110. root@orangepipc:/usr/local/src/tinymembench# cat /proc/cpuinfo
  111. processor : 0
  112. model name : ARMv7 Processor rev 5 (v7l)
  113. BogoMIPS : 48.00
  114. Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  115. CPU implementer : 0x41
  116. CPU architecture: 7
  117. CPU variant : 0x0
  118. CPU part : 0xc07
  119. CPU revision : 5
  120.  
  121. processor : 1
  122. model name : ARMv7 Processor rev 5 (v7l)
  123. BogoMIPS : 48.00
  124. Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  125. CPU implementer : 0x41
  126. CPU architecture: 7
  127. CPU variant : 0x0
  128. CPU part : 0xc07
  129. CPU revision : 5
  130.  
  131. processor : 2
  132. model name : ARMv7 Processor rev 5 (v7l)
  133. BogoMIPS : 48.00
  134. Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  135. CPU implementer : 0x41
  136. CPU architecture: 7
  137. CPU variant : 0x0
  138. CPU part : 0xc07
  139. CPU revision : 5
  140.  
  141. processor : 3
  142. model name : ARMv7 Processor rev 5 (v7l)
  143. BogoMIPS : 48.00
  144. Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  145. CPU implementer : 0x41
  146. CPU architecture: 7
  147. CPU variant : 0x0
  148. CPU part : 0xc07
  149. CPU revision : 5
  150.  
  151. Hardware : Allwinner sun8i Family
  152. Revision : 0000
  153. Serial : 0200462044000000
  154. root@orangepipc:/usr/local/src/tinymembench# uname -a
  155. Linux orangepipc 4.6.0-rc1-sunxi #10 SMP Sat Apr 2 16:19:47 CEST 2016 armv7l GNU/Linux
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