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Feb 8th, 2016
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VHDL 0.22 KB | None | 0 0
  1.  
  2. entity Nand2 is
  3.     Port ( a : in  STD_LOGIC;
  4.            b : in  STD_LOGIC;
  5.            z : out  STD_LOGIC);
  6. end Nand2;
  7.  
  8. architecture Behavioral of Nand2 is
  9.  
  10. begin
  11. z <= not(a and b);
  12. -- z<=a nand b;
  13.  
  14. end Behavioral;
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