API tools faq
paste
Advertisement
Guest User

Untitled

a guest
Apr 16th, 2014
290
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
Diff 12.02 KB | None | 0 0
raw download clone embed print report
  1. diff -r d30cffa47f75 src/mem/protocol/MESI_CMP_directory-L1cache.sm
  2. --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm    Tue Apr 15 14:37:21 2014 -0400
  3. +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm    Wed Apr 16 11:04:00 2014 -0400
  4. @@ -496,61 +496,67 @@
  5.    action(a_issueGETS, "a", desc="Issue GETS") {
  6.      peek(mandatoryQueue_in, RubyRequest) {
  7.        enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
  8.          out_msg.Addr := address;
  9.          out_msg.Type := CoherenceRequestType:GETS;
  10.          out_msg.Requestor := machineID;
  11.          out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
  12.                                                    l2_select_low_bit, l2_select_num_bits));
  13.          DPRINTF(RubySlicc, "address: %s, destination: %s\n",
  14.                  address, out_msg.Destination);
  15.          out_msg.MessageSize := MessageSizeType:Control;
  16.          out_msg.Prefetch := in_msg.Prefetch;
  17.          out_msg.AccessMode := in_msg.AccessMode;
  18. +        out_msg.ProgramCounter := in_msg.ProgramCounter;
  19. +        out_msg.ThreadId := in_msg.contextId;
  20.        }
  21.      }
  22.    }
  23.  
  24.    action(pa_issuePfGETS, "pa", desc="Issue prefetch GETS") {
  25.      peek(optionalQueue_in, RubyRequest) {
  26.        enqueue(requestIntraChipL1Network_out, RequestMsg,
  27.                latency=l1_request_latency) {
  28.          out_msg.Addr := address;
  29.          out_msg.Type := CoherenceRequestType:GETS;
  30.          out_msg.Requestor := machineID;
  31.          out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
  32.                                        l2_select_low_bit, l2_select_num_bits));
  33.          DPRINTF(RubySlicc, "address: %s, destination: %s\n",
  34.                  address, out_msg.Destination);
  35.          out_msg.MessageSize := MessageSizeType:Control;
  36.          out_msg.Prefetch := in_msg.Prefetch;
  37.          out_msg.AccessMode := in_msg.AccessMode;
  38. +        out_msg.ProgramCounter := in_msg.ProgramCounter;
  39. +        out_msg.ThreadId := in_msg.contextId;
  40.        }
  41.      }
  42.    }
  43.  
  44.    action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
  45.      peek(mandatoryQueue_in, RubyRequest) {
  46.        enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
  47.          out_msg.Addr := address;
  48.          out_msg.Type := CoherenceRequestType:GET_INSTR;
  49.          out_msg.Requestor := machineID;
  50.          out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
  51.                                                    l2_select_low_bit, l2_select_num_bits));
  52.          DPRINTF(RubySlicc, "address: %s, destination: %s\n",
  53.                  address, out_msg.Destination);
  54.          out_msg.MessageSize := MessageSizeType:Control;
  55.          out_msg.Prefetch := in_msg.Prefetch;
  56.          out_msg.AccessMode := in_msg.AccessMode;
  57. +        out_msg.ProgramCounter := in_msg.ProgramCounter;
  58. +        out_msg.ThreadId := in_msg.contextId;
  59.        }
  60.      }
  61.    }
  62.  
  63.    action(pai_issuePfGETINSTR, "pai",
  64.           desc="Issue GETINSTR for prefetch request") {
  65.        peek(optionalQueue_in, RubyRequest) {
  66.            enqueue(requestIntraChipL1Network_out, RequestMsg,
  67.                    latency=l1_request_latency) {
  68.                out_msg.Addr := address;
  69.                out_msg.Type := CoherenceRequestType:GET_INSTR;
  70.                out_msg.Requestor := machineID;
  71.                out_msg.Destination.add(
  72. @@ -570,26 +576,28 @@
  73.      peek(mandatoryQueue_in, RubyRequest) {
  74.        enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
  75.          out_msg.Addr := address;
  76.          out_msg.Type := CoherenceRequestType:GETX;
  77.          out_msg.Requestor := machineID;
  78.          DPRINTF(RubySlicc, "%s\n", machineID);
  79.          out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
  80.                                                    l2_select_low_bit, l2_select_num_bits));
  81.          DPRINTF(RubySlicc, "address: %s, destination: %s\n",
  82.                  address, out_msg.Destination);
  83.          out_msg.MessageSize := MessageSizeType:Control;
  84.          out_msg.Prefetch := in_msg.Prefetch;
  85.          out_msg.AccessMode := in_msg.AccessMode;
  86. +        out_msg.ProgramCounter := in_msg.ProgramCounter;
  87. +        out_msg.ThreadId := in_msg.contextId;
  88.        }
  89.      }
  90.    }
  91.  
  92.    action(pb_issuePfGETX, "pb", desc="Issue prefetch GETX") {
  93.        peek(optionalQueue_in, RubyRequest) {
  94.            enqueue(requestIntraChipL1Network_out, RequestMsg,
  95.                    latency=l1_request_latency) {
  96.                out_msg.Addr := address;
  97.                out_msg.Type := CoherenceRequestType:GETX;
  98.                out_msg.Requestor := machineID;
  99.                DPRINTF(RubySlicc, "%s\n", machineID);
  100.  
  101. diff -r d30cffa47f75 src/mem/protocol/MESI_CMP_directory-L2cache.sm
  102. --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm    Tue Apr 15 14:37:21 2014 -0400
  103. +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm    Wed Apr 16 11:04:00 2014 -0400
  104. @@ -394,39 +394,43 @@
  105.    }
  106.  
  107.  
  108.    // ACTIONS
  109.  
  110.    action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
  111.      peek(L1RequestIntraChipL2Network_in, RequestMsg) {
  112.        enqueue(DirRequestIntraChipL2Network_out, RequestMsg, latency=l2_request_latency) {
  113.          out_msg.Addr := address;
  114.          out_msg.Type := CoherenceRequestType:GETS;
  115.          out_msg.Requestor := machineID;
  116.          out_msg.Destination.add(map_Address_to_Directory(address));
  117.          out_msg.MessageSize := MessageSizeType:Control;
  118. +        out_msg.ProgramCounter := in_msg.ProgramCounter;
  119. +        out_msg.ThreadId := in_msg.ThreadId;
  120.        }
  121.      }
  122.    }
  123.  
  124.    action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
  125.      peek(L1RequestIntraChipL2Network_in, RequestMsg) {
  126.        enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
  127.          assert(is_valid(cache_entry));
  128.          out_msg.Addr := address;
  129.          out_msg.Type := in_msg.Type;
  130.          out_msg.Requestor := in_msg.Requestor;
  131.          out_msg.Destination.add(cache_entry.Exclusive);
  132.          out_msg.MessageSize := MessageSizeType:Request_Control;
  133. +        out_msg.ProgramCounter := in_msg.ProgramCounter;
  134. +        out_msg.ThreadId := in_msg.ThreadId;
  135.        }
  136.      }
  137.    }
  138.  
  139.    action(c_exclusiveReplacement, "c", desc="Send data to memory") {
  140.      enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
  141.        assert(is_valid(cache_entry));
  142.        out_msg.Addr := address;
  143.        out_msg.Type := CoherenceResponseType:MEMORY_DATA;
  144.        out_msg.Sender := machineID;
  145.        out_msg.Destination.add(map_Address_to_Directory(address));
  146.        out_msg.DataBlk := cache_entry.DataBlk;
  147.        out_msg.Dirty := cache_entry.Dirty;
  148. diff -r d30cffa47f75 src/mem/protocol/MESI_CMP_directory-dir.sm
  149. --- a/src/mem/protocol/MESI_CMP_directory-dir.sm    Tue Apr 15 14:37:21 2014 -0400
  150. +++ b/src/mem/protocol/MESI_CMP_directory-dir.sm    Wed Apr 16 11:04:00 2014 -0400
  151. @@ -305,26 +305,28 @@
  152.      wakeUpBuffers(address);
  153.    }
  154.  
  155.    action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
  156.      peek(requestNetwork_in, RequestMsg) {
  157.        enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
  158.          out_msg.Addr := address;
  159.          out_msg.Type := MemoryRequestType:MEMORY_READ;
  160.          out_msg.Sender := machineID;
  161.          out_msg.OriginalRequestorMachId := in_msg.Requestor;
  162.          out_msg.MessageSize := in_msg.MessageSize;
  163.          out_msg.Prefetch := in_msg.Prefetch;
  164.          out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
  165. +        out_msg.ProgramCounter := in_msg.ProgramCounter;
  166. +        out_msg.ThreadId := in_msg.ThreadId;
  167.  
  168.          DPRINTF(RubySlicc, "%s\n", out_msg);
  169.        }
  170.      }
  171.    }
  172.  
  173.    action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
  174.      peek(responseNetwork_in, ResponseMsg) {
  175.        enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
  176.          out_msg.Addr := address;
  177.          out_msg.Type := MemoryRequestType:MEMORY_WB;
  178.          out_msg.Sender := machineID;
  179.          out_msg.OriginalRequestorMachId := in_msg.Sender;
  180. @@ -344,26 +346,28 @@
  181.                in_msg.Addr, in_msg.DataBlk);
  182.      }
  183.    }
  184.  //added by SS for dma
  185.    action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
  186.      peek(requestNetwork_in, RequestMsg) {
  187.        enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
  188.          out_msg.Addr := address;
  189.          out_msg.Type := MemoryRequestType:MEMORY_READ;
  190.          out_msg.Sender := machineID;
  191.          out_msg.OriginalRequestorMachId := machineID;
  192.          out_msg.MessageSize := in_msg.MessageSize;
  193.          out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
  194. +        out_msg.ProgramCounter := in_msg.ProgramCounter;
  195. +        out_msg.ThreadId := in_msg.ThreadId;
  196.          DPRINTF(RubySlicc, "%s\n", out_msg);
  197.        }
  198.      }
  199.    }
  200.  
  201.    action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
  202.      requestNetwork_in.dequeue();
  203.    }
  204.  
  205.    action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
  206.      peek(memQueue_in, MemoryMsg) {
  207.        enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
  208.          out_msg.Addr := address;
  209. diff -r d30cffa47f75 src/mem/protocol/MESI_CMP_directory-msg.sm
  210. --- a/src/mem/protocol/MESI_CMP_directory-msg.sm    Tue Apr 15 14:37:21 2014 -0400
  211. +++ b/src/mem/protocol/MESI_CMP_directory-msg.sm    Wed Apr 16 11:04:00 2014 -0400
  212. @@ -58,26 +58,28 @@
  213.  
  214.  // RequestMsg
  215.  structure(RequestMsg, desc="...", interface="NetworkMessage") {
  216.    Address Addr,              desc="Physical address for this request";
  217.    CoherenceRequestType Type,    desc="Type of request (GetS, GetX, PutX, etc)";
  218.    RubyAccessMode AccessMode,    desc="user/supervisor access type";
  219.    MachineID Requestor      ,    desc="What component request";
  220.    NetDest Destination,          desc="What components receive the request, includes MachineType and num";
  221.    MessageSizeType MessageSize,  desc="size category of the message";
  222.    DataBlock DataBlk,            desc="Data for the cache line (if PUTX)";
  223.    int Len;
  224.    bool Dirty, default="false",  desc="Dirty bit";
  225.    PrefetchBit Prefetch,         desc="Is this a prefetch request";
  226. +  Address ProgramCounter,       desc="PC that caused this request";
  227. +  int ThreadId,                 desc="Context ID of issuing request";
  228.  
  229.    bool functionalRead(Packet *pkt) {
  230.      // Only PUTX messages contains the data block
  231.      if (Type == CoherenceRequestType:PUTX) {
  232.          return testAndRead(Addr, DataBlk, pkt);
  233.      }
  234.  
  235.      return false;
  236.    }
  237.  
  238.    bool functionalWrite(Packet *pkt) {
  239.      // No check on message type required since the protocol should
  240.      // read data from those messages that contain the block
  241. diff -r d30cffa47f75 src/mem/protocol/RubySlicc_MemControl.sm
  242. --- a/src/mem/protocol/RubySlicc_MemControl.sm  Tue Apr 15 14:37:21 2014 -0400
  243. +++ b/src/mem/protocol/RubySlicc_MemControl.sm  Wed Apr 16 11:04:00 2014 -0400
  244. @@ -51,22 +51,24 @@
  245.  // Message to and from Memory Control
  246.  
  247.  structure(MemoryMsg, desc="...", interface="Message") {
  248.    Address Addr,              desc="Physical address for this request";
  249.    MemoryRequestType Type,       desc="Type of memory request (MEMORY_READ or MEMORY_WB)";
  250.    MachineID Sender,             desc="What component sent the data";
  251.    MachineID OriginalRequestorMachId, desc="What component originally requested";
  252.    DataBlock DataBlk,            desc="Data to writeback";
  253.    MessageSizeType MessageSize,  desc="size category of the message";
  254.    // Not all fields used by all protocols:
  255.    PrefetchBit Prefetch,         desc="Is this a prefetch request";
  256.    bool ReadX,                   desc="Exclusive";
  257.    int Acks,                     desc="How many acks to expect";
  258. +  Address ProgramCounter,       desc="Program Counter causing miss";
  259. +  int ThreadId,                 desc="Context ID of issuing request";
  260.  
  261.    bool functionalRead(Packet *pkt) {
  262.      return testAndRead(Addr, DataBlk, pkt);
  263.    }
  264.  
  265.    bool functionalWrite(Packet *pkt) {
  266.      return testAndWrite(Addr, DataBlk, pkt);
  267.    }
  268.  }
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!